1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * tools/testing/selftests/kvm/include/x86_64/processor.h
4  *
5  * Copyright (C) 2018, Google LLC.
6  */
7 
8 #ifndef SELFTEST_KVM_PROCESSOR_H
9 #define SELFTEST_KVM_PROCESSOR_H
10 
11 #include <assert.h>
12 #include <stdint.h>
13 
14 #include <asm/msr-index.h>
15 
16 #include "../kvm_util.h"
17 
18 #define X86_EFLAGS_FIXED	 (1u << 1)
19 
20 #define X86_CR4_VME		(1ul << 0)
21 #define X86_CR4_PVI		(1ul << 1)
22 #define X86_CR4_TSD		(1ul << 2)
23 #define X86_CR4_DE		(1ul << 3)
24 #define X86_CR4_PSE		(1ul << 4)
25 #define X86_CR4_PAE		(1ul << 5)
26 #define X86_CR4_MCE		(1ul << 6)
27 #define X86_CR4_PGE		(1ul << 7)
28 #define X86_CR4_PCE		(1ul << 8)
29 #define X86_CR4_OSFXSR		(1ul << 9)
30 #define X86_CR4_OSXMMEXCPT	(1ul << 10)
31 #define X86_CR4_UMIP		(1ul << 11)
32 #define X86_CR4_LA57		(1ul << 12)
33 #define X86_CR4_VMXE		(1ul << 13)
34 #define X86_CR4_SMXE		(1ul << 14)
35 #define X86_CR4_FSGSBASE	(1ul << 16)
36 #define X86_CR4_PCIDE		(1ul << 17)
37 #define X86_CR4_OSXSAVE		(1ul << 18)
38 #define X86_CR4_SMEP		(1ul << 20)
39 #define X86_CR4_SMAP		(1ul << 21)
40 #define X86_CR4_PKE		(1ul << 22)
41 
42 /* CPUID.1.ECX */
43 #define CPUID_VMX		(1ul << 5)
44 #define CPUID_SMX		(1ul << 6)
45 #define CPUID_PCID		(1ul << 17)
46 #define CPUID_XSAVE		(1ul << 26)
47 
48 /* CPUID.7.EBX */
49 #define CPUID_FSGSBASE		(1ul << 0)
50 #define CPUID_SMEP		(1ul << 7)
51 #define CPUID_SMAP		(1ul << 20)
52 
53 /* CPUID.7.ECX */
54 #define CPUID_UMIP		(1ul << 2)
55 #define CPUID_PKU		(1ul << 3)
56 #define CPUID_LA57		(1ul << 16)
57 
58 /* CPUID.0x8000_0001.EDX */
59 #define CPUID_GBPAGES		(1ul << 26)
60 
61 /* General Registers in 64-Bit Mode */
62 struct gpr64_regs {
63 	u64 rax;
64 	u64 rcx;
65 	u64 rdx;
66 	u64 rbx;
67 	u64 rsp;
68 	u64 rbp;
69 	u64 rsi;
70 	u64 rdi;
71 	u64 r8;
72 	u64 r9;
73 	u64 r10;
74 	u64 r11;
75 	u64 r12;
76 	u64 r13;
77 	u64 r14;
78 	u64 r15;
79 };
80 
81 struct desc64 {
82 	uint16_t limit0;
83 	uint16_t base0;
84 	unsigned base1:8, type:4, s:1, dpl:2, p:1;
85 	unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
86 	uint32_t base3;
87 	uint32_t zero1;
88 } __attribute__((packed));
89 
90 struct desc_ptr {
91 	uint16_t size;
92 	uint64_t address;
93 } __attribute__((packed));
94 
95 static inline uint64_t get_desc64_base(const struct desc64 *desc)
96 {
97 	return ((uint64_t)desc->base3 << 32) |
98 		(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
99 }
100 
101 static inline uint64_t rdtsc(void)
102 {
103 	uint32_t eax, edx;
104 	uint64_t tsc_val;
105 	/*
106 	 * The lfence is to wait (on Intel CPUs) until all previous
107 	 * instructions have been executed. If software requires RDTSC to be
108 	 * executed prior to execution of any subsequent instruction, it can
109 	 * execute LFENCE immediately after RDTSC
110 	 */
111 	__asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
112 	tsc_val = ((uint64_t)edx) << 32 | eax;
113 	return tsc_val;
114 }
115 
116 static inline uint64_t rdtscp(uint32_t *aux)
117 {
118 	uint32_t eax, edx;
119 
120 	__asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
121 	return ((uint64_t)edx) << 32 | eax;
122 }
123 
124 static inline uint64_t rdmsr(uint32_t msr)
125 {
126 	uint32_t a, d;
127 
128 	__asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
129 
130 	return a | ((uint64_t) d << 32);
131 }
132 
133 static inline void wrmsr(uint32_t msr, uint64_t value)
134 {
135 	uint32_t a = value;
136 	uint32_t d = value >> 32;
137 
138 	__asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
139 }
140 
141 
142 static inline uint16_t inw(uint16_t port)
143 {
144 	uint16_t tmp;
145 
146 	__asm__ __volatile__("in %%dx, %%ax"
147 		: /* output */ "=a" (tmp)
148 		: /* input */ "d" (port));
149 
150 	return tmp;
151 }
152 
153 static inline uint16_t get_es(void)
154 {
155 	uint16_t es;
156 
157 	__asm__ __volatile__("mov %%es, %[es]"
158 			     : /* output */ [es]"=rm"(es));
159 	return es;
160 }
161 
162 static inline uint16_t get_cs(void)
163 {
164 	uint16_t cs;
165 
166 	__asm__ __volatile__("mov %%cs, %[cs]"
167 			     : /* output */ [cs]"=rm"(cs));
168 	return cs;
169 }
170 
171 static inline uint16_t get_ss(void)
172 {
173 	uint16_t ss;
174 
175 	__asm__ __volatile__("mov %%ss, %[ss]"
176 			     : /* output */ [ss]"=rm"(ss));
177 	return ss;
178 }
179 
180 static inline uint16_t get_ds(void)
181 {
182 	uint16_t ds;
183 
184 	__asm__ __volatile__("mov %%ds, %[ds]"
185 			     : /* output */ [ds]"=rm"(ds));
186 	return ds;
187 }
188 
189 static inline uint16_t get_fs(void)
190 {
191 	uint16_t fs;
192 
193 	__asm__ __volatile__("mov %%fs, %[fs]"
194 			     : /* output */ [fs]"=rm"(fs));
195 	return fs;
196 }
197 
198 static inline uint16_t get_gs(void)
199 {
200 	uint16_t gs;
201 
202 	__asm__ __volatile__("mov %%gs, %[gs]"
203 			     : /* output */ [gs]"=rm"(gs));
204 	return gs;
205 }
206 
207 static inline uint16_t get_tr(void)
208 {
209 	uint16_t tr;
210 
211 	__asm__ __volatile__("str %[tr]"
212 			     : /* output */ [tr]"=rm"(tr));
213 	return tr;
214 }
215 
216 static inline uint64_t get_cr0(void)
217 {
218 	uint64_t cr0;
219 
220 	__asm__ __volatile__("mov %%cr0, %[cr0]"
221 			     : /* output */ [cr0]"=r"(cr0));
222 	return cr0;
223 }
224 
225 static inline uint64_t get_cr3(void)
226 {
227 	uint64_t cr3;
228 
229 	__asm__ __volatile__("mov %%cr3, %[cr3]"
230 			     : /* output */ [cr3]"=r"(cr3));
231 	return cr3;
232 }
233 
234 static inline uint64_t get_cr4(void)
235 {
236 	uint64_t cr4;
237 
238 	__asm__ __volatile__("mov %%cr4, %[cr4]"
239 			     : /* output */ [cr4]"=r"(cr4));
240 	return cr4;
241 }
242 
243 static inline void set_cr4(uint64_t val)
244 {
245 	__asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
246 }
247 
248 static inline struct desc_ptr get_gdt(void)
249 {
250 	struct desc_ptr gdt;
251 	__asm__ __volatile__("sgdt %[gdt]"
252 			     : /* output */ [gdt]"=m"(gdt));
253 	return gdt;
254 }
255 
256 static inline struct desc_ptr get_idt(void)
257 {
258 	struct desc_ptr idt;
259 	__asm__ __volatile__("sidt %[idt]"
260 			     : /* output */ [idt]"=m"(idt));
261 	return idt;
262 }
263 
264 static inline void outl(uint16_t port, uint32_t value)
265 {
266 	__asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
267 }
268 
269 static inline void cpuid(uint32_t *eax, uint32_t *ebx,
270 			 uint32_t *ecx, uint32_t *edx)
271 {
272 	/* ecx is often an input as well as an output. */
273 	asm volatile("cpuid"
274 	    : "=a" (*eax),
275 	      "=b" (*ebx),
276 	      "=c" (*ecx),
277 	      "=d" (*edx)
278 	    : "0" (*eax), "2" (*ecx)
279 	    : "memory");
280 }
281 
282 #define SET_XMM(__var, __xmm) \
283 	asm volatile("movq %0, %%"#__xmm : : "r"(__var) : #__xmm)
284 
285 static inline void set_xmm(int n, unsigned long val)
286 {
287 	switch (n) {
288 	case 0:
289 		SET_XMM(val, xmm0);
290 		break;
291 	case 1:
292 		SET_XMM(val, xmm1);
293 		break;
294 	case 2:
295 		SET_XMM(val, xmm2);
296 		break;
297 	case 3:
298 		SET_XMM(val, xmm3);
299 		break;
300 	case 4:
301 		SET_XMM(val, xmm4);
302 		break;
303 	case 5:
304 		SET_XMM(val, xmm5);
305 		break;
306 	case 6:
307 		SET_XMM(val, xmm6);
308 		break;
309 	case 7:
310 		SET_XMM(val, xmm7);
311 		break;
312 	}
313 }
314 
315 typedef unsigned long v1di __attribute__ ((vector_size (8)));
316 static inline unsigned long get_xmm(int n)
317 {
318 	assert(n >= 0 && n <= 7);
319 
320 	register v1di xmm0 __asm__("%xmm0");
321 	register v1di xmm1 __asm__("%xmm1");
322 	register v1di xmm2 __asm__("%xmm2");
323 	register v1di xmm3 __asm__("%xmm3");
324 	register v1di xmm4 __asm__("%xmm4");
325 	register v1di xmm5 __asm__("%xmm5");
326 	register v1di xmm6 __asm__("%xmm6");
327 	register v1di xmm7 __asm__("%xmm7");
328 	switch (n) {
329 	case 0:
330 		return (unsigned long)xmm0;
331 	case 1:
332 		return (unsigned long)xmm1;
333 	case 2:
334 		return (unsigned long)xmm2;
335 	case 3:
336 		return (unsigned long)xmm3;
337 	case 4:
338 		return (unsigned long)xmm4;
339 	case 5:
340 		return (unsigned long)xmm5;
341 	case 6:
342 		return (unsigned long)xmm6;
343 	case 7:
344 		return (unsigned long)xmm7;
345 	}
346 	return 0;
347 }
348 
349 bool is_intel_cpu(void);
350 
351 struct kvm_x86_state;
352 struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid);
353 void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid,
354 		     struct kvm_x86_state *state);
355 
356 struct kvm_msr_list *kvm_get_msr_index_list(void);
357 uint64_t kvm_get_feature_msr(uint64_t msr_index);
358 struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
359 
360 struct kvm_cpuid2 *vcpu_get_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
361 void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
362 		    struct kvm_cpuid2 *cpuid);
363 
364 struct kvm_cpuid_entry2 *
365 kvm_get_supported_cpuid_index(uint32_t function, uint32_t index);
366 
367 static inline struct kvm_cpuid_entry2 *
368 kvm_get_supported_cpuid_entry(uint32_t function)
369 {
370 	return kvm_get_supported_cpuid_index(function, 0);
371 }
372 
373 uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index);
374 int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
375 		  uint64_t msr_value);
376 void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
377 	  	  uint64_t msr_value);
378 
379 uint32_t kvm_get_cpuid_max_basic(void);
380 uint32_t kvm_get_cpuid_max_extended(void);
381 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
382 
383 struct ex_regs {
384 	uint64_t rax, rcx, rdx, rbx;
385 	uint64_t rbp, rsi, rdi;
386 	uint64_t r8, r9, r10, r11;
387 	uint64_t r12, r13, r14, r15;
388 	uint64_t vector;
389 	uint64_t error_code;
390 	uint64_t rip;
391 	uint64_t cs;
392 	uint64_t rflags;
393 };
394 
395 void vm_init_descriptor_tables(struct kvm_vm *vm);
396 void vcpu_init_descriptor_tables(struct kvm_vm *vm, uint32_t vcpuid);
397 void vm_install_exception_handler(struct kvm_vm *vm, int vector,
398 			void (*handler)(struct ex_regs *));
399 
400 uint64_t vm_get_page_table_entry(struct kvm_vm *vm, int vcpuid, uint64_t vaddr);
401 void vm_set_page_table_entry(struct kvm_vm *vm, int vcpuid, uint64_t vaddr,
402 			     uint64_t pte);
403 
404 /*
405  * set_cpuid() - overwrites a matching cpuid entry with the provided value.
406  *		 matches based on ent->function && ent->index. returns true
407  *		 if a match was found and successfully overwritten.
408  * @cpuid: the kvm cpuid list to modify.
409  * @ent: cpuid entry to insert
410  */
411 bool set_cpuid(struct kvm_cpuid2 *cpuid, struct kvm_cpuid_entry2 *ent);
412 
413 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
414 		       uint64_t a3);
415 
416 struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void);
417 void vcpu_set_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
418 struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
419 
420 enum x86_page_size {
421 	X86_PAGE_SIZE_4K = 0,
422 	X86_PAGE_SIZE_2M,
423 	X86_PAGE_SIZE_1G,
424 };
425 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
426 		   enum x86_page_size page_size);
427 
428 /*
429  * Basic CPU control in CR0
430  */
431 #define X86_CR0_PE          (1UL<<0) /* Protection Enable */
432 #define X86_CR0_MP          (1UL<<1) /* Monitor Coprocessor */
433 #define X86_CR0_EM          (1UL<<2) /* Emulation */
434 #define X86_CR0_TS          (1UL<<3) /* Task Switched */
435 #define X86_CR0_ET          (1UL<<4) /* Extension Type */
436 #define X86_CR0_NE          (1UL<<5) /* Numeric Error */
437 #define X86_CR0_WP          (1UL<<16) /* Write Protect */
438 #define X86_CR0_AM          (1UL<<18) /* Alignment Mask */
439 #define X86_CR0_NW          (1UL<<29) /* Not Write-through */
440 #define X86_CR0_CD          (1UL<<30) /* Cache Disable */
441 #define X86_CR0_PG          (1UL<<31) /* Paging */
442 
443 /* VMX_EPT_VPID_CAP bits */
444 #define VMX_EPT_VPID_CAP_AD_BITS       (1ULL << 21)
445 
446 #endif /* SELFTEST_KVM_PROCESSOR_H */
447