1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * tools/testing/selftests/kvm/include/x86_64/processor.h
4  *
5  * Copyright (C) 2018, Google LLC.
6  */
7 
8 #ifndef SELFTEST_KVM_PROCESSOR_H
9 #define SELFTEST_KVM_PROCESSOR_H
10 
11 #include <assert.h>
12 #include <stdint.h>
13 #include <syscall.h>
14 
15 #include <asm/msr-index.h>
16 #include <asm/prctl.h>
17 
18 #include "../kvm_util.h"
19 
20 #define X86_EFLAGS_FIXED	 (1u << 1)
21 
22 #define X86_CR4_VME		(1ul << 0)
23 #define X86_CR4_PVI		(1ul << 1)
24 #define X86_CR4_TSD		(1ul << 2)
25 #define X86_CR4_DE		(1ul << 3)
26 #define X86_CR4_PSE		(1ul << 4)
27 #define X86_CR4_PAE		(1ul << 5)
28 #define X86_CR4_MCE		(1ul << 6)
29 #define X86_CR4_PGE		(1ul << 7)
30 #define X86_CR4_PCE		(1ul << 8)
31 #define X86_CR4_OSFXSR		(1ul << 9)
32 #define X86_CR4_OSXMMEXCPT	(1ul << 10)
33 #define X86_CR4_UMIP		(1ul << 11)
34 #define X86_CR4_LA57		(1ul << 12)
35 #define X86_CR4_VMXE		(1ul << 13)
36 #define X86_CR4_SMXE		(1ul << 14)
37 #define X86_CR4_FSGSBASE	(1ul << 16)
38 #define X86_CR4_PCIDE		(1ul << 17)
39 #define X86_CR4_OSXSAVE		(1ul << 18)
40 #define X86_CR4_SMEP		(1ul << 20)
41 #define X86_CR4_SMAP		(1ul << 21)
42 #define X86_CR4_PKE		(1ul << 22)
43 
44 /* CPUID.1.ECX */
45 #define CPUID_VMX		(1ul << 5)
46 #define CPUID_SMX		(1ul << 6)
47 #define CPUID_PCID		(1ul << 17)
48 #define CPUID_XSAVE		(1ul << 26)
49 
50 /* CPUID.7.EBX */
51 #define CPUID_FSGSBASE		(1ul << 0)
52 #define CPUID_SMEP		(1ul << 7)
53 #define CPUID_SMAP		(1ul << 20)
54 
55 /* CPUID.7.ECX */
56 #define CPUID_UMIP		(1ul << 2)
57 #define CPUID_PKU		(1ul << 3)
58 #define CPUID_LA57		(1ul << 16)
59 
60 /* CPUID.0x8000_0001.EDX */
61 #define CPUID_GBPAGES		(1ul << 26)
62 
63 /* General Registers in 64-Bit Mode */
64 struct gpr64_regs {
65 	u64 rax;
66 	u64 rcx;
67 	u64 rdx;
68 	u64 rbx;
69 	u64 rsp;
70 	u64 rbp;
71 	u64 rsi;
72 	u64 rdi;
73 	u64 r8;
74 	u64 r9;
75 	u64 r10;
76 	u64 r11;
77 	u64 r12;
78 	u64 r13;
79 	u64 r14;
80 	u64 r15;
81 };
82 
83 struct desc64 {
84 	uint16_t limit0;
85 	uint16_t base0;
86 	unsigned base1:8, type:4, s:1, dpl:2, p:1;
87 	unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
88 	uint32_t base3;
89 	uint32_t zero1;
90 } __attribute__((packed));
91 
92 struct desc_ptr {
93 	uint16_t size;
94 	uint64_t address;
95 } __attribute__((packed));
96 
97 struct kvm_x86_state {
98 	struct kvm_xsave *xsave;
99 	struct kvm_vcpu_events events;
100 	struct kvm_mp_state mp_state;
101 	struct kvm_regs regs;
102 	struct kvm_xcrs xcrs;
103 	struct kvm_sregs sregs;
104 	struct kvm_debugregs debugregs;
105 	union {
106 		struct kvm_nested_state nested;
107 		char nested_[16384];
108 	};
109 	struct kvm_msrs msrs;
110 };
111 
112 static inline uint64_t get_desc64_base(const struct desc64 *desc)
113 {
114 	return ((uint64_t)desc->base3 << 32) |
115 		(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
116 }
117 
118 static inline uint64_t rdtsc(void)
119 {
120 	uint32_t eax, edx;
121 	uint64_t tsc_val;
122 	/*
123 	 * The lfence is to wait (on Intel CPUs) until all previous
124 	 * instructions have been executed. If software requires RDTSC to be
125 	 * executed prior to execution of any subsequent instruction, it can
126 	 * execute LFENCE immediately after RDTSC
127 	 */
128 	__asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
129 	tsc_val = ((uint64_t)edx) << 32 | eax;
130 	return tsc_val;
131 }
132 
133 static inline uint64_t rdtscp(uint32_t *aux)
134 {
135 	uint32_t eax, edx;
136 
137 	__asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
138 	return ((uint64_t)edx) << 32 | eax;
139 }
140 
141 static inline uint64_t rdmsr(uint32_t msr)
142 {
143 	uint32_t a, d;
144 
145 	__asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
146 
147 	return a | ((uint64_t) d << 32);
148 }
149 
150 static inline void wrmsr(uint32_t msr, uint64_t value)
151 {
152 	uint32_t a = value;
153 	uint32_t d = value >> 32;
154 
155 	__asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
156 }
157 
158 
159 static inline uint16_t inw(uint16_t port)
160 {
161 	uint16_t tmp;
162 
163 	__asm__ __volatile__("in %%dx, %%ax"
164 		: /* output */ "=a" (tmp)
165 		: /* input */ "d" (port));
166 
167 	return tmp;
168 }
169 
170 static inline uint16_t get_es(void)
171 {
172 	uint16_t es;
173 
174 	__asm__ __volatile__("mov %%es, %[es]"
175 			     : /* output */ [es]"=rm"(es));
176 	return es;
177 }
178 
179 static inline uint16_t get_cs(void)
180 {
181 	uint16_t cs;
182 
183 	__asm__ __volatile__("mov %%cs, %[cs]"
184 			     : /* output */ [cs]"=rm"(cs));
185 	return cs;
186 }
187 
188 static inline uint16_t get_ss(void)
189 {
190 	uint16_t ss;
191 
192 	__asm__ __volatile__("mov %%ss, %[ss]"
193 			     : /* output */ [ss]"=rm"(ss));
194 	return ss;
195 }
196 
197 static inline uint16_t get_ds(void)
198 {
199 	uint16_t ds;
200 
201 	__asm__ __volatile__("mov %%ds, %[ds]"
202 			     : /* output */ [ds]"=rm"(ds));
203 	return ds;
204 }
205 
206 static inline uint16_t get_fs(void)
207 {
208 	uint16_t fs;
209 
210 	__asm__ __volatile__("mov %%fs, %[fs]"
211 			     : /* output */ [fs]"=rm"(fs));
212 	return fs;
213 }
214 
215 static inline uint16_t get_gs(void)
216 {
217 	uint16_t gs;
218 
219 	__asm__ __volatile__("mov %%gs, %[gs]"
220 			     : /* output */ [gs]"=rm"(gs));
221 	return gs;
222 }
223 
224 static inline uint16_t get_tr(void)
225 {
226 	uint16_t tr;
227 
228 	__asm__ __volatile__("str %[tr]"
229 			     : /* output */ [tr]"=rm"(tr));
230 	return tr;
231 }
232 
233 static inline uint64_t get_cr0(void)
234 {
235 	uint64_t cr0;
236 
237 	__asm__ __volatile__("mov %%cr0, %[cr0]"
238 			     : /* output */ [cr0]"=r"(cr0));
239 	return cr0;
240 }
241 
242 static inline uint64_t get_cr3(void)
243 {
244 	uint64_t cr3;
245 
246 	__asm__ __volatile__("mov %%cr3, %[cr3]"
247 			     : /* output */ [cr3]"=r"(cr3));
248 	return cr3;
249 }
250 
251 static inline uint64_t get_cr4(void)
252 {
253 	uint64_t cr4;
254 
255 	__asm__ __volatile__("mov %%cr4, %[cr4]"
256 			     : /* output */ [cr4]"=r"(cr4));
257 	return cr4;
258 }
259 
260 static inline void set_cr4(uint64_t val)
261 {
262 	__asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
263 }
264 
265 static inline struct desc_ptr get_gdt(void)
266 {
267 	struct desc_ptr gdt;
268 	__asm__ __volatile__("sgdt %[gdt]"
269 			     : /* output */ [gdt]"=m"(gdt));
270 	return gdt;
271 }
272 
273 static inline struct desc_ptr get_idt(void)
274 {
275 	struct desc_ptr idt;
276 	__asm__ __volatile__("sidt %[idt]"
277 			     : /* output */ [idt]"=m"(idt));
278 	return idt;
279 }
280 
281 static inline void outl(uint16_t port, uint32_t value)
282 {
283 	__asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
284 }
285 
286 static inline void cpuid(uint32_t *eax, uint32_t *ebx,
287 			 uint32_t *ecx, uint32_t *edx)
288 {
289 	/* ecx is often an input as well as an output. */
290 	asm volatile("cpuid"
291 	    : "=a" (*eax),
292 	      "=b" (*ebx),
293 	      "=c" (*ecx),
294 	      "=d" (*edx)
295 	    : "0" (*eax), "2" (*ecx)
296 	    : "memory");
297 }
298 
299 #define SET_XMM(__var, __xmm) \
300 	asm volatile("movq %0, %%"#__xmm : : "r"(__var) : #__xmm)
301 
302 static inline void set_xmm(int n, unsigned long val)
303 {
304 	switch (n) {
305 	case 0:
306 		SET_XMM(val, xmm0);
307 		break;
308 	case 1:
309 		SET_XMM(val, xmm1);
310 		break;
311 	case 2:
312 		SET_XMM(val, xmm2);
313 		break;
314 	case 3:
315 		SET_XMM(val, xmm3);
316 		break;
317 	case 4:
318 		SET_XMM(val, xmm4);
319 		break;
320 	case 5:
321 		SET_XMM(val, xmm5);
322 		break;
323 	case 6:
324 		SET_XMM(val, xmm6);
325 		break;
326 	case 7:
327 		SET_XMM(val, xmm7);
328 		break;
329 	}
330 }
331 
332 #define GET_XMM(__xmm)							\
333 ({									\
334 	unsigned long __val;						\
335 	asm volatile("movq %%"#__xmm", %0" : "=r"(__val));		\
336 	__val;								\
337 })
338 
339 static inline unsigned long get_xmm(int n)
340 {
341 	assert(n >= 0 && n <= 7);
342 
343 	switch (n) {
344 	case 0:
345 		return GET_XMM(xmm0);
346 	case 1:
347 		return GET_XMM(xmm1);
348 	case 2:
349 		return GET_XMM(xmm2);
350 	case 3:
351 		return GET_XMM(xmm3);
352 	case 4:
353 		return GET_XMM(xmm4);
354 	case 5:
355 		return GET_XMM(xmm5);
356 	case 6:
357 		return GET_XMM(xmm6);
358 	case 7:
359 		return GET_XMM(xmm7);
360 	}
361 
362 	/* never reached */
363 	return 0;
364 }
365 
366 bool is_intel_cpu(void);
367 bool is_amd_cpu(void);
368 
369 static inline unsigned int x86_family(unsigned int eax)
370 {
371 	unsigned int x86;
372 
373 	x86 = (eax >> 8) & 0xf;
374 
375 	if (x86 == 0xf)
376 		x86 += (eax >> 20) & 0xff;
377 
378 	return x86;
379 }
380 
381 static inline unsigned int x86_model(unsigned int eax)
382 {
383 	return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f);
384 }
385 
386 struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid);
387 void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid,
388 		     struct kvm_x86_state *state);
389 void kvm_x86_state_cleanup(struct kvm_x86_state *state);
390 
391 struct kvm_msr_list *kvm_get_msr_index_list(void);
392 uint64_t kvm_get_feature_msr(uint64_t msr_index);
393 struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
394 
395 struct kvm_cpuid2 *vcpu_get_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
396 int __vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
397 		     struct kvm_cpuid2 *cpuid);
398 void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
399 		    struct kvm_cpuid2 *cpuid);
400 
401 struct kvm_cpuid_entry2 *
402 kvm_get_supported_cpuid_index(uint32_t function, uint32_t index);
403 
404 static inline struct kvm_cpuid_entry2 *
405 kvm_get_supported_cpuid_entry(uint32_t function)
406 {
407 	return kvm_get_supported_cpuid_index(function, 0);
408 }
409 
410 uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index);
411 int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
412 		  uint64_t msr_value);
413 void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
414 	  	  uint64_t msr_value);
415 
416 uint32_t kvm_get_cpuid_max_basic(void);
417 uint32_t kvm_get_cpuid_max_extended(void);
418 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
419 
420 struct ex_regs {
421 	uint64_t rax, rcx, rdx, rbx;
422 	uint64_t rbp, rsi, rdi;
423 	uint64_t r8, r9, r10, r11;
424 	uint64_t r12, r13, r14, r15;
425 	uint64_t vector;
426 	uint64_t error_code;
427 	uint64_t rip;
428 	uint64_t cs;
429 	uint64_t rflags;
430 };
431 
432 void vm_init_descriptor_tables(struct kvm_vm *vm);
433 void vcpu_init_descriptor_tables(struct kvm_vm *vm, uint32_t vcpuid);
434 void vm_install_exception_handler(struct kvm_vm *vm, int vector,
435 			void (*handler)(struct ex_regs *));
436 
437 uint64_t vm_get_page_table_entry(struct kvm_vm *vm, int vcpuid, uint64_t vaddr);
438 void vm_set_page_table_entry(struct kvm_vm *vm, int vcpuid, uint64_t vaddr,
439 			     uint64_t pte);
440 
441 /*
442  * get_cpuid() - find matching CPUID entry and return pointer to it.
443  */
444 struct kvm_cpuid_entry2 *get_cpuid(struct kvm_cpuid2 *cpuid, uint32_t function,
445 				   uint32_t index);
446 /*
447  * set_cpuid() - overwrites a matching cpuid entry with the provided value.
448  *		 matches based on ent->function && ent->index. returns true
449  *		 if a match was found and successfully overwritten.
450  * @cpuid: the kvm cpuid list to modify.
451  * @ent: cpuid entry to insert
452  */
453 bool set_cpuid(struct kvm_cpuid2 *cpuid, struct kvm_cpuid_entry2 *ent);
454 
455 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
456 		       uint64_t a3);
457 
458 struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void);
459 void vcpu_set_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
460 struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
461 
462 enum x86_page_size {
463 	X86_PAGE_SIZE_4K = 0,
464 	X86_PAGE_SIZE_2M,
465 	X86_PAGE_SIZE_1G,
466 };
467 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
468 		   enum x86_page_size page_size);
469 
470 /*
471  * Basic CPU control in CR0
472  */
473 #define X86_CR0_PE          (1UL<<0) /* Protection Enable */
474 #define X86_CR0_MP          (1UL<<1) /* Monitor Coprocessor */
475 #define X86_CR0_EM          (1UL<<2) /* Emulation */
476 #define X86_CR0_TS          (1UL<<3) /* Task Switched */
477 #define X86_CR0_ET          (1UL<<4) /* Extension Type */
478 #define X86_CR0_NE          (1UL<<5) /* Numeric Error */
479 #define X86_CR0_WP          (1UL<<16) /* Write Protect */
480 #define X86_CR0_AM          (1UL<<18) /* Alignment Mask */
481 #define X86_CR0_NW          (1UL<<29) /* Not Write-through */
482 #define X86_CR0_CD          (1UL<<30) /* Cache Disable */
483 #define X86_CR0_PG          (1UL<<31) /* Paging */
484 
485 /* VMX_EPT_VPID_CAP bits */
486 #define VMX_EPT_VPID_CAP_AD_BITS       (1ULL << 21)
487 
488 #define XSTATE_XTILE_CFG_BIT		17
489 #define XSTATE_XTILE_DATA_BIT		18
490 
491 #define XSTATE_XTILE_CFG_MASK		(1ULL << XSTATE_XTILE_CFG_BIT)
492 #define XSTATE_XTILE_DATA_MASK		(1ULL << XSTATE_XTILE_DATA_BIT)
493 #define XFEATURE_XTILE_MASK		(XSTATE_XTILE_CFG_MASK | \
494 					XSTATE_XTILE_DATA_MASK)
495 #endif /* SELFTEST_KVM_PROCESSOR_H */
496