1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * tools/testing/selftests/kvm/include/x86_64/processor.h 4 * 5 * Copyright (C) 2018, Google LLC. 6 */ 7 8 #ifndef SELFTEST_KVM_PROCESSOR_H 9 #define SELFTEST_KVM_PROCESSOR_H 10 11 #include <assert.h> 12 #include <stdint.h> 13 #include <syscall.h> 14 15 #include <asm/msr-index.h> 16 #include <asm/prctl.h> 17 18 #include <linux/stringify.h> 19 20 #include "../kvm_util.h" 21 22 extern bool host_cpu_is_intel; 23 extern bool host_cpu_is_amd; 24 25 #define NMI_VECTOR 0x02 26 27 #define X86_EFLAGS_FIXED (1u << 1) 28 29 #define X86_CR4_VME (1ul << 0) 30 #define X86_CR4_PVI (1ul << 1) 31 #define X86_CR4_TSD (1ul << 2) 32 #define X86_CR4_DE (1ul << 3) 33 #define X86_CR4_PSE (1ul << 4) 34 #define X86_CR4_PAE (1ul << 5) 35 #define X86_CR4_MCE (1ul << 6) 36 #define X86_CR4_PGE (1ul << 7) 37 #define X86_CR4_PCE (1ul << 8) 38 #define X86_CR4_OSFXSR (1ul << 9) 39 #define X86_CR4_OSXMMEXCPT (1ul << 10) 40 #define X86_CR4_UMIP (1ul << 11) 41 #define X86_CR4_LA57 (1ul << 12) 42 #define X86_CR4_VMXE (1ul << 13) 43 #define X86_CR4_SMXE (1ul << 14) 44 #define X86_CR4_FSGSBASE (1ul << 16) 45 #define X86_CR4_PCIDE (1ul << 17) 46 #define X86_CR4_OSXSAVE (1ul << 18) 47 #define X86_CR4_SMEP (1ul << 20) 48 #define X86_CR4_SMAP (1ul << 21) 49 #define X86_CR4_PKE (1ul << 22) 50 51 struct xstate_header { 52 u64 xstate_bv; 53 u64 xcomp_bv; 54 u64 reserved[6]; 55 } __attribute__((packed)); 56 57 struct xstate { 58 u8 i387[512]; 59 struct xstate_header header; 60 u8 extended_state_area[0]; 61 } __attribute__ ((packed, aligned (64))); 62 63 #define XFEATURE_MASK_FP BIT_ULL(0) 64 #define XFEATURE_MASK_SSE BIT_ULL(1) 65 #define XFEATURE_MASK_YMM BIT_ULL(2) 66 #define XFEATURE_MASK_BNDREGS BIT_ULL(3) 67 #define XFEATURE_MASK_BNDCSR BIT_ULL(4) 68 #define XFEATURE_MASK_OPMASK BIT_ULL(5) 69 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) 70 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) 71 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) 72 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) 73 74 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ 75 XFEATURE_MASK_ZMM_Hi256 | \ 76 XFEATURE_MASK_Hi16_ZMM) 77 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ 78 XFEATURE_MASK_XTILE_CFG) 79 80 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */ 81 enum cpuid_output_regs { 82 KVM_CPUID_EAX, 83 KVM_CPUID_EBX, 84 KVM_CPUID_ECX, 85 KVM_CPUID_EDX 86 }; 87 88 /* 89 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 90 * passed by value with no overhead. 91 */ 92 struct kvm_x86_cpu_feature { 93 u32 function; 94 u16 index; 95 u8 reg; 96 u8 bit; 97 }; 98 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 99 ({ \ 100 struct kvm_x86_cpu_feature feature = { \ 101 .function = fn, \ 102 .index = idx, \ 103 .reg = KVM_CPUID_##gpr, \ 104 .bit = __bit, \ 105 }; \ 106 \ 107 kvm_static_assert((fn & 0xc0000000) == 0 || \ 108 (fn & 0xc0000000) == 0x40000000 || \ 109 (fn & 0xc0000000) == 0x80000000 || \ 110 (fn & 0xc0000000) == 0xc0000000); \ 111 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 112 feature; \ 113 }) 114 115 /* 116 * Basic Leafs, a.k.a. Intel defined 117 */ 118 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3) 119 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5) 120 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6) 121 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15) 122 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17) 123 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21) 124 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22) 125 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24) 126 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26) 127 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27) 128 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30) 129 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31) 130 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6) 131 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7) 132 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9) 133 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19) 134 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25) 135 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26) 136 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0) 137 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1) 138 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2) 139 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4) 140 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7) 141 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10) 142 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11) 143 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14) 144 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20) 145 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22) 146 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23) 147 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24) 148 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2) 149 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3) 150 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16) 151 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22) 152 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30) 153 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7) 154 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20) 155 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24) 156 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26) 157 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29) 158 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31) 159 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17) 160 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18) 161 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3) 162 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4) 163 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2) 164 165 /* 166 * Extended Leafs, a.k.a. AMD defined 167 */ 168 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 169 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 170 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 171 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 172 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 173 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) 174 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 175 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 176 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 177 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 178 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 179 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 180 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 181 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 182 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 183 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) 184 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) 185 186 /* 187 * KVM defined paravirt features. 188 */ 189 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0) 190 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1) 191 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2) 192 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3) 193 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 194 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5) 195 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6) 196 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7) 197 /* Bit 8 apparently isn't used?!?! */ 198 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9) 199 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10) 200 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11) 201 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12) 202 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13) 203 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 204 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15) 205 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16) 206 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17) 207 208 /* 209 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 210 * value/property as opposed to a single-bit feature. Again, pack the info 211 * into a 64-bit value to pass by value with no overhead. 212 */ 213 struct kvm_x86_cpu_property { 214 u32 function; 215 u8 index; 216 u8 reg; 217 u8 lo_bit; 218 u8 hi_bit; 219 }; 220 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 221 ({ \ 222 struct kvm_x86_cpu_property property = { \ 223 .function = fn, \ 224 .index = idx, \ 225 .reg = KVM_CPUID_##gpr, \ 226 .lo_bit = low_bit, \ 227 .hi_bit = high_bit, \ 228 }; \ 229 \ 230 kvm_static_assert(low_bit < high_bit); \ 231 kvm_static_assert((fn & 0xc0000000) == 0 || \ 232 (fn & 0xc0000000) == 0x40000000 || \ 233 (fn & 0xc0000000) == 0x80000000 || \ 234 (fn & 0xc0000000) == 0xc0000000); \ 235 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 236 property; \ 237 }) 238 239 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 240 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 241 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 242 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 243 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 244 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7) 245 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 246 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 247 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 248 249 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 250 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 251 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 252 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 253 254 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 255 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 256 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 257 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 258 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 259 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 260 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 261 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 262 263 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 264 265 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 266 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 267 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 268 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 269 270 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 271 272 /* 273 * Intel's architectural PMU events are bizarre. They have a "feature" bit 274 * that indicates the feature is _not_ supported, and a property that states 275 * the length of the bit mask of unsupported features. A feature is supported 276 * if the size of the bit mask is larger than the "unavailable" bit, and said 277 * bit is not set. 278 * 279 * Wrap the "unavailable" feature to simplify checking whether or not a given 280 * architectural event is supported. 281 */ 282 struct kvm_x86_pmu_feature { 283 struct kvm_x86_cpu_feature anti_feature; 284 }; 285 #define KVM_X86_PMU_FEATURE(name, __bit) \ 286 ({ \ 287 struct kvm_x86_pmu_feature feature = { \ 288 .anti_feature = KVM_X86_CPU_FEATURE(0xa, 0, EBX, __bit), \ 289 }; \ 290 \ 291 feature; \ 292 }) 293 294 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(BRANCH_INSNS_RETIRED, 5) 295 296 static inline unsigned int x86_family(unsigned int eax) 297 { 298 unsigned int x86; 299 300 x86 = (eax >> 8) & 0xf; 301 302 if (x86 == 0xf) 303 x86 += (eax >> 20) & 0xff; 304 305 return x86; 306 } 307 308 static inline unsigned int x86_model(unsigned int eax) 309 { 310 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); 311 } 312 313 /* Page table bitfield declarations */ 314 #define PTE_PRESENT_MASK BIT_ULL(0) 315 #define PTE_WRITABLE_MASK BIT_ULL(1) 316 #define PTE_USER_MASK BIT_ULL(2) 317 #define PTE_ACCESSED_MASK BIT_ULL(5) 318 #define PTE_DIRTY_MASK BIT_ULL(6) 319 #define PTE_LARGE_MASK BIT_ULL(7) 320 #define PTE_GLOBAL_MASK BIT_ULL(8) 321 #define PTE_NX_MASK BIT_ULL(63) 322 323 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12) 324 325 #define PAGE_SHIFT 12 326 #define PAGE_SIZE (1ULL << PAGE_SHIFT) 327 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK) 328 329 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9)) 330 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x)) 331 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK) 332 333 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK) 334 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT) 335 336 /* General Registers in 64-Bit Mode */ 337 struct gpr64_regs { 338 u64 rax; 339 u64 rcx; 340 u64 rdx; 341 u64 rbx; 342 u64 rsp; 343 u64 rbp; 344 u64 rsi; 345 u64 rdi; 346 u64 r8; 347 u64 r9; 348 u64 r10; 349 u64 r11; 350 u64 r12; 351 u64 r13; 352 u64 r14; 353 u64 r15; 354 }; 355 356 struct desc64 { 357 uint16_t limit0; 358 uint16_t base0; 359 unsigned base1:8, type:4, s:1, dpl:2, p:1; 360 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; 361 uint32_t base3; 362 uint32_t zero1; 363 } __attribute__((packed)); 364 365 struct desc_ptr { 366 uint16_t size; 367 uint64_t address; 368 } __attribute__((packed)); 369 370 struct kvm_x86_state { 371 struct kvm_xsave *xsave; 372 struct kvm_vcpu_events events; 373 struct kvm_mp_state mp_state; 374 struct kvm_regs regs; 375 struct kvm_xcrs xcrs; 376 struct kvm_sregs sregs; 377 struct kvm_debugregs debugregs; 378 union { 379 struct kvm_nested_state nested; 380 char nested_[16384]; 381 }; 382 struct kvm_msrs msrs; 383 }; 384 385 static inline uint64_t get_desc64_base(const struct desc64 *desc) 386 { 387 return ((uint64_t)desc->base3 << 32) | 388 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 389 } 390 391 static inline uint64_t rdtsc(void) 392 { 393 uint32_t eax, edx; 394 uint64_t tsc_val; 395 /* 396 * The lfence is to wait (on Intel CPUs) until all previous 397 * instructions have been executed. If software requires RDTSC to be 398 * executed prior to execution of any subsequent instruction, it can 399 * execute LFENCE immediately after RDTSC 400 */ 401 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 402 tsc_val = ((uint64_t)edx) << 32 | eax; 403 return tsc_val; 404 } 405 406 static inline uint64_t rdtscp(uint32_t *aux) 407 { 408 uint32_t eax, edx; 409 410 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); 411 return ((uint64_t)edx) << 32 | eax; 412 } 413 414 static inline uint64_t rdmsr(uint32_t msr) 415 { 416 uint32_t a, d; 417 418 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); 419 420 return a | ((uint64_t) d << 32); 421 } 422 423 static inline void wrmsr(uint32_t msr, uint64_t value) 424 { 425 uint32_t a = value; 426 uint32_t d = value >> 32; 427 428 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); 429 } 430 431 432 static inline uint16_t inw(uint16_t port) 433 { 434 uint16_t tmp; 435 436 __asm__ __volatile__("in %%dx, %%ax" 437 : /* output */ "=a" (tmp) 438 : /* input */ "d" (port)); 439 440 return tmp; 441 } 442 443 static inline uint16_t get_es(void) 444 { 445 uint16_t es; 446 447 __asm__ __volatile__("mov %%es, %[es]" 448 : /* output */ [es]"=rm"(es)); 449 return es; 450 } 451 452 static inline uint16_t get_cs(void) 453 { 454 uint16_t cs; 455 456 __asm__ __volatile__("mov %%cs, %[cs]" 457 : /* output */ [cs]"=rm"(cs)); 458 return cs; 459 } 460 461 static inline uint16_t get_ss(void) 462 { 463 uint16_t ss; 464 465 __asm__ __volatile__("mov %%ss, %[ss]" 466 : /* output */ [ss]"=rm"(ss)); 467 return ss; 468 } 469 470 static inline uint16_t get_ds(void) 471 { 472 uint16_t ds; 473 474 __asm__ __volatile__("mov %%ds, %[ds]" 475 : /* output */ [ds]"=rm"(ds)); 476 return ds; 477 } 478 479 static inline uint16_t get_fs(void) 480 { 481 uint16_t fs; 482 483 __asm__ __volatile__("mov %%fs, %[fs]" 484 : /* output */ [fs]"=rm"(fs)); 485 return fs; 486 } 487 488 static inline uint16_t get_gs(void) 489 { 490 uint16_t gs; 491 492 __asm__ __volatile__("mov %%gs, %[gs]" 493 : /* output */ [gs]"=rm"(gs)); 494 return gs; 495 } 496 497 static inline uint16_t get_tr(void) 498 { 499 uint16_t tr; 500 501 __asm__ __volatile__("str %[tr]" 502 : /* output */ [tr]"=rm"(tr)); 503 return tr; 504 } 505 506 static inline uint64_t get_cr0(void) 507 { 508 uint64_t cr0; 509 510 __asm__ __volatile__("mov %%cr0, %[cr0]" 511 : /* output */ [cr0]"=r"(cr0)); 512 return cr0; 513 } 514 515 static inline uint64_t get_cr3(void) 516 { 517 uint64_t cr3; 518 519 __asm__ __volatile__("mov %%cr3, %[cr3]" 520 : /* output */ [cr3]"=r"(cr3)); 521 return cr3; 522 } 523 524 static inline uint64_t get_cr4(void) 525 { 526 uint64_t cr4; 527 528 __asm__ __volatile__("mov %%cr4, %[cr4]" 529 : /* output */ [cr4]"=r"(cr4)); 530 return cr4; 531 } 532 533 static inline void set_cr4(uint64_t val) 534 { 535 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); 536 } 537 538 static inline u64 xgetbv(u32 index) 539 { 540 u32 eax, edx; 541 542 __asm__ __volatile__("xgetbv;" 543 : "=a" (eax), "=d" (edx) 544 : "c" (index)); 545 return eax | ((u64)edx << 32); 546 } 547 548 static inline void xsetbv(u32 index, u64 value) 549 { 550 u32 eax = value; 551 u32 edx = value >> 32; 552 553 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); 554 } 555 556 static inline struct desc_ptr get_gdt(void) 557 { 558 struct desc_ptr gdt; 559 __asm__ __volatile__("sgdt %[gdt]" 560 : /* output */ [gdt]"=m"(gdt)); 561 return gdt; 562 } 563 564 static inline struct desc_ptr get_idt(void) 565 { 566 struct desc_ptr idt; 567 __asm__ __volatile__("sidt %[idt]" 568 : /* output */ [idt]"=m"(idt)); 569 return idt; 570 } 571 572 static inline void outl(uint16_t port, uint32_t value) 573 { 574 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); 575 } 576 577 static inline void __cpuid(uint32_t function, uint32_t index, 578 uint32_t *eax, uint32_t *ebx, 579 uint32_t *ecx, uint32_t *edx) 580 { 581 *eax = function; 582 *ecx = index; 583 584 asm volatile("cpuid" 585 : "=a" (*eax), 586 "=b" (*ebx), 587 "=c" (*ecx), 588 "=d" (*edx) 589 : "0" (*eax), "2" (*ecx) 590 : "memory"); 591 } 592 593 static inline void cpuid(uint32_t function, 594 uint32_t *eax, uint32_t *ebx, 595 uint32_t *ecx, uint32_t *edx) 596 { 597 return __cpuid(function, 0, eax, ebx, ecx, edx); 598 } 599 600 static inline uint32_t this_cpu_fms(void) 601 { 602 uint32_t eax, ebx, ecx, edx; 603 604 cpuid(1, &eax, &ebx, &ecx, &edx); 605 return eax; 606 } 607 608 static inline uint32_t this_cpu_family(void) 609 { 610 return x86_family(this_cpu_fms()); 611 } 612 613 static inline uint32_t this_cpu_model(void) 614 { 615 return x86_model(this_cpu_fms()); 616 } 617 618 static inline bool this_cpu_vendor_string_is(const char *vendor) 619 { 620 const uint32_t *chunk = (const uint32_t *)vendor; 621 uint32_t eax, ebx, ecx, edx; 622 623 cpuid(0, &eax, &ebx, &ecx, &edx); 624 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); 625 } 626 627 static inline bool this_cpu_is_intel(void) 628 { 629 return this_cpu_vendor_string_is("GenuineIntel"); 630 } 631 632 /* 633 * Exclude early K5 samples with a vendor string of "AMDisbetter!" 634 */ 635 static inline bool this_cpu_is_amd(void) 636 { 637 return this_cpu_vendor_string_is("AuthenticAMD"); 638 } 639 640 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index, 641 uint8_t reg, uint8_t lo, uint8_t hi) 642 { 643 uint32_t gprs[4]; 644 645 __cpuid(function, index, 646 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], 647 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]); 648 649 return (gprs[reg] & GENMASK(hi, lo)) >> lo; 650 } 651 652 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) 653 { 654 return __this_cpu_has(feature.function, feature.index, 655 feature.reg, feature.bit, feature.bit); 656 } 657 658 static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property) 659 { 660 return __this_cpu_has(property.function, property.index, 661 property.reg, property.lo_bit, property.hi_bit); 662 } 663 664 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) 665 { 666 uint32_t max_leaf; 667 668 switch (property.function & 0xc0000000) { 669 case 0: 670 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 671 break; 672 case 0x40000000: 673 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 674 break; 675 case 0x80000000: 676 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 677 break; 678 case 0xc0000000: 679 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 680 } 681 return max_leaf >= property.function; 682 } 683 684 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) 685 { 686 uint32_t nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 687 688 return nr_bits > feature.anti_feature.bit && 689 !this_cpu_has(feature.anti_feature); 690 } 691 692 static __always_inline uint64_t this_cpu_supported_xcr0(void) 693 { 694 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 695 return 0; 696 697 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 698 ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 699 } 700 701 typedef u32 __attribute__((vector_size(16))) sse128_t; 702 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } 703 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; }) 704 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; }) 705 706 static inline void read_sse_reg(int reg, sse128_t *data) 707 { 708 switch (reg) { 709 case 0: 710 asm("movdqa %%xmm0, %0" : "=m"(*data)); 711 break; 712 case 1: 713 asm("movdqa %%xmm1, %0" : "=m"(*data)); 714 break; 715 case 2: 716 asm("movdqa %%xmm2, %0" : "=m"(*data)); 717 break; 718 case 3: 719 asm("movdqa %%xmm3, %0" : "=m"(*data)); 720 break; 721 case 4: 722 asm("movdqa %%xmm4, %0" : "=m"(*data)); 723 break; 724 case 5: 725 asm("movdqa %%xmm5, %0" : "=m"(*data)); 726 break; 727 case 6: 728 asm("movdqa %%xmm6, %0" : "=m"(*data)); 729 break; 730 case 7: 731 asm("movdqa %%xmm7, %0" : "=m"(*data)); 732 break; 733 default: 734 BUG(); 735 } 736 } 737 738 static inline void write_sse_reg(int reg, const sse128_t *data) 739 { 740 switch (reg) { 741 case 0: 742 asm("movdqa %0, %%xmm0" : : "m"(*data)); 743 break; 744 case 1: 745 asm("movdqa %0, %%xmm1" : : "m"(*data)); 746 break; 747 case 2: 748 asm("movdqa %0, %%xmm2" : : "m"(*data)); 749 break; 750 case 3: 751 asm("movdqa %0, %%xmm3" : : "m"(*data)); 752 break; 753 case 4: 754 asm("movdqa %0, %%xmm4" : : "m"(*data)); 755 break; 756 case 5: 757 asm("movdqa %0, %%xmm5" : : "m"(*data)); 758 break; 759 case 6: 760 asm("movdqa %0, %%xmm6" : : "m"(*data)); 761 break; 762 case 7: 763 asm("movdqa %0, %%xmm7" : : "m"(*data)); 764 break; 765 default: 766 BUG(); 767 } 768 } 769 770 static inline void cpu_relax(void) 771 { 772 asm volatile("rep; nop" ::: "memory"); 773 } 774 775 #define ud2() \ 776 __asm__ __volatile__( \ 777 "ud2\n" \ 778 ) 779 780 #define hlt() \ 781 __asm__ __volatile__( \ 782 "hlt\n" \ 783 ) 784 785 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu); 786 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state); 787 void kvm_x86_state_cleanup(struct kvm_x86_state *state); 788 789 const struct kvm_msr_list *kvm_get_msr_index_list(void); 790 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); 791 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index); 792 uint64_t kvm_get_feature_msr(uint64_t msr_index); 793 794 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, 795 struct kvm_msrs *msrs) 796 { 797 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs); 798 799 TEST_ASSERT(r == msrs->nmsrs, 800 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)", 801 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 802 } 803 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) 804 { 805 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs); 806 807 TEST_ASSERT(r == msrs->nmsrs, 808 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)", 809 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 810 } 811 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu, 812 struct kvm_debugregs *debugregs) 813 { 814 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs); 815 } 816 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu, 817 struct kvm_debugregs *debugregs) 818 { 819 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs); 820 } 821 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu, 822 struct kvm_xsave *xsave) 823 { 824 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave); 825 } 826 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu, 827 struct kvm_xsave *xsave) 828 { 829 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave); 830 } 831 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu, 832 struct kvm_xsave *xsave) 833 { 834 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave); 835 } 836 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu, 837 struct kvm_xcrs *xcrs) 838 { 839 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs); 840 } 841 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) 842 { 843 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs); 844 } 845 846 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 847 uint32_t function, uint32_t index); 848 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); 849 const struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void); 850 const struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vcpu *vcpu); 851 852 static inline uint32_t kvm_cpu_fms(void) 853 { 854 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; 855 } 856 857 static inline uint32_t kvm_cpu_family(void) 858 { 859 return x86_family(kvm_cpu_fms()); 860 } 861 862 static inline uint32_t kvm_cpu_model(void) 863 { 864 return x86_model(kvm_cpu_fms()); 865 } 866 867 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 868 struct kvm_x86_cpu_feature feature); 869 870 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) 871 { 872 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); 873 } 874 875 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 876 struct kvm_x86_cpu_property property); 877 878 static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property) 879 { 880 return kvm_cpuid_property(kvm_get_supported_cpuid(), property); 881 } 882 883 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) 884 { 885 uint32_t max_leaf; 886 887 switch (property.function & 0xc0000000) { 888 case 0: 889 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 890 break; 891 case 0x40000000: 892 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 893 break; 894 case 0x80000000: 895 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 896 break; 897 case 0xc0000000: 898 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 899 } 900 return max_leaf >= property.function; 901 } 902 903 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) 904 { 905 uint32_t nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 906 907 return nr_bits > feature.anti_feature.bit && 908 !kvm_cpu_has(feature.anti_feature); 909 } 910 911 static inline size_t kvm_cpuid2_size(int nr_entries) 912 { 913 return sizeof(struct kvm_cpuid2) + 914 sizeof(struct kvm_cpuid_entry2) * nr_entries; 915 } 916 917 /* 918 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of 919 * entries sized to hold @nr_entries. The caller is responsible for freeing 920 * the struct. 921 */ 922 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries) 923 { 924 struct kvm_cpuid2 *cpuid; 925 926 cpuid = malloc(kvm_cpuid2_size(nr_entries)); 927 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2"); 928 929 cpuid->nent = nr_entries; 930 931 return cpuid; 932 } 933 934 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid); 935 void vcpu_set_hv_cpuid(struct kvm_vcpu *vcpu); 936 937 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 938 uint32_t function, 939 uint32_t index) 940 { 941 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid, 942 function, index); 943 } 944 945 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 946 uint32_t function) 947 { 948 return __vcpu_get_cpuid_entry(vcpu, function, 0); 949 } 950 951 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu) 952 { 953 int r; 954 955 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 956 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 957 if (r) 958 return r; 959 960 /* On success, refresh the cache to pick up adjustments made by KVM. */ 961 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 962 return 0; 963 } 964 965 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) 966 { 967 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 968 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 969 970 /* Refresh the cache to pick up adjustments made by KVM. */ 971 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 972 } 973 974 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); 975 976 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); 977 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 978 struct kvm_x86_cpu_feature feature, 979 bool set); 980 981 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu, 982 struct kvm_x86_cpu_feature feature) 983 { 984 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true); 985 986 } 987 988 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, 989 struct kvm_x86_cpu_feature feature) 990 { 991 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); 992 } 993 994 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index); 995 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value); 996 997 /* 998 * Assert on an MSR access(es) and pretty print the MSR name when possible. 999 * Note, the caller provides the stringified name so that the name of macro is 1000 * printed, not the value the macro resolves to (due to macro expansion). 1001 */ 1002 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \ 1003 do { \ 1004 if (__builtin_constant_p(msr)) { \ 1005 TEST_ASSERT(cond, fmt, str, args); \ 1006 } else if (!(cond)) { \ 1007 char buf[16]; \ 1008 \ 1009 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \ 1010 TEST_ASSERT(cond, fmt, buf, args); \ 1011 } \ 1012 } while (0) 1013 1014 /* 1015 * Returns true if KVM should return the last written value when reading an MSR 1016 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that 1017 * is changing, etc. This is NOT an exhaustive list! The intent is to filter 1018 * out MSRs that are not durable _and_ that a selftest wants to write. 1019 */ 1020 static inline bool is_durable_msr(uint32_t msr) 1021 { 1022 return msr != MSR_IA32_TSC; 1023 } 1024 1025 #define vcpu_set_msr(vcpu, msr, val) \ 1026 do { \ 1027 uint64_t r, v = val; \ 1028 \ 1029 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ 1030 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ 1031 if (!is_durable_msr(msr)) \ 1032 break; \ 1033 r = vcpu_get_msr(vcpu, msr); \ 1034 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\ 1035 } while (0) 1036 1037 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); 1038 bool vm_is_unrestricted_guest(struct kvm_vm *vm); 1039 1040 struct ex_regs { 1041 uint64_t rax, rcx, rdx, rbx; 1042 uint64_t rbp, rsi, rdi; 1043 uint64_t r8, r9, r10, r11; 1044 uint64_t r12, r13, r14, r15; 1045 uint64_t vector; 1046 uint64_t error_code; 1047 uint64_t rip; 1048 uint64_t cs; 1049 uint64_t rflags; 1050 }; 1051 1052 struct idt_entry { 1053 uint16_t offset0; 1054 uint16_t selector; 1055 uint16_t ist : 3; 1056 uint16_t : 5; 1057 uint16_t type : 4; 1058 uint16_t : 1; 1059 uint16_t dpl : 2; 1060 uint16_t p : 1; 1061 uint16_t offset1; 1062 uint32_t offset2; uint32_t reserved; 1063 }; 1064 1065 void vm_init_descriptor_tables(struct kvm_vm *vm); 1066 void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu); 1067 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 1068 void (*handler)(struct ex_regs *)); 1069 1070 /* If a toddler were to say "abracadabra". */ 1071 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL 1072 1073 /* 1074 * KVM selftest exception fixup uses registers to coordinate with the exception 1075 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory 1076 * per-CPU data. Using only registers avoids having to map memory into the 1077 * guest, doesn't require a valid, stable GS.base, and reduces the risk of 1078 * for recursive faults when accessing memory in the handler. The downside to 1079 * using registers is that it restricts what registers can be used by the actual 1080 * instruction. But, selftests are 64-bit only, making register* pressure a 1081 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved 1082 * by the callee, and except for r11 are not implicit parameters to any 1083 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit 1084 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V 1085 * is higher priority than testing non-faulting SYSCALL/SYSRET. 1086 * 1087 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector 1088 * is guaranteed to be non-zero on fault. 1089 * 1090 * REGISTER INPUTS: 1091 * r9 = MAGIC 1092 * r10 = RIP 1093 * r11 = new RIP on fault 1094 * 1095 * REGISTER OUTPUTS: 1096 * r9 = exception vector (non-zero) 1097 * r10 = error code 1098 */ 1099 #define KVM_ASM_SAFE(insn) \ 1100 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \ 1101 "lea 1f(%%rip), %%r10\n\t" \ 1102 "lea 2f(%%rip), %%r11\n\t" \ 1103 "1: " insn "\n\t" \ 1104 "xor %%r9, %%r9\n\t" \ 1105 "2:\n\t" \ 1106 "mov %%r9b, %[vector]\n\t" \ 1107 "mov %%r10, %[error_code]\n\t" 1108 1109 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec) 1110 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11" 1111 1112 #define kvm_asm_safe(insn, inputs...) \ 1113 ({ \ 1114 uint64_t ign_error_code; \ 1115 uint8_t vector; \ 1116 \ 1117 asm volatile(KVM_ASM_SAFE(insn) \ 1118 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1119 : inputs \ 1120 : KVM_ASM_SAFE_CLOBBERS); \ 1121 vector; \ 1122 }) 1123 1124 #define kvm_asm_safe_ec(insn, error_code, inputs...) \ 1125 ({ \ 1126 uint8_t vector; \ 1127 \ 1128 asm volatile(KVM_ASM_SAFE(insn) \ 1129 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1130 : inputs \ 1131 : KVM_ASM_SAFE_CLOBBERS); \ 1132 vector; \ 1133 }) 1134 1135 static inline uint8_t rdmsr_safe(uint32_t msr, uint64_t *val) 1136 { 1137 uint64_t error_code; 1138 uint8_t vector; 1139 uint32_t a, d; 1140 1141 asm volatile(KVM_ASM_SAFE("rdmsr") 1142 : "=a"(a), "=d"(d), KVM_ASM_SAFE_OUTPUTS(vector, error_code) 1143 : "c"(msr) 1144 : KVM_ASM_SAFE_CLOBBERS); 1145 1146 *val = (uint64_t)a | ((uint64_t)d << 32); 1147 return vector; 1148 } 1149 1150 static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val) 1151 { 1152 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); 1153 } 1154 1155 static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value) 1156 { 1157 u32 eax = value; 1158 u32 edx = value >> 32; 1159 1160 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); 1161 } 1162 1163 bool kvm_is_tdp_enabled(void); 1164 1165 uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr, 1166 int *level); 1167 uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr); 1168 1169 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, 1170 uint64_t a3); 1171 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1172 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1173 1174 void __vm_xsave_require_permission(uint64_t xfeature, const char *name); 1175 1176 #define vm_xsave_require_permission(xfeature) \ 1177 __vm_xsave_require_permission(xfeature, #xfeature) 1178 1179 enum pg_level { 1180 PG_LEVEL_NONE, 1181 PG_LEVEL_4K, 1182 PG_LEVEL_2M, 1183 PG_LEVEL_1G, 1184 PG_LEVEL_512G, 1185 PG_LEVEL_NUM 1186 }; 1187 1188 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12) 1189 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level)) 1190 1191 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K) 1192 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M) 1193 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G) 1194 1195 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level); 1196 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 1197 uint64_t nr_bytes, int level); 1198 1199 /* 1200 * Basic CPU control in CR0 1201 */ 1202 #define X86_CR0_PE (1UL<<0) /* Protection Enable */ 1203 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */ 1204 #define X86_CR0_EM (1UL<<2) /* Emulation */ 1205 #define X86_CR0_TS (1UL<<3) /* Task Switched */ 1206 #define X86_CR0_ET (1UL<<4) /* Extension Type */ 1207 #define X86_CR0_NE (1UL<<5) /* Numeric Error */ 1208 #define X86_CR0_WP (1UL<<16) /* Write Protect */ 1209 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */ 1210 #define X86_CR0_NW (1UL<<29) /* Not Write-through */ 1211 #define X86_CR0_CD (1UL<<30) /* Cache Disable */ 1212 #define X86_CR0_PG (1UL<<31) /* Paging */ 1213 1214 #define PFERR_PRESENT_BIT 0 1215 #define PFERR_WRITE_BIT 1 1216 #define PFERR_USER_BIT 2 1217 #define PFERR_RSVD_BIT 3 1218 #define PFERR_FETCH_BIT 4 1219 #define PFERR_PK_BIT 5 1220 #define PFERR_SGX_BIT 15 1221 #define PFERR_GUEST_FINAL_BIT 32 1222 #define PFERR_GUEST_PAGE_BIT 33 1223 #define PFERR_IMPLICIT_ACCESS_BIT 48 1224 1225 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) 1226 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) 1227 #define PFERR_USER_MASK BIT(PFERR_USER_BIT) 1228 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT) 1229 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT) 1230 #define PFERR_PK_MASK BIT(PFERR_PK_BIT) 1231 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT) 1232 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) 1233 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) 1234 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) 1235 1236 #endif /* SELFTEST_KVM_PROCESSOR_H */ 1237