1*eede2065SJue Wang /* SPDX-License-Identifier: GPL-2.0-only */ 2*eede2065SJue Wang /* 3*eede2065SJue Wang * tools/testing/selftests/kvm/include/x86_64/mce.h 4*eede2065SJue Wang * 5*eede2065SJue Wang * Copyright (C) 2022, Google LLC. 6*eede2065SJue Wang */ 7*eede2065SJue Wang 8*eede2065SJue Wang #ifndef SELFTEST_KVM_MCE_H 9*eede2065SJue Wang #define SELFTEST_KVM_MCE_H 10*eede2065SJue Wang 11*eede2065SJue Wang #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */ 12*eede2065SJue Wang #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */ 13*eede2065SJue Wang #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */ 14*eede2065SJue Wang #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */ 15*eede2065SJue Wang #define KVM_MAX_MCE_BANKS 32 16*eede2065SJue Wang #define MCG_CAP_BANKS_MASK 0xff /* Bit 0-7 of the MCG_CAP register are #banks */ 17*eede2065SJue Wang #define MCI_STATUS_VAL (1ULL << 63) /* valid error */ 18*eede2065SJue Wang #define MCI_STATUS_UC (1ULL << 61) /* uncorrected error */ 19*eede2065SJue Wang #define MCI_STATUS_EN (1ULL << 60) /* error enabled */ 20*eede2065SJue Wang #define MCI_STATUS_MISCV (1ULL << 59) /* misc error reg. valid */ 21*eede2065SJue Wang #define MCI_STATUS_ADDRV (1ULL << 58) /* addr reg. valid */ 22*eede2065SJue Wang #define MCM_ADDR_PHYS 2 /* physical address */ 23*eede2065SJue Wang #define MCI_CTL2_CMCI_EN BIT_ULL(30) 24*eede2065SJue Wang 25*eede2065SJue Wang #endif /* SELFTEST_KVM_MCE_H */ 26