1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. 4 */ 5 #ifndef __NFIT_TEST_H__ 6 #define __NFIT_TEST_H__ 7 #include <linux/list.h> 8 #include <linux/uuid.h> 9 #include <linux/ioport.h> 10 #include <linux/spinlock_types.h> 11 12 struct nfit_test_request { 13 struct list_head list; 14 struct resource res; 15 }; 16 17 struct nfit_test_resource { 18 struct list_head requests; 19 struct list_head list; 20 struct resource res; 21 struct device *dev; 22 spinlock_t lock; 23 int req_count; 24 void *buf; 25 }; 26 27 #define ND_TRANSLATE_SPA_STATUS_INVALID_SPA 2 28 #define NFIT_ARS_INJECT_INVALID 2 29 30 enum err_inj_options { 31 ND_ARS_ERR_INJ_OPT_NOTIFY = 0, 32 }; 33 34 /* nfit commands */ 35 enum nfit_cmd_num { 36 NFIT_CMD_TRANSLATE_SPA = 5, 37 NFIT_CMD_ARS_INJECT_SET = 7, 38 NFIT_CMD_ARS_INJECT_CLEAR = 8, 39 NFIT_CMD_ARS_INJECT_GET = 9, 40 }; 41 42 struct nd_cmd_translate_spa { 43 __u64 spa; 44 __u32 status; 45 __u8 flags; 46 __u8 _reserved[3]; 47 __u64 translate_length; 48 __u32 num_nvdimms; 49 struct nd_nvdimm_device { 50 __u32 nfit_device_handle; 51 __u32 _reserved; 52 __u64 dpa; 53 } __packed devices[0]; 54 55 } __packed; 56 57 struct nd_cmd_ars_err_inj { 58 __u64 err_inj_spa_range_base; 59 __u64 err_inj_spa_range_length; 60 __u8 err_inj_options; 61 __u32 status; 62 } __packed; 63 64 struct nd_cmd_ars_err_inj_clr { 65 __u64 err_inj_clr_spa_range_base; 66 __u64 err_inj_clr_spa_range_length; 67 __u32 status; 68 } __packed; 69 70 struct nd_cmd_ars_err_inj_stat { 71 __u32 status; 72 __u32 inj_err_rec_count; 73 struct nd_error_stat_query_record { 74 __u64 err_inj_stat_spa_range_base; 75 __u64 err_inj_stat_spa_range_length; 76 } __packed record[0]; 77 } __packed; 78 79 #define ND_INTEL_SMART 1 80 #define ND_INTEL_SMART_THRESHOLD 2 81 #define ND_INTEL_ENABLE_LSS_STATUS 10 82 #define ND_INTEL_FW_GET_INFO 12 83 #define ND_INTEL_FW_START_UPDATE 13 84 #define ND_INTEL_FW_SEND_DATA 14 85 #define ND_INTEL_FW_FINISH_UPDATE 15 86 #define ND_INTEL_FW_FINISH_QUERY 16 87 #define ND_INTEL_SMART_SET_THRESHOLD 17 88 #define ND_INTEL_SMART_INJECT 18 89 90 #define ND_INTEL_SMART_HEALTH_VALID (1 << 0) 91 #define ND_INTEL_SMART_SPARES_VALID (1 << 1) 92 #define ND_INTEL_SMART_USED_VALID (1 << 2) 93 #define ND_INTEL_SMART_MTEMP_VALID (1 << 3) 94 #define ND_INTEL_SMART_CTEMP_VALID (1 << 4) 95 #define ND_INTEL_SMART_SHUTDOWN_COUNT_VALID (1 << 5) 96 #define ND_INTEL_SMART_AIT_STATUS_VALID (1 << 6) 97 #define ND_INTEL_SMART_PTEMP_VALID (1 << 7) 98 #define ND_INTEL_SMART_ALARM_VALID (1 << 9) 99 #define ND_INTEL_SMART_SHUTDOWN_VALID (1 << 10) 100 #define ND_INTEL_SMART_VENDOR_VALID (1 << 11) 101 #define ND_INTEL_SMART_SPARE_TRIP (1 << 0) 102 #define ND_INTEL_SMART_TEMP_TRIP (1 << 1) 103 #define ND_INTEL_SMART_CTEMP_TRIP (1 << 2) 104 #define ND_INTEL_SMART_NON_CRITICAL_HEALTH (1 << 0) 105 #define ND_INTEL_SMART_CRITICAL_HEALTH (1 << 1) 106 #define ND_INTEL_SMART_FATAL_HEALTH (1 << 2) 107 #define ND_INTEL_SMART_INJECT_MTEMP (1 << 0) 108 #define ND_INTEL_SMART_INJECT_SPARE (1 << 1) 109 #define ND_INTEL_SMART_INJECT_FATAL (1 << 2) 110 #define ND_INTEL_SMART_INJECT_SHUTDOWN (1 << 3) 111 112 struct nd_intel_smart_threshold { 113 __u32 status; 114 union { 115 struct { 116 __u16 alarm_control; 117 __u8 spares; 118 __u16 media_temperature; 119 __u16 ctrl_temperature; 120 __u8 reserved[1]; 121 } __packed; 122 __u8 data[8]; 123 }; 124 } __packed; 125 126 struct nd_intel_smart_set_threshold { 127 __u16 alarm_control; 128 __u8 spares; 129 __u16 media_temperature; 130 __u16 ctrl_temperature; 131 __u32 status; 132 } __packed; 133 134 struct nd_intel_smart_inject { 135 __u64 flags; 136 __u8 mtemp_enable; 137 __u16 media_temperature; 138 __u8 spare_enable; 139 __u8 spares; 140 __u8 fatal_enable; 141 __u8 unsafe_shutdown_enable; 142 __u32 status; 143 } __packed; 144 145 #define INTEL_FW_STORAGE_SIZE 0x100000 146 #define INTEL_FW_MAX_SEND_LEN 0xFFEC 147 #define INTEL_FW_QUERY_INTERVAL 250000 148 #define INTEL_FW_QUERY_MAX_TIME 3000000 149 #define INTEL_FW_FIS_VERSION 0x0105 150 #define INTEL_FW_FAKE_VERSION 0xffffffffabcd 151 152 enum intel_fw_update_state { 153 FW_STATE_NEW = 0, 154 FW_STATE_IN_PROGRESS, 155 FW_STATE_VERIFY, 156 FW_STATE_UPDATED, 157 }; 158 159 struct nd_intel_fw_info { 160 __u32 status; 161 __u32 storage_size; 162 __u32 max_send_len; 163 __u32 query_interval; 164 __u32 max_query_time; 165 __u8 update_cap; 166 __u8 reserved[3]; 167 __u32 fis_version; 168 __u64 run_version; 169 __u64 updated_version; 170 } __packed; 171 172 struct nd_intel_fw_start { 173 __u32 status; 174 __u32 context; 175 } __packed; 176 177 /* this one has the output first because the variable input data size */ 178 struct nd_intel_fw_send_data { 179 __u32 context; 180 __u32 offset; 181 __u32 length; 182 __u8 data[0]; 183 /* this field is not declared due ot variable data from input */ 184 /* __u32 status; */ 185 } __packed; 186 187 struct nd_intel_fw_finish_update { 188 __u8 ctrl_flags; 189 __u8 reserved[3]; 190 __u32 context; 191 __u32 status; 192 } __packed; 193 194 struct nd_intel_fw_finish_query { 195 __u32 context; 196 __u32 status; 197 __u64 updated_fw_rev; 198 } __packed; 199 200 struct nd_intel_lss { 201 __u8 enable; 202 __u32 status; 203 } __packed; 204 205 union acpi_object; 206 typedef void *acpi_handle; 207 208 typedef struct nfit_test_resource *(*nfit_test_lookup_fn)(resource_size_t); 209 typedef union acpi_object *(*nfit_test_evaluate_dsm_fn)(acpi_handle handle, 210 const guid_t *guid, u64 rev, u64 func, 211 union acpi_object *argv4); 212 void __iomem *__wrap_ioremap_nocache(resource_size_t offset, 213 unsigned long size); 214 void __wrap_iounmap(volatile void __iomem *addr); 215 void nfit_test_setup(nfit_test_lookup_fn lookup, 216 nfit_test_evaluate_dsm_fn evaluate); 217 void nfit_test_teardown(void); 218 struct nfit_test_resource *get_nfit_res(resource_size_t resource); 219 #endif 220