1 /* 2 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License for more details. 12 */ 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/workqueue.h> 17 #include <linux/libnvdimm.h> 18 #include <linux/vmalloc.h> 19 #include <linux/device.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/ndctl.h> 23 #include <linux/sizes.h> 24 #include <linux/list.h> 25 #include <linux/slab.h> 26 #include <nd-core.h> 27 #include <nfit.h> 28 #include <nd.h> 29 #include "nfit_test.h" 30 #include "../watermark.h" 31 32 #include <asm/mcsafe_test.h> 33 34 /* 35 * Generate an NFIT table to describe the following topology: 36 * 37 * BUS0: Interleaved PMEM regions, and aliasing with BLK regions 38 * 39 * (a) (b) DIMM BLK-REGION 40 * +----------+--------------+----------+---------+ 41 * +------+ | blk2.0 | pm0.0 | blk2.1 | pm1.0 | 0 region2 42 * | imc0 +--+- - - - - region0 - - - -+----------+ + 43 * +--+---+ | blk3.0 | pm0.0 | blk3.1 | pm1.0 | 1 region3 44 * | +----------+--------------v----------v v 45 * +--+---+ | | 46 * | cpu0 | region1 47 * +--+---+ | | 48 * | +-------------------------^----------^ ^ 49 * +--+---+ | blk4.0 | pm1.0 | 2 region4 50 * | imc1 +--+-------------------------+----------+ + 51 * +------+ | blk5.0 | pm1.0 | 3 region5 52 * +-------------------------+----------+-+-------+ 53 * 54 * +--+---+ 55 * | cpu1 | 56 * +--+---+ (Hotplug DIMM) 57 * | +----------------------------------------------+ 58 * +--+---+ | blk6.0/pm7.0 | 4 region6/7 59 * | imc0 +--+----------------------------------------------+ 60 * +------+ 61 * 62 * 63 * *) In this layout we have four dimms and two memory controllers in one 64 * socket. Each unique interface (BLK or PMEM) to DPA space 65 * is identified by a region device with a dynamically assigned id. 66 * 67 * *) The first portion of dimm0 and dimm1 are interleaved as REGION0. 68 * A single PMEM namespace "pm0.0" is created using half of the 69 * REGION0 SPA-range. REGION0 spans dimm0 and dimm1. PMEM namespace 70 * allocate from from the bottom of a region. The unallocated 71 * portion of REGION0 aliases with REGION2 and REGION3. That 72 * unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and 73 * "blk3.0") starting at the base of each DIMM to offset (a) in those 74 * DIMMs. "pm0.0", "blk2.0" and "blk3.0" are free-form readable 75 * names that can be assigned to a namespace. 76 * 77 * *) In the last portion of dimm0 and dimm1 we have an interleaved 78 * SPA range, REGION1, that spans those two dimms as well as dimm2 79 * and dimm3. Some of REGION1 allocated to a PMEM namespace named 80 * "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each 81 * dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and 82 * "blk5.0". 83 * 84 * *) The portion of dimm2 and dimm3 that do not participate in the 85 * REGION1 interleaved SPA range (i.e. the DPA address below offset 86 * (b) are also included in the "blk4.0" and "blk5.0" namespaces. 87 * Note, that BLK namespaces need not be contiguous in DPA-space, and 88 * can consume aliased capacity from multiple interleave sets. 89 * 90 * BUS1: Legacy NVDIMM (single contiguous range) 91 * 92 * region2 93 * +---------------------+ 94 * |---------------------| 95 * || pm2.0 || 96 * |---------------------| 97 * +---------------------+ 98 * 99 * *) A NFIT-table may describe a simple system-physical-address range 100 * with no BLK aliasing. This type of region may optionally 101 * reference an NVDIMM. 102 */ 103 enum { 104 NUM_PM = 3, 105 NUM_DCR = 5, 106 NUM_HINTS = 8, 107 NUM_BDW = NUM_DCR, 108 NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW, 109 NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */ 110 + 4 /* spa1 iset */ + 1 /* spa11 iset */, 111 DIMM_SIZE = SZ_32M, 112 LABEL_SIZE = SZ_128K, 113 SPA_VCD_SIZE = SZ_4M, 114 SPA0_SIZE = DIMM_SIZE, 115 SPA1_SIZE = DIMM_SIZE*2, 116 SPA2_SIZE = DIMM_SIZE, 117 BDW_SIZE = 64 << 8, 118 DCR_SIZE = 12, 119 NUM_NFITS = 2, /* permit testing multiple NFITs per system */ 120 }; 121 122 struct nfit_test_dcr { 123 __le64 bdw_addr; 124 __le32 bdw_status; 125 __u8 aperature[BDW_SIZE]; 126 }; 127 128 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \ 129 (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \ 130 | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf)) 131 132 static u32 handle[] = { 133 [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0), 134 [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1), 135 [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0), 136 [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1), 137 [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0), 138 [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0), 139 [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1), 140 }; 141 142 static unsigned long dimm_fail_cmd_flags[NUM_DCR]; 143 static int dimm_fail_cmd_code[NUM_DCR]; 144 145 static const struct nd_intel_smart smart_def = { 146 .flags = ND_INTEL_SMART_HEALTH_VALID 147 | ND_INTEL_SMART_SPARES_VALID 148 | ND_INTEL_SMART_ALARM_VALID 149 | ND_INTEL_SMART_USED_VALID 150 | ND_INTEL_SMART_SHUTDOWN_VALID 151 | ND_INTEL_SMART_MTEMP_VALID 152 | ND_INTEL_SMART_CTEMP_VALID, 153 .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH, 154 .media_temperature = 23 * 16, 155 .ctrl_temperature = 25 * 16, 156 .pmic_temperature = 40 * 16, 157 .spares = 75, 158 .alarm_flags = ND_INTEL_SMART_SPARE_TRIP 159 | ND_INTEL_SMART_TEMP_TRIP, 160 .ait_status = 1, 161 .life_used = 5, 162 .shutdown_state = 0, 163 .vendor_size = 0, 164 .shutdown_count = 100, 165 }; 166 167 struct nfit_test_fw { 168 enum intel_fw_update_state state; 169 u32 context; 170 u64 version; 171 u32 size_received; 172 u64 end_time; 173 }; 174 175 struct nfit_test { 176 struct acpi_nfit_desc acpi_desc; 177 struct platform_device pdev; 178 struct list_head resources; 179 void *nfit_buf; 180 dma_addr_t nfit_dma; 181 size_t nfit_size; 182 size_t nfit_filled; 183 int dcr_idx; 184 int num_dcr; 185 int num_pm; 186 void **dimm; 187 dma_addr_t *dimm_dma; 188 void **flush; 189 dma_addr_t *flush_dma; 190 void **label; 191 dma_addr_t *label_dma; 192 void **spa_set; 193 dma_addr_t *spa_set_dma; 194 struct nfit_test_dcr **dcr; 195 dma_addr_t *dcr_dma; 196 int (*alloc)(struct nfit_test *t); 197 void (*setup)(struct nfit_test *t); 198 int setup_hotplug; 199 union acpi_object **_fit; 200 dma_addr_t _fit_dma; 201 struct ars_state { 202 struct nd_cmd_ars_status *ars_status; 203 unsigned long deadline; 204 spinlock_t lock; 205 } ars_state; 206 struct device *dimm_dev[NUM_DCR]; 207 struct nd_intel_smart *smart; 208 struct nd_intel_smart_threshold *smart_threshold; 209 struct badrange badrange; 210 struct work_struct work; 211 struct nfit_test_fw *fw; 212 }; 213 214 static struct workqueue_struct *nfit_wq; 215 216 static struct nfit_test *to_nfit_test(struct device *dev) 217 { 218 struct platform_device *pdev = to_platform_device(dev); 219 220 return container_of(pdev, struct nfit_test, pdev); 221 } 222 223 static int nd_intel_test_get_fw_info(struct nfit_test *t, 224 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len, 225 int idx) 226 { 227 struct device *dev = &t->pdev.dev; 228 struct nfit_test_fw *fw = &t->fw[idx]; 229 230 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n", 231 __func__, t, nd_cmd, buf_len, idx); 232 233 if (buf_len < sizeof(*nd_cmd)) 234 return -EINVAL; 235 236 nd_cmd->status = 0; 237 nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE; 238 nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN; 239 nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL; 240 nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME; 241 nd_cmd->update_cap = 0; 242 nd_cmd->fis_version = INTEL_FW_FIS_VERSION; 243 nd_cmd->run_version = 0; 244 nd_cmd->updated_version = fw->version; 245 246 return 0; 247 } 248 249 static int nd_intel_test_start_update(struct nfit_test *t, 250 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len, 251 int idx) 252 { 253 struct device *dev = &t->pdev.dev; 254 struct nfit_test_fw *fw = &t->fw[idx]; 255 256 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 257 __func__, t, nd_cmd, buf_len, idx); 258 259 if (buf_len < sizeof(*nd_cmd)) 260 return -EINVAL; 261 262 if (fw->state != FW_STATE_NEW) { 263 /* extended status, FW update in progress */ 264 nd_cmd->status = 0x10007; 265 return 0; 266 } 267 268 fw->state = FW_STATE_IN_PROGRESS; 269 fw->context++; 270 fw->size_received = 0; 271 nd_cmd->status = 0; 272 nd_cmd->context = fw->context; 273 274 dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context); 275 276 return 0; 277 } 278 279 static int nd_intel_test_send_data(struct nfit_test *t, 280 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len, 281 int idx) 282 { 283 struct device *dev = &t->pdev.dev; 284 struct nfit_test_fw *fw = &t->fw[idx]; 285 u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length]; 286 287 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 288 __func__, t, nd_cmd, buf_len, idx); 289 290 if (buf_len < sizeof(*nd_cmd)) 291 return -EINVAL; 292 293 294 dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status); 295 dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]); 296 dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1, 297 nd_cmd->data[nd_cmd->length-1]); 298 299 if (fw->state != FW_STATE_IN_PROGRESS) { 300 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__); 301 *status = 0x5; 302 return 0; 303 } 304 305 if (nd_cmd->context != fw->context) { 306 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 307 __func__, nd_cmd->context, fw->context); 308 *status = 0x10007; 309 return 0; 310 } 311 312 /* 313 * check offset + len > size of fw storage 314 * check length is > max send length 315 */ 316 if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE || 317 nd_cmd->length > INTEL_FW_MAX_SEND_LEN) { 318 *status = 0x3; 319 dev_dbg(dev, "%s: buffer boundary violation\n", __func__); 320 return 0; 321 } 322 323 fw->size_received += nd_cmd->length; 324 dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n", 325 __func__, nd_cmd->length, fw->size_received); 326 *status = 0; 327 return 0; 328 } 329 330 static int nd_intel_test_finish_fw(struct nfit_test *t, 331 struct nd_intel_fw_finish_update *nd_cmd, 332 unsigned int buf_len, int idx) 333 { 334 struct device *dev = &t->pdev.dev; 335 struct nfit_test_fw *fw = &t->fw[idx]; 336 337 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 338 __func__, t, nd_cmd, buf_len, idx); 339 340 if (fw->state == FW_STATE_UPDATED) { 341 /* update already done, need cold boot */ 342 nd_cmd->status = 0x20007; 343 return 0; 344 } 345 346 dev_dbg(dev, "%s: context: %#x ctrl_flags: %#x\n", 347 __func__, nd_cmd->context, nd_cmd->ctrl_flags); 348 349 switch (nd_cmd->ctrl_flags) { 350 case 0: /* finish */ 351 if (nd_cmd->context != fw->context) { 352 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 353 __func__, nd_cmd->context, 354 fw->context); 355 nd_cmd->status = 0x10007; 356 return 0; 357 } 358 nd_cmd->status = 0; 359 fw->state = FW_STATE_VERIFY; 360 /* set 1 second of time for firmware "update" */ 361 fw->end_time = jiffies + HZ; 362 break; 363 364 case 1: /* abort */ 365 fw->size_received = 0; 366 /* successfully aborted status */ 367 nd_cmd->status = 0x40007; 368 fw->state = FW_STATE_NEW; 369 dev_dbg(dev, "%s: abort successful\n", __func__); 370 break; 371 372 default: /* bad control flag */ 373 dev_warn(dev, "%s: unknown control flag: %#x\n", 374 __func__, nd_cmd->ctrl_flags); 375 return -EINVAL; 376 } 377 378 return 0; 379 } 380 381 static int nd_intel_test_finish_query(struct nfit_test *t, 382 struct nd_intel_fw_finish_query *nd_cmd, 383 unsigned int buf_len, int idx) 384 { 385 struct device *dev = &t->pdev.dev; 386 struct nfit_test_fw *fw = &t->fw[idx]; 387 388 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 389 __func__, t, nd_cmd, buf_len, idx); 390 391 if (buf_len < sizeof(*nd_cmd)) 392 return -EINVAL; 393 394 if (nd_cmd->context != fw->context) { 395 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 396 __func__, nd_cmd->context, fw->context); 397 nd_cmd->status = 0x10007; 398 return 0; 399 } 400 401 dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context); 402 403 switch (fw->state) { 404 case FW_STATE_NEW: 405 nd_cmd->updated_fw_rev = 0; 406 nd_cmd->status = 0; 407 dev_dbg(dev, "%s: new state\n", __func__); 408 break; 409 410 case FW_STATE_IN_PROGRESS: 411 /* sequencing error */ 412 nd_cmd->status = 0x40007; 413 nd_cmd->updated_fw_rev = 0; 414 dev_dbg(dev, "%s: sequence error\n", __func__); 415 break; 416 417 case FW_STATE_VERIFY: 418 if (time_is_after_jiffies64(fw->end_time)) { 419 nd_cmd->updated_fw_rev = 0; 420 nd_cmd->status = 0x20007; 421 dev_dbg(dev, "%s: still verifying\n", __func__); 422 break; 423 } 424 425 dev_dbg(dev, "%s: transition out verify\n", __func__); 426 fw->state = FW_STATE_UPDATED; 427 /* we are going to fall through if it's "done" */ 428 case FW_STATE_UPDATED: 429 nd_cmd->status = 0; 430 /* bogus test version */ 431 fw->version = nd_cmd->updated_fw_rev = 432 INTEL_FW_FAKE_VERSION; 433 dev_dbg(dev, "%s: updated\n", __func__); 434 break; 435 436 default: /* we should never get here */ 437 return -EINVAL; 438 } 439 440 return 0; 441 } 442 443 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd, 444 unsigned int buf_len) 445 { 446 if (buf_len < sizeof(*nd_cmd)) 447 return -EINVAL; 448 449 nd_cmd->status = 0; 450 nd_cmd->config_size = LABEL_SIZE; 451 nd_cmd->max_xfer = SZ_4K; 452 453 return 0; 454 } 455 456 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr 457 *nd_cmd, unsigned int buf_len, void *label) 458 { 459 unsigned int len, offset = nd_cmd->in_offset; 460 int rc; 461 462 if (buf_len < sizeof(*nd_cmd)) 463 return -EINVAL; 464 if (offset >= LABEL_SIZE) 465 return -EINVAL; 466 if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len) 467 return -EINVAL; 468 469 nd_cmd->status = 0; 470 len = min(nd_cmd->in_length, LABEL_SIZE - offset); 471 memcpy(nd_cmd->out_buf, label + offset, len); 472 rc = buf_len - sizeof(*nd_cmd) - len; 473 474 return rc; 475 } 476 477 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd, 478 unsigned int buf_len, void *label) 479 { 480 unsigned int len, offset = nd_cmd->in_offset; 481 u32 *status; 482 int rc; 483 484 if (buf_len < sizeof(*nd_cmd)) 485 return -EINVAL; 486 if (offset >= LABEL_SIZE) 487 return -EINVAL; 488 if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len) 489 return -EINVAL; 490 491 status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd); 492 *status = 0; 493 len = min(nd_cmd->in_length, LABEL_SIZE - offset); 494 memcpy(label + offset, nd_cmd->in_buf, len); 495 rc = buf_len - sizeof(*nd_cmd) - (len + 4); 496 497 return rc; 498 } 499 500 #define NFIT_TEST_CLEAR_ERR_UNIT 256 501 502 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd, 503 unsigned int buf_len) 504 { 505 int ars_recs; 506 507 if (buf_len < sizeof(*nd_cmd)) 508 return -EINVAL; 509 510 /* for testing, only store up to n records that fit within 4k */ 511 ars_recs = SZ_4K / sizeof(struct nd_ars_record); 512 513 nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status) 514 + ars_recs * sizeof(struct nd_ars_record); 515 nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16; 516 nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT; 517 518 return 0; 519 } 520 521 static void post_ars_status(struct ars_state *ars_state, 522 struct badrange *badrange, u64 addr, u64 len) 523 { 524 struct nd_cmd_ars_status *ars_status; 525 struct nd_ars_record *ars_record; 526 struct badrange_entry *be; 527 u64 end = addr + len - 1; 528 int i = 0; 529 530 ars_state->deadline = jiffies + 1*HZ; 531 ars_status = ars_state->ars_status; 532 ars_status->status = 0; 533 ars_status->address = addr; 534 ars_status->length = len; 535 ars_status->type = ND_ARS_PERSISTENT; 536 537 spin_lock(&badrange->lock); 538 list_for_each_entry(be, &badrange->list, list) { 539 u64 be_end = be->start + be->length - 1; 540 u64 rstart, rend; 541 542 /* skip entries outside the range */ 543 if (be_end < addr || be->start > end) 544 continue; 545 546 rstart = (be->start < addr) ? addr : be->start; 547 rend = (be_end < end) ? be_end : end; 548 ars_record = &ars_status->records[i]; 549 ars_record->handle = 0; 550 ars_record->err_address = rstart; 551 ars_record->length = rend - rstart + 1; 552 i++; 553 } 554 spin_unlock(&badrange->lock); 555 ars_status->num_records = i; 556 ars_status->out_length = sizeof(struct nd_cmd_ars_status) 557 + i * sizeof(struct nd_ars_record); 558 } 559 560 static int nfit_test_cmd_ars_start(struct nfit_test *t, 561 struct ars_state *ars_state, 562 struct nd_cmd_ars_start *ars_start, unsigned int buf_len, 563 int *cmd_rc) 564 { 565 if (buf_len < sizeof(*ars_start)) 566 return -EINVAL; 567 568 spin_lock(&ars_state->lock); 569 if (time_before(jiffies, ars_state->deadline)) { 570 ars_start->status = NFIT_ARS_START_BUSY; 571 *cmd_rc = -EBUSY; 572 } else { 573 ars_start->status = 0; 574 ars_start->scrub_time = 1; 575 post_ars_status(ars_state, &t->badrange, ars_start->address, 576 ars_start->length); 577 *cmd_rc = 0; 578 } 579 spin_unlock(&ars_state->lock); 580 581 return 0; 582 } 583 584 static int nfit_test_cmd_ars_status(struct ars_state *ars_state, 585 struct nd_cmd_ars_status *ars_status, unsigned int buf_len, 586 int *cmd_rc) 587 { 588 if (buf_len < ars_state->ars_status->out_length) 589 return -EINVAL; 590 591 spin_lock(&ars_state->lock); 592 if (time_before(jiffies, ars_state->deadline)) { 593 memset(ars_status, 0, buf_len); 594 ars_status->status = NFIT_ARS_STATUS_BUSY; 595 ars_status->out_length = sizeof(*ars_status); 596 *cmd_rc = -EBUSY; 597 } else { 598 memcpy(ars_status, ars_state->ars_status, 599 ars_state->ars_status->out_length); 600 *cmd_rc = 0; 601 } 602 spin_unlock(&ars_state->lock); 603 return 0; 604 } 605 606 static int nfit_test_cmd_clear_error(struct nfit_test *t, 607 struct nd_cmd_clear_error *clear_err, 608 unsigned int buf_len, int *cmd_rc) 609 { 610 const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1; 611 if (buf_len < sizeof(*clear_err)) 612 return -EINVAL; 613 614 if ((clear_err->address & mask) || (clear_err->length & mask)) 615 return -EINVAL; 616 617 badrange_forget(&t->badrange, clear_err->address, clear_err->length); 618 clear_err->status = 0; 619 clear_err->cleared = clear_err->length; 620 *cmd_rc = 0; 621 return 0; 622 } 623 624 struct region_search_spa { 625 u64 addr; 626 struct nd_region *region; 627 }; 628 629 static int is_region_device(struct device *dev) 630 { 631 return !strncmp(dev->kobj.name, "region", 6); 632 } 633 634 static int nfit_test_search_region_spa(struct device *dev, void *data) 635 { 636 struct region_search_spa *ctx = data; 637 struct nd_region *nd_region; 638 resource_size_t ndr_end; 639 640 if (!is_region_device(dev)) 641 return 0; 642 643 nd_region = to_nd_region(dev); 644 ndr_end = nd_region->ndr_start + nd_region->ndr_size; 645 646 if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) { 647 ctx->region = nd_region; 648 return 1; 649 } 650 651 return 0; 652 } 653 654 static int nfit_test_search_spa(struct nvdimm_bus *bus, 655 struct nd_cmd_translate_spa *spa) 656 { 657 int ret; 658 struct nd_region *nd_region = NULL; 659 struct nvdimm *nvdimm = NULL; 660 struct nd_mapping *nd_mapping = NULL; 661 struct region_search_spa ctx = { 662 .addr = spa->spa, 663 .region = NULL, 664 }; 665 u64 dpa; 666 667 ret = device_for_each_child(&bus->dev, &ctx, 668 nfit_test_search_region_spa); 669 670 if (!ret) 671 return -ENODEV; 672 673 nd_region = ctx.region; 674 675 dpa = ctx.addr - nd_region->ndr_start; 676 677 /* 678 * last dimm is selected for test 679 */ 680 nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1]; 681 nvdimm = nd_mapping->nvdimm; 682 683 spa->devices[0].nfit_device_handle = handle[nvdimm->id]; 684 spa->num_nvdimms = 1; 685 spa->devices[0].dpa = dpa; 686 687 return 0; 688 } 689 690 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus, 691 struct nd_cmd_translate_spa *spa, unsigned int buf_len) 692 { 693 if (buf_len < spa->translate_length) 694 return -EINVAL; 695 696 if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms) 697 spa->status = 2; 698 699 return 0; 700 } 701 702 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len, 703 struct nd_intel_smart *smart_data) 704 { 705 if (buf_len < sizeof(*smart)) 706 return -EINVAL; 707 memcpy(smart, smart_data, sizeof(*smart)); 708 return 0; 709 } 710 711 static int nfit_test_cmd_smart_threshold( 712 struct nd_intel_smart_threshold *out, 713 unsigned int buf_len, 714 struct nd_intel_smart_threshold *smart_t) 715 { 716 if (buf_len < sizeof(*smart_t)) 717 return -EINVAL; 718 memcpy(out, smart_t, sizeof(*smart_t)); 719 return 0; 720 } 721 722 static void smart_notify(struct device *bus_dev, 723 struct device *dimm_dev, struct nd_intel_smart *smart, 724 struct nd_intel_smart_threshold *thresh) 725 { 726 dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n", 727 __func__, thresh->alarm_control, thresh->spares, 728 smart->spares, thresh->media_temperature, 729 smart->media_temperature, thresh->ctrl_temperature, 730 smart->ctrl_temperature); 731 if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP) 732 && smart->spares 733 <= thresh->spares) 734 || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP) 735 && smart->media_temperature 736 >= thresh->media_temperature) 737 || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP) 738 && smart->ctrl_temperature 739 >= thresh->ctrl_temperature) 740 || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH) 741 || (smart->shutdown_state != 0)) { 742 device_lock(bus_dev); 743 __acpi_nvdimm_notify(dimm_dev, 0x81); 744 device_unlock(bus_dev); 745 } 746 } 747 748 static int nfit_test_cmd_smart_set_threshold( 749 struct nd_intel_smart_set_threshold *in, 750 unsigned int buf_len, 751 struct nd_intel_smart_threshold *thresh, 752 struct nd_intel_smart *smart, 753 struct device *bus_dev, struct device *dimm_dev) 754 { 755 unsigned int size; 756 757 size = sizeof(*in) - 4; 758 if (buf_len < size) 759 return -EINVAL; 760 memcpy(thresh->data, in, size); 761 in->status = 0; 762 smart_notify(bus_dev, dimm_dev, smart, thresh); 763 764 return 0; 765 } 766 767 static int nfit_test_cmd_smart_inject( 768 struct nd_intel_smart_inject *inj, 769 unsigned int buf_len, 770 struct nd_intel_smart_threshold *thresh, 771 struct nd_intel_smart *smart, 772 struct device *bus_dev, struct device *dimm_dev) 773 { 774 if (buf_len != sizeof(*inj)) 775 return -EINVAL; 776 777 if (inj->flags & ND_INTEL_SMART_INJECT_MTEMP) { 778 if (inj->mtemp_enable) 779 smart->media_temperature = inj->media_temperature; 780 else 781 smart->media_temperature = smart_def.media_temperature; 782 } 783 if (inj->flags & ND_INTEL_SMART_INJECT_SPARE) { 784 if (inj->spare_enable) 785 smart->spares = inj->spares; 786 else 787 smart->spares = smart_def.spares; 788 } 789 if (inj->flags & ND_INTEL_SMART_INJECT_FATAL) { 790 if (inj->fatal_enable) 791 smart->health = ND_INTEL_SMART_FATAL_HEALTH; 792 else 793 smart->health = ND_INTEL_SMART_NON_CRITICAL_HEALTH; 794 } 795 if (inj->flags & ND_INTEL_SMART_INJECT_SHUTDOWN) { 796 if (inj->unsafe_shutdown_enable) { 797 smart->shutdown_state = 1; 798 smart->shutdown_count++; 799 } else 800 smart->shutdown_state = 0; 801 } 802 inj->status = 0; 803 smart_notify(bus_dev, dimm_dev, smart, thresh); 804 805 return 0; 806 } 807 808 static void uc_error_notify(struct work_struct *work) 809 { 810 struct nfit_test *t = container_of(work, typeof(*t), work); 811 812 __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR); 813 } 814 815 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t, 816 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len) 817 { 818 int rc; 819 820 if (buf_len != sizeof(*err_inj)) { 821 rc = -EINVAL; 822 goto err; 823 } 824 825 if (err_inj->err_inj_spa_range_length <= 0) { 826 rc = -EINVAL; 827 goto err; 828 } 829 830 rc = badrange_add(&t->badrange, err_inj->err_inj_spa_range_base, 831 err_inj->err_inj_spa_range_length); 832 if (rc < 0) 833 goto err; 834 835 if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY)) 836 queue_work(nfit_wq, &t->work); 837 838 err_inj->status = 0; 839 return 0; 840 841 err: 842 err_inj->status = NFIT_ARS_INJECT_INVALID; 843 return rc; 844 } 845 846 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t, 847 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len) 848 { 849 int rc; 850 851 if (buf_len != sizeof(*err_clr)) { 852 rc = -EINVAL; 853 goto err; 854 } 855 856 if (err_clr->err_inj_clr_spa_range_length <= 0) { 857 rc = -EINVAL; 858 goto err; 859 } 860 861 badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base, 862 err_clr->err_inj_clr_spa_range_length); 863 864 err_clr->status = 0; 865 return 0; 866 867 err: 868 err_clr->status = NFIT_ARS_INJECT_INVALID; 869 return rc; 870 } 871 872 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t, 873 struct nd_cmd_ars_err_inj_stat *err_stat, 874 unsigned int buf_len) 875 { 876 struct badrange_entry *be; 877 int max = SZ_4K / sizeof(struct nd_error_stat_query_record); 878 int i = 0; 879 880 err_stat->status = 0; 881 spin_lock(&t->badrange.lock); 882 list_for_each_entry(be, &t->badrange.list, list) { 883 err_stat->record[i].err_inj_stat_spa_range_base = be->start; 884 err_stat->record[i].err_inj_stat_spa_range_length = be->length; 885 i++; 886 if (i > max) 887 break; 888 } 889 spin_unlock(&t->badrange.lock); 890 err_stat->inj_err_rec_count = i; 891 892 return 0; 893 } 894 895 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t, 896 struct nd_intel_lss *nd_cmd, unsigned int buf_len) 897 { 898 struct device *dev = &t->pdev.dev; 899 900 if (buf_len < sizeof(*nd_cmd)) 901 return -EINVAL; 902 903 switch (nd_cmd->enable) { 904 case 0: 905 nd_cmd->status = 0; 906 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n", 907 __func__); 908 break; 909 case 1: 910 nd_cmd->status = 0; 911 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n", 912 __func__); 913 break; 914 default: 915 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable); 916 nd_cmd->status = 0x3; 917 break; 918 } 919 920 921 return 0; 922 } 923 924 static int override_return_code(int dimm, unsigned int func, int rc) 925 { 926 if ((1 << func) & dimm_fail_cmd_flags[dimm]) { 927 if (dimm_fail_cmd_code[dimm]) 928 return dimm_fail_cmd_code[dimm]; 929 return -EIO; 930 } 931 return rc; 932 } 933 934 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func) 935 { 936 int i; 937 938 /* lookup per-dimm data */ 939 for (i = 0; i < ARRAY_SIZE(handle); i++) 940 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i]) 941 break; 942 if (i >= ARRAY_SIZE(handle)) 943 return -ENXIO; 944 return i; 945 } 946 947 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc, 948 struct nvdimm *nvdimm, unsigned int cmd, void *buf, 949 unsigned int buf_len, int *cmd_rc) 950 { 951 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); 952 struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc); 953 unsigned int func = cmd; 954 int i, rc = 0, __cmd_rc; 955 956 if (!cmd_rc) 957 cmd_rc = &__cmd_rc; 958 *cmd_rc = 0; 959 960 if (nvdimm) { 961 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); 962 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm); 963 964 if (!nfit_mem) 965 return -ENOTTY; 966 967 if (cmd == ND_CMD_CALL) { 968 struct nd_cmd_pkg *call_pkg = buf; 969 970 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out; 971 buf = (void *) call_pkg->nd_payload; 972 func = call_pkg->nd_command; 973 if (call_pkg->nd_family != nfit_mem->family) 974 return -ENOTTY; 975 976 i = get_dimm(nfit_mem, func); 977 if (i < 0) 978 return i; 979 980 switch (func) { 981 case ND_INTEL_ENABLE_LSS_STATUS: 982 rc = nd_intel_test_cmd_set_lss_status(t, 983 buf, buf_len); 984 break; 985 case ND_INTEL_FW_GET_INFO: 986 rc = nd_intel_test_get_fw_info(t, buf, 987 buf_len, i - t->dcr_idx); 988 break; 989 case ND_INTEL_FW_START_UPDATE: 990 rc = nd_intel_test_start_update(t, buf, 991 buf_len, i - t->dcr_idx); 992 break; 993 case ND_INTEL_FW_SEND_DATA: 994 rc = nd_intel_test_send_data(t, buf, 995 buf_len, i - t->dcr_idx); 996 break; 997 case ND_INTEL_FW_FINISH_UPDATE: 998 rc = nd_intel_test_finish_fw(t, buf, 999 buf_len, i - t->dcr_idx); 1000 break; 1001 case ND_INTEL_FW_FINISH_QUERY: 1002 rc = nd_intel_test_finish_query(t, buf, 1003 buf_len, i - t->dcr_idx); 1004 break; 1005 case ND_INTEL_SMART: 1006 rc = nfit_test_cmd_smart(buf, buf_len, 1007 &t->smart[i - t->dcr_idx]); 1008 break; 1009 case ND_INTEL_SMART_THRESHOLD: 1010 rc = nfit_test_cmd_smart_threshold(buf, 1011 buf_len, 1012 &t->smart_threshold[i - 1013 t->dcr_idx]); 1014 break; 1015 case ND_INTEL_SMART_SET_THRESHOLD: 1016 rc = nfit_test_cmd_smart_set_threshold(buf, 1017 buf_len, 1018 &t->smart_threshold[i - 1019 t->dcr_idx], 1020 &t->smart[i - t->dcr_idx], 1021 &t->pdev.dev, t->dimm_dev[i]); 1022 break; 1023 case ND_INTEL_SMART_INJECT: 1024 rc = nfit_test_cmd_smart_inject(buf, 1025 buf_len, 1026 &t->smart_threshold[i - 1027 t->dcr_idx], 1028 &t->smart[i - t->dcr_idx], 1029 &t->pdev.dev, t->dimm_dev[i]); 1030 break; 1031 default: 1032 return -ENOTTY; 1033 } 1034 return override_return_code(i, func, rc); 1035 } 1036 1037 if (!test_bit(cmd, &cmd_mask) 1038 || !test_bit(func, &nfit_mem->dsm_mask)) 1039 return -ENOTTY; 1040 1041 i = get_dimm(nfit_mem, func); 1042 if (i < 0) 1043 return i; 1044 1045 switch (func) { 1046 case ND_CMD_GET_CONFIG_SIZE: 1047 rc = nfit_test_cmd_get_config_size(buf, buf_len); 1048 break; 1049 case ND_CMD_GET_CONFIG_DATA: 1050 rc = nfit_test_cmd_get_config_data(buf, buf_len, 1051 t->label[i - t->dcr_idx]); 1052 break; 1053 case ND_CMD_SET_CONFIG_DATA: 1054 rc = nfit_test_cmd_set_config_data(buf, buf_len, 1055 t->label[i - t->dcr_idx]); 1056 break; 1057 default: 1058 return -ENOTTY; 1059 } 1060 return override_return_code(i, func, rc); 1061 } else { 1062 struct ars_state *ars_state = &t->ars_state; 1063 struct nd_cmd_pkg *call_pkg = buf; 1064 1065 if (!nd_desc) 1066 return -ENOTTY; 1067 1068 if (cmd == ND_CMD_CALL) { 1069 func = call_pkg->nd_command; 1070 1071 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out; 1072 buf = (void *) call_pkg->nd_payload; 1073 1074 switch (func) { 1075 case NFIT_CMD_TRANSLATE_SPA: 1076 rc = nfit_test_cmd_translate_spa( 1077 acpi_desc->nvdimm_bus, buf, buf_len); 1078 return rc; 1079 case NFIT_CMD_ARS_INJECT_SET: 1080 rc = nfit_test_cmd_ars_error_inject(t, buf, 1081 buf_len); 1082 return rc; 1083 case NFIT_CMD_ARS_INJECT_CLEAR: 1084 rc = nfit_test_cmd_ars_inject_clear(t, buf, 1085 buf_len); 1086 return rc; 1087 case NFIT_CMD_ARS_INJECT_GET: 1088 rc = nfit_test_cmd_ars_inject_status(t, buf, 1089 buf_len); 1090 return rc; 1091 default: 1092 return -ENOTTY; 1093 } 1094 } 1095 1096 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask)) 1097 return -ENOTTY; 1098 1099 switch (func) { 1100 case ND_CMD_ARS_CAP: 1101 rc = nfit_test_cmd_ars_cap(buf, buf_len); 1102 break; 1103 case ND_CMD_ARS_START: 1104 rc = nfit_test_cmd_ars_start(t, ars_state, buf, 1105 buf_len, cmd_rc); 1106 break; 1107 case ND_CMD_ARS_STATUS: 1108 rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len, 1109 cmd_rc); 1110 break; 1111 case ND_CMD_CLEAR_ERROR: 1112 rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc); 1113 break; 1114 default: 1115 return -ENOTTY; 1116 } 1117 } 1118 1119 return rc; 1120 } 1121 1122 static DEFINE_SPINLOCK(nfit_test_lock); 1123 static struct nfit_test *instances[NUM_NFITS]; 1124 1125 static void release_nfit_res(void *data) 1126 { 1127 struct nfit_test_resource *nfit_res = data; 1128 1129 spin_lock(&nfit_test_lock); 1130 list_del(&nfit_res->list); 1131 spin_unlock(&nfit_test_lock); 1132 1133 vfree(nfit_res->buf); 1134 kfree(nfit_res); 1135 } 1136 1137 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma, 1138 void *buf) 1139 { 1140 struct device *dev = &t->pdev.dev; 1141 struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res), 1142 GFP_KERNEL); 1143 int rc; 1144 1145 if (!buf || !nfit_res) 1146 goto err; 1147 rc = devm_add_action(dev, release_nfit_res, nfit_res); 1148 if (rc) 1149 goto err; 1150 INIT_LIST_HEAD(&nfit_res->list); 1151 memset(buf, 0, size); 1152 nfit_res->dev = dev; 1153 nfit_res->buf = buf; 1154 nfit_res->res.start = *dma; 1155 nfit_res->res.end = *dma + size - 1; 1156 nfit_res->res.name = "NFIT"; 1157 spin_lock_init(&nfit_res->lock); 1158 INIT_LIST_HEAD(&nfit_res->requests); 1159 spin_lock(&nfit_test_lock); 1160 list_add(&nfit_res->list, &t->resources); 1161 spin_unlock(&nfit_test_lock); 1162 1163 return nfit_res->buf; 1164 err: 1165 if (buf) 1166 vfree(buf); 1167 kfree(nfit_res); 1168 return NULL; 1169 } 1170 1171 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma) 1172 { 1173 void *buf = vmalloc(size); 1174 1175 *dma = (unsigned long) buf; 1176 return __test_alloc(t, size, dma, buf); 1177 } 1178 1179 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr) 1180 { 1181 int i; 1182 1183 for (i = 0; i < ARRAY_SIZE(instances); i++) { 1184 struct nfit_test_resource *n, *nfit_res = NULL; 1185 struct nfit_test *t = instances[i]; 1186 1187 if (!t) 1188 continue; 1189 spin_lock(&nfit_test_lock); 1190 list_for_each_entry(n, &t->resources, list) { 1191 if (addr >= n->res.start && (addr < n->res.start 1192 + resource_size(&n->res))) { 1193 nfit_res = n; 1194 break; 1195 } else if (addr >= (unsigned long) n->buf 1196 && (addr < (unsigned long) n->buf 1197 + resource_size(&n->res))) { 1198 nfit_res = n; 1199 break; 1200 } 1201 } 1202 spin_unlock(&nfit_test_lock); 1203 if (nfit_res) 1204 return nfit_res; 1205 } 1206 1207 return NULL; 1208 } 1209 1210 static int ars_state_init(struct device *dev, struct ars_state *ars_state) 1211 { 1212 /* for testing, only store up to n records that fit within 4k */ 1213 ars_state->ars_status = devm_kzalloc(dev, 1214 sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL); 1215 if (!ars_state->ars_status) 1216 return -ENOMEM; 1217 spin_lock_init(&ars_state->lock); 1218 return 0; 1219 } 1220 1221 static void put_dimms(void *data) 1222 { 1223 struct nfit_test *t = data; 1224 int i; 1225 1226 for (i = 0; i < t->num_dcr; i++) 1227 if (t->dimm_dev[i]) 1228 device_unregister(t->dimm_dev[i]); 1229 } 1230 1231 static struct class *nfit_test_dimm; 1232 1233 static int dimm_name_to_id(struct device *dev) 1234 { 1235 int dimm; 1236 1237 if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1) 1238 return -ENXIO; 1239 return dimm; 1240 } 1241 1242 static ssize_t handle_show(struct device *dev, struct device_attribute *attr, 1243 char *buf) 1244 { 1245 int dimm = dimm_name_to_id(dev); 1246 1247 if (dimm < 0) 1248 return dimm; 1249 1250 return sprintf(buf, "%#x\n", handle[dimm]); 1251 } 1252 DEVICE_ATTR_RO(handle); 1253 1254 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr, 1255 char *buf) 1256 { 1257 int dimm = dimm_name_to_id(dev); 1258 1259 if (dimm < 0) 1260 return dimm; 1261 1262 return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]); 1263 } 1264 1265 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr, 1266 const char *buf, size_t size) 1267 { 1268 int dimm = dimm_name_to_id(dev); 1269 unsigned long val; 1270 ssize_t rc; 1271 1272 if (dimm < 0) 1273 return dimm; 1274 1275 rc = kstrtol(buf, 0, &val); 1276 if (rc) 1277 return rc; 1278 1279 dimm_fail_cmd_flags[dimm] = val; 1280 return size; 1281 } 1282 static DEVICE_ATTR_RW(fail_cmd); 1283 1284 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr, 1285 char *buf) 1286 { 1287 int dimm = dimm_name_to_id(dev); 1288 1289 if (dimm < 0) 1290 return dimm; 1291 1292 return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]); 1293 } 1294 1295 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr, 1296 const char *buf, size_t size) 1297 { 1298 int dimm = dimm_name_to_id(dev); 1299 unsigned long val; 1300 ssize_t rc; 1301 1302 if (dimm < 0) 1303 return dimm; 1304 1305 rc = kstrtol(buf, 0, &val); 1306 if (rc) 1307 return rc; 1308 1309 dimm_fail_cmd_code[dimm] = val; 1310 return size; 1311 } 1312 static DEVICE_ATTR_RW(fail_cmd_code); 1313 1314 static struct attribute *nfit_test_dimm_attributes[] = { 1315 &dev_attr_fail_cmd.attr, 1316 &dev_attr_fail_cmd_code.attr, 1317 &dev_attr_handle.attr, 1318 NULL, 1319 }; 1320 1321 static struct attribute_group nfit_test_dimm_attribute_group = { 1322 .attrs = nfit_test_dimm_attributes, 1323 }; 1324 1325 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = { 1326 &nfit_test_dimm_attribute_group, 1327 NULL, 1328 }; 1329 1330 static int nfit_test_dimm_init(struct nfit_test *t) 1331 { 1332 int i; 1333 1334 if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t)) 1335 return -ENOMEM; 1336 for (i = 0; i < t->num_dcr; i++) { 1337 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm, 1338 &t->pdev.dev, 0, NULL, 1339 nfit_test_dimm_attribute_groups, 1340 "test_dimm%d", i + t->dcr_idx); 1341 if (!t->dimm_dev[i]) 1342 return -ENOMEM; 1343 } 1344 return 0; 1345 } 1346 1347 static void smart_init(struct nfit_test *t) 1348 { 1349 int i; 1350 const struct nd_intel_smart_threshold smart_t_data = { 1351 .alarm_control = ND_INTEL_SMART_SPARE_TRIP 1352 | ND_INTEL_SMART_TEMP_TRIP, 1353 .media_temperature = 40 * 16, 1354 .ctrl_temperature = 30 * 16, 1355 .spares = 5, 1356 }; 1357 1358 for (i = 0; i < t->num_dcr; i++) { 1359 memcpy(&t->smart[i], &smart_def, sizeof(smart_def)); 1360 memcpy(&t->smart_threshold[i], &smart_t_data, 1361 sizeof(smart_t_data)); 1362 } 1363 } 1364 1365 static int nfit_test0_alloc(struct nfit_test *t) 1366 { 1367 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA 1368 + sizeof(struct acpi_nfit_memory_map) * NUM_MEM 1369 + sizeof(struct acpi_nfit_control_region) * NUM_DCR 1370 + offsetof(struct acpi_nfit_control_region, 1371 window_size) * NUM_DCR 1372 + sizeof(struct acpi_nfit_data_region) * NUM_BDW 1373 + (sizeof(struct acpi_nfit_flush_address) 1374 + sizeof(u64) * NUM_HINTS) * NUM_DCR 1375 + sizeof(struct acpi_nfit_capabilities); 1376 int i; 1377 1378 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma); 1379 if (!t->nfit_buf) 1380 return -ENOMEM; 1381 t->nfit_size = nfit_size; 1382 1383 t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]); 1384 if (!t->spa_set[0]) 1385 return -ENOMEM; 1386 1387 t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]); 1388 if (!t->spa_set[1]) 1389 return -ENOMEM; 1390 1391 t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]); 1392 if (!t->spa_set[2]) 1393 return -ENOMEM; 1394 1395 for (i = 0; i < t->num_dcr; i++) { 1396 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]); 1397 if (!t->dimm[i]) 1398 return -ENOMEM; 1399 1400 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]); 1401 if (!t->label[i]) 1402 return -ENOMEM; 1403 sprintf(t->label[i], "label%d", i); 1404 1405 t->flush[i] = test_alloc(t, max(PAGE_SIZE, 1406 sizeof(u64) * NUM_HINTS), 1407 &t->flush_dma[i]); 1408 if (!t->flush[i]) 1409 return -ENOMEM; 1410 } 1411 1412 for (i = 0; i < t->num_dcr; i++) { 1413 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]); 1414 if (!t->dcr[i]) 1415 return -ENOMEM; 1416 } 1417 1418 t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma); 1419 if (!t->_fit) 1420 return -ENOMEM; 1421 1422 if (nfit_test_dimm_init(t)) 1423 return -ENOMEM; 1424 smart_init(t); 1425 return ars_state_init(&t->pdev.dev, &t->ars_state); 1426 } 1427 1428 static int nfit_test1_alloc(struct nfit_test *t) 1429 { 1430 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2 1431 + sizeof(struct acpi_nfit_memory_map) * 2 1432 + offsetof(struct acpi_nfit_control_region, window_size) * 2; 1433 int i; 1434 1435 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma); 1436 if (!t->nfit_buf) 1437 return -ENOMEM; 1438 t->nfit_size = nfit_size; 1439 1440 t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]); 1441 if (!t->spa_set[0]) 1442 return -ENOMEM; 1443 1444 for (i = 0; i < t->num_dcr; i++) { 1445 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]); 1446 if (!t->label[i]) 1447 return -ENOMEM; 1448 sprintf(t->label[i], "label%d", i); 1449 } 1450 1451 t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]); 1452 if (!t->spa_set[1]) 1453 return -ENOMEM; 1454 1455 if (nfit_test_dimm_init(t)) 1456 return -ENOMEM; 1457 smart_init(t); 1458 return ars_state_init(&t->pdev.dev, &t->ars_state); 1459 } 1460 1461 static void dcr_common_init(struct acpi_nfit_control_region *dcr) 1462 { 1463 dcr->vendor_id = 0xabcd; 1464 dcr->device_id = 0; 1465 dcr->revision_id = 1; 1466 dcr->valid_fields = 1; 1467 dcr->manufacturing_location = 0xa; 1468 dcr->manufacturing_date = cpu_to_be16(2016); 1469 } 1470 1471 static void nfit_test0_setup(struct nfit_test *t) 1472 { 1473 const int flush_hint_size = sizeof(struct acpi_nfit_flush_address) 1474 + (sizeof(u64) * NUM_HINTS); 1475 struct acpi_nfit_desc *acpi_desc; 1476 struct acpi_nfit_memory_map *memdev; 1477 void *nfit_buf = t->nfit_buf; 1478 struct acpi_nfit_system_address *spa; 1479 struct acpi_nfit_control_region *dcr; 1480 struct acpi_nfit_data_region *bdw; 1481 struct acpi_nfit_flush_address *flush; 1482 struct acpi_nfit_capabilities *pcap; 1483 unsigned int offset = 0, i; 1484 1485 /* 1486 * spa0 (interleave first half of dimm0 and dimm1, note storage 1487 * does not actually alias the related block-data-window 1488 * regions) 1489 */ 1490 spa = nfit_buf; 1491 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1492 spa->header.length = sizeof(*spa); 1493 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 1494 spa->range_index = 0+1; 1495 spa->address = t->spa_set_dma[0]; 1496 spa->length = SPA0_SIZE; 1497 offset += spa->header.length; 1498 1499 /* 1500 * spa1 (interleave last half of the 4 DIMMS, note storage 1501 * does not actually alias the related block-data-window 1502 * regions) 1503 */ 1504 spa = nfit_buf + offset; 1505 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1506 spa->header.length = sizeof(*spa); 1507 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 1508 spa->range_index = 1+1; 1509 spa->address = t->spa_set_dma[1]; 1510 spa->length = SPA1_SIZE; 1511 offset += spa->header.length; 1512 1513 /* spa2 (dcr0) dimm0 */ 1514 spa = nfit_buf + offset; 1515 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1516 spa->header.length = sizeof(*spa); 1517 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1518 spa->range_index = 2+1; 1519 spa->address = t->dcr_dma[0]; 1520 spa->length = DCR_SIZE; 1521 offset += spa->header.length; 1522 1523 /* spa3 (dcr1) dimm1 */ 1524 spa = nfit_buf + offset; 1525 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1526 spa->header.length = sizeof(*spa); 1527 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1528 spa->range_index = 3+1; 1529 spa->address = t->dcr_dma[1]; 1530 spa->length = DCR_SIZE; 1531 offset += spa->header.length; 1532 1533 /* spa4 (dcr2) dimm2 */ 1534 spa = nfit_buf + offset; 1535 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1536 spa->header.length = sizeof(*spa); 1537 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1538 spa->range_index = 4+1; 1539 spa->address = t->dcr_dma[2]; 1540 spa->length = DCR_SIZE; 1541 offset += spa->header.length; 1542 1543 /* spa5 (dcr3) dimm3 */ 1544 spa = nfit_buf + offset; 1545 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1546 spa->header.length = sizeof(*spa); 1547 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1548 spa->range_index = 5+1; 1549 spa->address = t->dcr_dma[3]; 1550 spa->length = DCR_SIZE; 1551 offset += spa->header.length; 1552 1553 /* spa6 (bdw for dcr0) dimm0 */ 1554 spa = nfit_buf + offset; 1555 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1556 spa->header.length = sizeof(*spa); 1557 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1558 spa->range_index = 6+1; 1559 spa->address = t->dimm_dma[0]; 1560 spa->length = DIMM_SIZE; 1561 offset += spa->header.length; 1562 1563 /* spa7 (bdw for dcr1) dimm1 */ 1564 spa = nfit_buf + offset; 1565 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1566 spa->header.length = sizeof(*spa); 1567 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1568 spa->range_index = 7+1; 1569 spa->address = t->dimm_dma[1]; 1570 spa->length = DIMM_SIZE; 1571 offset += spa->header.length; 1572 1573 /* spa8 (bdw for dcr2) dimm2 */ 1574 spa = nfit_buf + offset; 1575 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1576 spa->header.length = sizeof(*spa); 1577 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1578 spa->range_index = 8+1; 1579 spa->address = t->dimm_dma[2]; 1580 spa->length = DIMM_SIZE; 1581 offset += spa->header.length; 1582 1583 /* spa9 (bdw for dcr3) dimm3 */ 1584 spa = nfit_buf + offset; 1585 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1586 spa->header.length = sizeof(*spa); 1587 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1588 spa->range_index = 9+1; 1589 spa->address = t->dimm_dma[3]; 1590 spa->length = DIMM_SIZE; 1591 offset += spa->header.length; 1592 1593 /* mem-region0 (spa0, dimm0) */ 1594 memdev = nfit_buf + offset; 1595 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1596 memdev->header.length = sizeof(*memdev); 1597 memdev->device_handle = handle[0]; 1598 memdev->physical_id = 0; 1599 memdev->region_id = 0; 1600 memdev->range_index = 0+1; 1601 memdev->region_index = 4+1; 1602 memdev->region_size = SPA0_SIZE/2; 1603 memdev->region_offset = 1; 1604 memdev->address = 0; 1605 memdev->interleave_index = 0; 1606 memdev->interleave_ways = 2; 1607 offset += memdev->header.length; 1608 1609 /* mem-region1 (spa0, dimm1) */ 1610 memdev = nfit_buf + offset; 1611 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1612 memdev->header.length = sizeof(*memdev); 1613 memdev->device_handle = handle[1]; 1614 memdev->physical_id = 1; 1615 memdev->region_id = 0; 1616 memdev->range_index = 0+1; 1617 memdev->region_index = 5+1; 1618 memdev->region_size = SPA0_SIZE/2; 1619 memdev->region_offset = (1 << 8); 1620 memdev->address = 0; 1621 memdev->interleave_index = 0; 1622 memdev->interleave_ways = 2; 1623 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1624 offset += memdev->header.length; 1625 1626 /* mem-region2 (spa1, dimm0) */ 1627 memdev = nfit_buf + offset; 1628 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1629 memdev->header.length = sizeof(*memdev); 1630 memdev->device_handle = handle[0]; 1631 memdev->physical_id = 0; 1632 memdev->region_id = 1; 1633 memdev->range_index = 1+1; 1634 memdev->region_index = 4+1; 1635 memdev->region_size = SPA1_SIZE/4; 1636 memdev->region_offset = (1 << 16); 1637 memdev->address = SPA0_SIZE/2; 1638 memdev->interleave_index = 0; 1639 memdev->interleave_ways = 4; 1640 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1641 offset += memdev->header.length; 1642 1643 /* mem-region3 (spa1, dimm1) */ 1644 memdev = nfit_buf + offset; 1645 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1646 memdev->header.length = sizeof(*memdev); 1647 memdev->device_handle = handle[1]; 1648 memdev->physical_id = 1; 1649 memdev->region_id = 1; 1650 memdev->range_index = 1+1; 1651 memdev->region_index = 5+1; 1652 memdev->region_size = SPA1_SIZE/4; 1653 memdev->region_offset = (1 << 24); 1654 memdev->address = SPA0_SIZE/2; 1655 memdev->interleave_index = 0; 1656 memdev->interleave_ways = 4; 1657 offset += memdev->header.length; 1658 1659 /* mem-region4 (spa1, dimm2) */ 1660 memdev = nfit_buf + offset; 1661 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1662 memdev->header.length = sizeof(*memdev); 1663 memdev->device_handle = handle[2]; 1664 memdev->physical_id = 2; 1665 memdev->region_id = 0; 1666 memdev->range_index = 1+1; 1667 memdev->region_index = 6+1; 1668 memdev->region_size = SPA1_SIZE/4; 1669 memdev->region_offset = (1ULL << 32); 1670 memdev->address = SPA0_SIZE/2; 1671 memdev->interleave_index = 0; 1672 memdev->interleave_ways = 4; 1673 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1674 offset += memdev->header.length; 1675 1676 /* mem-region5 (spa1, dimm3) */ 1677 memdev = nfit_buf + offset; 1678 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1679 memdev->header.length = sizeof(*memdev); 1680 memdev->device_handle = handle[3]; 1681 memdev->physical_id = 3; 1682 memdev->region_id = 0; 1683 memdev->range_index = 1+1; 1684 memdev->region_index = 7+1; 1685 memdev->region_size = SPA1_SIZE/4; 1686 memdev->region_offset = (1ULL << 40); 1687 memdev->address = SPA0_SIZE/2; 1688 memdev->interleave_index = 0; 1689 memdev->interleave_ways = 4; 1690 offset += memdev->header.length; 1691 1692 /* mem-region6 (spa/dcr0, dimm0) */ 1693 memdev = nfit_buf + offset; 1694 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1695 memdev->header.length = sizeof(*memdev); 1696 memdev->device_handle = handle[0]; 1697 memdev->physical_id = 0; 1698 memdev->region_id = 0; 1699 memdev->range_index = 2+1; 1700 memdev->region_index = 0+1; 1701 memdev->region_size = 0; 1702 memdev->region_offset = 0; 1703 memdev->address = 0; 1704 memdev->interleave_index = 0; 1705 memdev->interleave_ways = 1; 1706 offset += memdev->header.length; 1707 1708 /* mem-region7 (spa/dcr1, dimm1) */ 1709 memdev = nfit_buf + offset; 1710 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1711 memdev->header.length = sizeof(*memdev); 1712 memdev->device_handle = handle[1]; 1713 memdev->physical_id = 1; 1714 memdev->region_id = 0; 1715 memdev->range_index = 3+1; 1716 memdev->region_index = 1+1; 1717 memdev->region_size = 0; 1718 memdev->region_offset = 0; 1719 memdev->address = 0; 1720 memdev->interleave_index = 0; 1721 memdev->interleave_ways = 1; 1722 offset += memdev->header.length; 1723 1724 /* mem-region8 (spa/dcr2, dimm2) */ 1725 memdev = nfit_buf + offset; 1726 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1727 memdev->header.length = sizeof(*memdev); 1728 memdev->device_handle = handle[2]; 1729 memdev->physical_id = 2; 1730 memdev->region_id = 0; 1731 memdev->range_index = 4+1; 1732 memdev->region_index = 2+1; 1733 memdev->region_size = 0; 1734 memdev->region_offset = 0; 1735 memdev->address = 0; 1736 memdev->interleave_index = 0; 1737 memdev->interleave_ways = 1; 1738 offset += memdev->header.length; 1739 1740 /* mem-region9 (spa/dcr3, dimm3) */ 1741 memdev = nfit_buf + offset; 1742 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1743 memdev->header.length = sizeof(*memdev); 1744 memdev->device_handle = handle[3]; 1745 memdev->physical_id = 3; 1746 memdev->region_id = 0; 1747 memdev->range_index = 5+1; 1748 memdev->region_index = 3+1; 1749 memdev->region_size = 0; 1750 memdev->region_offset = 0; 1751 memdev->address = 0; 1752 memdev->interleave_index = 0; 1753 memdev->interleave_ways = 1; 1754 offset += memdev->header.length; 1755 1756 /* mem-region10 (spa/bdw0, dimm0) */ 1757 memdev = nfit_buf + offset; 1758 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1759 memdev->header.length = sizeof(*memdev); 1760 memdev->device_handle = handle[0]; 1761 memdev->physical_id = 0; 1762 memdev->region_id = 0; 1763 memdev->range_index = 6+1; 1764 memdev->region_index = 0+1; 1765 memdev->region_size = 0; 1766 memdev->region_offset = 0; 1767 memdev->address = 0; 1768 memdev->interleave_index = 0; 1769 memdev->interleave_ways = 1; 1770 offset += memdev->header.length; 1771 1772 /* mem-region11 (spa/bdw1, dimm1) */ 1773 memdev = nfit_buf + offset; 1774 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1775 memdev->header.length = sizeof(*memdev); 1776 memdev->device_handle = handle[1]; 1777 memdev->physical_id = 1; 1778 memdev->region_id = 0; 1779 memdev->range_index = 7+1; 1780 memdev->region_index = 1+1; 1781 memdev->region_size = 0; 1782 memdev->region_offset = 0; 1783 memdev->address = 0; 1784 memdev->interleave_index = 0; 1785 memdev->interleave_ways = 1; 1786 offset += memdev->header.length; 1787 1788 /* mem-region12 (spa/bdw2, dimm2) */ 1789 memdev = nfit_buf + offset; 1790 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1791 memdev->header.length = sizeof(*memdev); 1792 memdev->device_handle = handle[2]; 1793 memdev->physical_id = 2; 1794 memdev->region_id = 0; 1795 memdev->range_index = 8+1; 1796 memdev->region_index = 2+1; 1797 memdev->region_size = 0; 1798 memdev->region_offset = 0; 1799 memdev->address = 0; 1800 memdev->interleave_index = 0; 1801 memdev->interleave_ways = 1; 1802 offset += memdev->header.length; 1803 1804 /* mem-region13 (spa/dcr3, dimm3) */ 1805 memdev = nfit_buf + offset; 1806 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1807 memdev->header.length = sizeof(*memdev); 1808 memdev->device_handle = handle[3]; 1809 memdev->physical_id = 3; 1810 memdev->region_id = 0; 1811 memdev->range_index = 9+1; 1812 memdev->region_index = 3+1; 1813 memdev->region_size = 0; 1814 memdev->region_offset = 0; 1815 memdev->address = 0; 1816 memdev->interleave_index = 0; 1817 memdev->interleave_ways = 1; 1818 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1819 offset += memdev->header.length; 1820 1821 /* dcr-descriptor0: blk */ 1822 dcr = nfit_buf + offset; 1823 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1824 dcr->header.length = sizeof(*dcr); 1825 dcr->region_index = 0+1; 1826 dcr_common_init(dcr); 1827 dcr->serial_number = ~handle[0]; 1828 dcr->code = NFIT_FIC_BLK; 1829 dcr->windows = 1; 1830 dcr->window_size = DCR_SIZE; 1831 dcr->command_offset = 0; 1832 dcr->command_size = 8; 1833 dcr->status_offset = 8; 1834 dcr->status_size = 4; 1835 offset += dcr->header.length; 1836 1837 /* dcr-descriptor1: blk */ 1838 dcr = nfit_buf + offset; 1839 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1840 dcr->header.length = sizeof(*dcr); 1841 dcr->region_index = 1+1; 1842 dcr_common_init(dcr); 1843 dcr->serial_number = ~handle[1]; 1844 dcr->code = NFIT_FIC_BLK; 1845 dcr->windows = 1; 1846 dcr->window_size = DCR_SIZE; 1847 dcr->command_offset = 0; 1848 dcr->command_size = 8; 1849 dcr->status_offset = 8; 1850 dcr->status_size = 4; 1851 offset += dcr->header.length; 1852 1853 /* dcr-descriptor2: blk */ 1854 dcr = nfit_buf + offset; 1855 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1856 dcr->header.length = sizeof(*dcr); 1857 dcr->region_index = 2+1; 1858 dcr_common_init(dcr); 1859 dcr->serial_number = ~handle[2]; 1860 dcr->code = NFIT_FIC_BLK; 1861 dcr->windows = 1; 1862 dcr->window_size = DCR_SIZE; 1863 dcr->command_offset = 0; 1864 dcr->command_size = 8; 1865 dcr->status_offset = 8; 1866 dcr->status_size = 4; 1867 offset += dcr->header.length; 1868 1869 /* dcr-descriptor3: blk */ 1870 dcr = nfit_buf + offset; 1871 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1872 dcr->header.length = sizeof(*dcr); 1873 dcr->region_index = 3+1; 1874 dcr_common_init(dcr); 1875 dcr->serial_number = ~handle[3]; 1876 dcr->code = NFIT_FIC_BLK; 1877 dcr->windows = 1; 1878 dcr->window_size = DCR_SIZE; 1879 dcr->command_offset = 0; 1880 dcr->command_size = 8; 1881 dcr->status_offset = 8; 1882 dcr->status_size = 4; 1883 offset += dcr->header.length; 1884 1885 /* dcr-descriptor0: pmem */ 1886 dcr = nfit_buf + offset; 1887 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1888 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1889 window_size); 1890 dcr->region_index = 4+1; 1891 dcr_common_init(dcr); 1892 dcr->serial_number = ~handle[0]; 1893 dcr->code = NFIT_FIC_BYTEN; 1894 dcr->windows = 0; 1895 offset += dcr->header.length; 1896 1897 /* dcr-descriptor1: pmem */ 1898 dcr = nfit_buf + offset; 1899 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1900 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1901 window_size); 1902 dcr->region_index = 5+1; 1903 dcr_common_init(dcr); 1904 dcr->serial_number = ~handle[1]; 1905 dcr->code = NFIT_FIC_BYTEN; 1906 dcr->windows = 0; 1907 offset += dcr->header.length; 1908 1909 /* dcr-descriptor2: pmem */ 1910 dcr = nfit_buf + offset; 1911 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1912 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1913 window_size); 1914 dcr->region_index = 6+1; 1915 dcr_common_init(dcr); 1916 dcr->serial_number = ~handle[2]; 1917 dcr->code = NFIT_FIC_BYTEN; 1918 dcr->windows = 0; 1919 offset += dcr->header.length; 1920 1921 /* dcr-descriptor3: pmem */ 1922 dcr = nfit_buf + offset; 1923 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1924 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1925 window_size); 1926 dcr->region_index = 7+1; 1927 dcr_common_init(dcr); 1928 dcr->serial_number = ~handle[3]; 1929 dcr->code = NFIT_FIC_BYTEN; 1930 dcr->windows = 0; 1931 offset += dcr->header.length; 1932 1933 /* bdw0 (spa/dcr0, dimm0) */ 1934 bdw = nfit_buf + offset; 1935 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1936 bdw->header.length = sizeof(*bdw); 1937 bdw->region_index = 0+1; 1938 bdw->windows = 1; 1939 bdw->offset = 0; 1940 bdw->size = BDW_SIZE; 1941 bdw->capacity = DIMM_SIZE; 1942 bdw->start_address = 0; 1943 offset += bdw->header.length; 1944 1945 /* bdw1 (spa/dcr1, dimm1) */ 1946 bdw = nfit_buf + offset; 1947 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1948 bdw->header.length = sizeof(*bdw); 1949 bdw->region_index = 1+1; 1950 bdw->windows = 1; 1951 bdw->offset = 0; 1952 bdw->size = BDW_SIZE; 1953 bdw->capacity = DIMM_SIZE; 1954 bdw->start_address = 0; 1955 offset += bdw->header.length; 1956 1957 /* bdw2 (spa/dcr2, dimm2) */ 1958 bdw = nfit_buf + offset; 1959 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1960 bdw->header.length = sizeof(*bdw); 1961 bdw->region_index = 2+1; 1962 bdw->windows = 1; 1963 bdw->offset = 0; 1964 bdw->size = BDW_SIZE; 1965 bdw->capacity = DIMM_SIZE; 1966 bdw->start_address = 0; 1967 offset += bdw->header.length; 1968 1969 /* bdw3 (spa/dcr3, dimm3) */ 1970 bdw = nfit_buf + offset; 1971 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1972 bdw->header.length = sizeof(*bdw); 1973 bdw->region_index = 3+1; 1974 bdw->windows = 1; 1975 bdw->offset = 0; 1976 bdw->size = BDW_SIZE; 1977 bdw->capacity = DIMM_SIZE; 1978 bdw->start_address = 0; 1979 offset += bdw->header.length; 1980 1981 /* flush0 (dimm0) */ 1982 flush = nfit_buf + offset; 1983 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 1984 flush->header.length = flush_hint_size; 1985 flush->device_handle = handle[0]; 1986 flush->hint_count = NUM_HINTS; 1987 for (i = 0; i < NUM_HINTS; i++) 1988 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64); 1989 offset += flush->header.length; 1990 1991 /* flush1 (dimm1) */ 1992 flush = nfit_buf + offset; 1993 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 1994 flush->header.length = flush_hint_size; 1995 flush->device_handle = handle[1]; 1996 flush->hint_count = NUM_HINTS; 1997 for (i = 0; i < NUM_HINTS; i++) 1998 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64); 1999 offset += flush->header.length; 2000 2001 /* flush2 (dimm2) */ 2002 flush = nfit_buf + offset; 2003 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2004 flush->header.length = flush_hint_size; 2005 flush->device_handle = handle[2]; 2006 flush->hint_count = NUM_HINTS; 2007 for (i = 0; i < NUM_HINTS; i++) 2008 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64); 2009 offset += flush->header.length; 2010 2011 /* flush3 (dimm3) */ 2012 flush = nfit_buf + offset; 2013 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2014 flush->header.length = flush_hint_size; 2015 flush->device_handle = handle[3]; 2016 flush->hint_count = NUM_HINTS; 2017 for (i = 0; i < NUM_HINTS; i++) 2018 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64); 2019 offset += flush->header.length; 2020 2021 /* platform capabilities */ 2022 pcap = nfit_buf + offset; 2023 pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES; 2024 pcap->header.length = sizeof(*pcap); 2025 pcap->highest_capability = 1; 2026 pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH; 2027 offset += pcap->header.length; 2028 2029 if (t->setup_hotplug) { 2030 /* dcr-descriptor4: blk */ 2031 dcr = nfit_buf + offset; 2032 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2033 dcr->header.length = sizeof(*dcr); 2034 dcr->region_index = 8+1; 2035 dcr_common_init(dcr); 2036 dcr->serial_number = ~handle[4]; 2037 dcr->code = NFIT_FIC_BLK; 2038 dcr->windows = 1; 2039 dcr->window_size = DCR_SIZE; 2040 dcr->command_offset = 0; 2041 dcr->command_size = 8; 2042 dcr->status_offset = 8; 2043 dcr->status_size = 4; 2044 offset += dcr->header.length; 2045 2046 /* dcr-descriptor4: pmem */ 2047 dcr = nfit_buf + offset; 2048 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2049 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2050 window_size); 2051 dcr->region_index = 9+1; 2052 dcr_common_init(dcr); 2053 dcr->serial_number = ~handle[4]; 2054 dcr->code = NFIT_FIC_BYTEN; 2055 dcr->windows = 0; 2056 offset += dcr->header.length; 2057 2058 /* bdw4 (spa/dcr4, dimm4) */ 2059 bdw = nfit_buf + offset; 2060 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 2061 bdw->header.length = sizeof(*bdw); 2062 bdw->region_index = 8+1; 2063 bdw->windows = 1; 2064 bdw->offset = 0; 2065 bdw->size = BDW_SIZE; 2066 bdw->capacity = DIMM_SIZE; 2067 bdw->start_address = 0; 2068 offset += bdw->header.length; 2069 2070 /* spa10 (dcr4) dimm4 */ 2071 spa = nfit_buf + offset; 2072 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2073 spa->header.length = sizeof(*spa); 2074 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 2075 spa->range_index = 10+1; 2076 spa->address = t->dcr_dma[4]; 2077 spa->length = DCR_SIZE; 2078 offset += spa->header.length; 2079 2080 /* 2081 * spa11 (single-dimm interleave for hotplug, note storage 2082 * does not actually alias the related block-data-window 2083 * regions) 2084 */ 2085 spa = nfit_buf + offset; 2086 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2087 spa->header.length = sizeof(*spa); 2088 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 2089 spa->range_index = 11+1; 2090 spa->address = t->spa_set_dma[2]; 2091 spa->length = SPA0_SIZE; 2092 offset += spa->header.length; 2093 2094 /* spa12 (bdw for dcr4) dimm4 */ 2095 spa = nfit_buf + offset; 2096 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2097 spa->header.length = sizeof(*spa); 2098 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 2099 spa->range_index = 12+1; 2100 spa->address = t->dimm_dma[4]; 2101 spa->length = DIMM_SIZE; 2102 offset += spa->header.length; 2103 2104 /* mem-region14 (spa/dcr4, dimm4) */ 2105 memdev = nfit_buf + offset; 2106 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2107 memdev->header.length = sizeof(*memdev); 2108 memdev->device_handle = handle[4]; 2109 memdev->physical_id = 4; 2110 memdev->region_id = 0; 2111 memdev->range_index = 10+1; 2112 memdev->region_index = 8+1; 2113 memdev->region_size = 0; 2114 memdev->region_offset = 0; 2115 memdev->address = 0; 2116 memdev->interleave_index = 0; 2117 memdev->interleave_ways = 1; 2118 offset += memdev->header.length; 2119 2120 /* mem-region15 (spa11, dimm4) */ 2121 memdev = nfit_buf + offset; 2122 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2123 memdev->header.length = sizeof(*memdev); 2124 memdev->device_handle = handle[4]; 2125 memdev->physical_id = 4; 2126 memdev->region_id = 0; 2127 memdev->range_index = 11+1; 2128 memdev->region_index = 9+1; 2129 memdev->region_size = SPA0_SIZE; 2130 memdev->region_offset = (1ULL << 48); 2131 memdev->address = 0; 2132 memdev->interleave_index = 0; 2133 memdev->interleave_ways = 1; 2134 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 2135 offset += memdev->header.length; 2136 2137 /* mem-region16 (spa/bdw4, dimm4) */ 2138 memdev = nfit_buf + offset; 2139 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2140 memdev->header.length = sizeof(*memdev); 2141 memdev->device_handle = handle[4]; 2142 memdev->physical_id = 4; 2143 memdev->region_id = 0; 2144 memdev->range_index = 12+1; 2145 memdev->region_index = 8+1; 2146 memdev->region_size = 0; 2147 memdev->region_offset = 0; 2148 memdev->address = 0; 2149 memdev->interleave_index = 0; 2150 memdev->interleave_ways = 1; 2151 offset += memdev->header.length; 2152 2153 /* flush3 (dimm4) */ 2154 flush = nfit_buf + offset; 2155 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2156 flush->header.length = flush_hint_size; 2157 flush->device_handle = handle[4]; 2158 flush->hint_count = NUM_HINTS; 2159 for (i = 0; i < NUM_HINTS; i++) 2160 flush->hint_address[i] = t->flush_dma[4] 2161 + i * sizeof(u64); 2162 offset += flush->header.length; 2163 2164 /* sanity check to make sure we've filled the buffer */ 2165 WARN_ON(offset != t->nfit_size); 2166 } 2167 2168 t->nfit_filled = offset; 2169 2170 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0], 2171 SPA0_SIZE); 2172 2173 acpi_desc = &t->acpi_desc; 2174 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en); 2175 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2176 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2177 set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en); 2178 set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en); 2179 set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en); 2180 set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en); 2181 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en); 2182 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en); 2183 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en); 2184 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en); 2185 set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en); 2186 set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_nfit_cmd_force_en); 2187 set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_nfit_cmd_force_en); 2188 set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_nfit_cmd_force_en); 2189 set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_nfit_cmd_force_en); 2190 set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en); 2191 set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en); 2192 set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en); 2193 set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en); 2194 set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en); 2195 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en); 2196 } 2197 2198 static void nfit_test1_setup(struct nfit_test *t) 2199 { 2200 size_t offset; 2201 void *nfit_buf = t->nfit_buf; 2202 struct acpi_nfit_memory_map *memdev; 2203 struct acpi_nfit_control_region *dcr; 2204 struct acpi_nfit_system_address *spa; 2205 struct acpi_nfit_desc *acpi_desc; 2206 2207 offset = 0; 2208 /* spa0 (flat range with no bdw aliasing) */ 2209 spa = nfit_buf + offset; 2210 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2211 spa->header.length = sizeof(*spa); 2212 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 2213 spa->range_index = 0+1; 2214 spa->address = t->spa_set_dma[0]; 2215 spa->length = SPA2_SIZE; 2216 offset += spa->header.length; 2217 2218 /* virtual cd region */ 2219 spa = nfit_buf + offset; 2220 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2221 spa->header.length = sizeof(*spa); 2222 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16); 2223 spa->range_index = 0; 2224 spa->address = t->spa_set_dma[1]; 2225 spa->length = SPA_VCD_SIZE; 2226 offset += spa->header.length; 2227 2228 /* mem-region0 (spa0, dimm0) */ 2229 memdev = nfit_buf + offset; 2230 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2231 memdev->header.length = sizeof(*memdev); 2232 memdev->device_handle = handle[5]; 2233 memdev->physical_id = 0; 2234 memdev->region_id = 0; 2235 memdev->range_index = 0+1; 2236 memdev->region_index = 0+1; 2237 memdev->region_size = SPA2_SIZE; 2238 memdev->region_offset = 0; 2239 memdev->address = 0; 2240 memdev->interleave_index = 0; 2241 memdev->interleave_ways = 1; 2242 memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED 2243 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED 2244 | ACPI_NFIT_MEM_NOT_ARMED; 2245 offset += memdev->header.length; 2246 2247 /* dcr-descriptor0 */ 2248 dcr = nfit_buf + offset; 2249 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2250 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2251 window_size); 2252 dcr->region_index = 0+1; 2253 dcr_common_init(dcr); 2254 dcr->serial_number = ~handle[5]; 2255 dcr->code = NFIT_FIC_BYTE; 2256 dcr->windows = 0; 2257 offset += dcr->header.length; 2258 2259 memdev = nfit_buf + offset; 2260 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2261 memdev->header.length = sizeof(*memdev); 2262 memdev->device_handle = handle[6]; 2263 memdev->physical_id = 0; 2264 memdev->region_id = 0; 2265 memdev->range_index = 0; 2266 memdev->region_index = 0+2; 2267 memdev->region_size = SPA2_SIZE; 2268 memdev->region_offset = 0; 2269 memdev->address = 0; 2270 memdev->interleave_index = 0; 2271 memdev->interleave_ways = 1; 2272 memdev->flags = ACPI_NFIT_MEM_MAP_FAILED; 2273 offset += memdev->header.length; 2274 2275 /* dcr-descriptor1 */ 2276 dcr = nfit_buf + offset; 2277 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2278 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2279 window_size); 2280 dcr->region_index = 0+2; 2281 dcr_common_init(dcr); 2282 dcr->serial_number = ~handle[6]; 2283 dcr->code = NFIT_FIC_BYTE; 2284 dcr->windows = 0; 2285 offset += dcr->header.length; 2286 2287 /* sanity check to make sure we've filled the buffer */ 2288 WARN_ON(offset != t->nfit_size); 2289 2290 t->nfit_filled = offset; 2291 2292 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0], 2293 SPA2_SIZE); 2294 2295 acpi_desc = &t->acpi_desc; 2296 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en); 2297 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en); 2298 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en); 2299 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en); 2300 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en); 2301 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en); 2302 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2303 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2304 } 2305 2306 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa, 2307 void *iobuf, u64 len, int rw) 2308 { 2309 struct nfit_blk *nfit_blk = ndbr->blk_provider_data; 2310 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW]; 2311 struct nd_region *nd_region = &ndbr->nd_region; 2312 unsigned int lane; 2313 2314 lane = nd_region_acquire_lane(nd_region); 2315 if (rw) 2316 memcpy(mmio->addr.base + dpa, iobuf, len); 2317 else { 2318 memcpy(iobuf, mmio->addr.base + dpa, len); 2319 2320 /* give us some some coverage of the arch_invalidate_pmem() API */ 2321 arch_invalidate_pmem(mmio->addr.base + dpa, len); 2322 } 2323 nd_region_release_lane(nd_region, lane); 2324 2325 return 0; 2326 } 2327 2328 static unsigned long nfit_ctl_handle; 2329 2330 union acpi_object *result; 2331 2332 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle, 2333 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4) 2334 { 2335 if (handle != &nfit_ctl_handle) 2336 return ERR_PTR(-ENXIO); 2337 2338 return result; 2339 } 2340 2341 static int setup_result(void *buf, size_t size) 2342 { 2343 result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL); 2344 if (!result) 2345 return -ENOMEM; 2346 result->package.type = ACPI_TYPE_BUFFER, 2347 result->buffer.pointer = (void *) (result + 1); 2348 result->buffer.length = size; 2349 memcpy(result->buffer.pointer, buf, size); 2350 memset(buf, 0, size); 2351 return 0; 2352 } 2353 2354 static int nfit_ctl_test(struct device *dev) 2355 { 2356 int rc, cmd_rc; 2357 struct nvdimm *nvdimm; 2358 struct acpi_device *adev; 2359 struct nfit_mem *nfit_mem; 2360 struct nd_ars_record *record; 2361 struct acpi_nfit_desc *acpi_desc; 2362 const u64 test_val = 0x0123456789abcdefULL; 2363 unsigned long mask, cmd_size, offset; 2364 union { 2365 struct nd_cmd_get_config_size cfg_size; 2366 struct nd_cmd_clear_error clear_err; 2367 struct nd_cmd_ars_status ars_stat; 2368 struct nd_cmd_ars_cap ars_cap; 2369 char buf[sizeof(struct nd_cmd_ars_status) 2370 + sizeof(struct nd_ars_record)]; 2371 } cmds; 2372 2373 adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL); 2374 if (!adev) 2375 return -ENOMEM; 2376 *adev = (struct acpi_device) { 2377 .handle = &nfit_ctl_handle, 2378 .dev = { 2379 .init_name = "test-adev", 2380 }, 2381 }; 2382 2383 acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL); 2384 if (!acpi_desc) 2385 return -ENOMEM; 2386 *acpi_desc = (struct acpi_nfit_desc) { 2387 .nd_desc = { 2388 .cmd_mask = 1UL << ND_CMD_ARS_CAP 2389 | 1UL << ND_CMD_ARS_START 2390 | 1UL << ND_CMD_ARS_STATUS 2391 | 1UL << ND_CMD_CLEAR_ERROR 2392 | 1UL << ND_CMD_CALL, 2393 .module = THIS_MODULE, 2394 .provider_name = "ACPI.NFIT", 2395 .ndctl = acpi_nfit_ctl, 2396 .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA 2397 | 1UL << NFIT_CMD_ARS_INJECT_SET 2398 | 1UL << NFIT_CMD_ARS_INJECT_CLEAR 2399 | 1UL << NFIT_CMD_ARS_INJECT_GET, 2400 }, 2401 .dev = &adev->dev, 2402 }; 2403 2404 nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL); 2405 if (!nfit_mem) 2406 return -ENOMEM; 2407 2408 mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD 2409 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE 2410 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA 2411 | 1UL << ND_CMD_VENDOR; 2412 *nfit_mem = (struct nfit_mem) { 2413 .adev = adev, 2414 .family = NVDIMM_FAMILY_INTEL, 2415 .dsm_mask = mask, 2416 }; 2417 2418 nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL); 2419 if (!nvdimm) 2420 return -ENOMEM; 2421 *nvdimm = (struct nvdimm) { 2422 .provider_data = nfit_mem, 2423 .cmd_mask = mask, 2424 .dev = { 2425 .init_name = "test-dimm", 2426 }, 2427 }; 2428 2429 2430 /* basic checkout of a typical 'get config size' command */ 2431 cmd_size = sizeof(cmds.cfg_size); 2432 cmds.cfg_size = (struct nd_cmd_get_config_size) { 2433 .status = 0, 2434 .config_size = SZ_128K, 2435 .max_xfer = SZ_4K, 2436 }; 2437 rc = setup_result(cmds.buf, cmd_size); 2438 if (rc) 2439 return rc; 2440 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE, 2441 cmds.buf, cmd_size, &cmd_rc); 2442 2443 if (rc < 0 || cmd_rc || cmds.cfg_size.status != 0 2444 || cmds.cfg_size.config_size != SZ_128K 2445 || cmds.cfg_size.max_xfer != SZ_4K) { 2446 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2447 __func__, __LINE__, rc, cmd_rc); 2448 return -EIO; 2449 } 2450 2451 2452 /* test ars_status with zero output */ 2453 cmd_size = offsetof(struct nd_cmd_ars_status, address); 2454 cmds.ars_stat = (struct nd_cmd_ars_status) { 2455 .out_length = 0, 2456 }; 2457 rc = setup_result(cmds.buf, cmd_size); 2458 if (rc) 2459 return rc; 2460 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2461 cmds.buf, cmd_size, &cmd_rc); 2462 2463 if (rc < 0 || cmd_rc) { 2464 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2465 __func__, __LINE__, rc, cmd_rc); 2466 return -EIO; 2467 } 2468 2469 2470 /* test ars_cap with benign extended status */ 2471 cmd_size = sizeof(cmds.ars_cap); 2472 cmds.ars_cap = (struct nd_cmd_ars_cap) { 2473 .status = ND_ARS_PERSISTENT << 16, 2474 }; 2475 offset = offsetof(struct nd_cmd_ars_cap, status); 2476 rc = setup_result(cmds.buf + offset, cmd_size - offset); 2477 if (rc) 2478 return rc; 2479 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP, 2480 cmds.buf, cmd_size, &cmd_rc); 2481 2482 if (rc < 0 || cmd_rc) { 2483 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2484 __func__, __LINE__, rc, cmd_rc); 2485 return -EIO; 2486 } 2487 2488 2489 /* test ars_status with 'status' trimmed from 'out_length' */ 2490 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record); 2491 cmds.ars_stat = (struct nd_cmd_ars_status) { 2492 .out_length = cmd_size - 4, 2493 }; 2494 record = &cmds.ars_stat.records[0]; 2495 *record = (struct nd_ars_record) { 2496 .length = test_val, 2497 }; 2498 rc = setup_result(cmds.buf, cmd_size); 2499 if (rc) 2500 return rc; 2501 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2502 cmds.buf, cmd_size, &cmd_rc); 2503 2504 if (rc < 0 || cmd_rc || record->length != test_val) { 2505 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2506 __func__, __LINE__, rc, cmd_rc); 2507 return -EIO; 2508 } 2509 2510 2511 /* test ars_status with 'Output (Size)' including 'status' */ 2512 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record); 2513 cmds.ars_stat = (struct nd_cmd_ars_status) { 2514 .out_length = cmd_size, 2515 }; 2516 record = &cmds.ars_stat.records[0]; 2517 *record = (struct nd_ars_record) { 2518 .length = test_val, 2519 }; 2520 rc = setup_result(cmds.buf, cmd_size); 2521 if (rc) 2522 return rc; 2523 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2524 cmds.buf, cmd_size, &cmd_rc); 2525 2526 if (rc < 0 || cmd_rc || record->length != test_val) { 2527 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2528 __func__, __LINE__, rc, cmd_rc); 2529 return -EIO; 2530 } 2531 2532 2533 /* test extended status for get_config_size results in failure */ 2534 cmd_size = sizeof(cmds.cfg_size); 2535 cmds.cfg_size = (struct nd_cmd_get_config_size) { 2536 .status = 1 << 16, 2537 }; 2538 rc = setup_result(cmds.buf, cmd_size); 2539 if (rc) 2540 return rc; 2541 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE, 2542 cmds.buf, cmd_size, &cmd_rc); 2543 2544 if (rc < 0 || cmd_rc >= 0) { 2545 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2546 __func__, __LINE__, rc, cmd_rc); 2547 return -EIO; 2548 } 2549 2550 /* test clear error */ 2551 cmd_size = sizeof(cmds.clear_err); 2552 cmds.clear_err = (struct nd_cmd_clear_error) { 2553 .length = 512, 2554 .cleared = 512, 2555 }; 2556 rc = setup_result(cmds.buf, cmd_size); 2557 if (rc) 2558 return rc; 2559 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR, 2560 cmds.buf, cmd_size, &cmd_rc); 2561 if (rc < 0 || cmd_rc) { 2562 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2563 __func__, __LINE__, rc, cmd_rc); 2564 return -EIO; 2565 } 2566 2567 return 0; 2568 } 2569 2570 static int nfit_test_probe(struct platform_device *pdev) 2571 { 2572 struct nvdimm_bus_descriptor *nd_desc; 2573 struct acpi_nfit_desc *acpi_desc; 2574 struct device *dev = &pdev->dev; 2575 struct nfit_test *nfit_test; 2576 struct nfit_mem *nfit_mem; 2577 union acpi_object *obj; 2578 int rc; 2579 2580 if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) { 2581 rc = nfit_ctl_test(&pdev->dev); 2582 if (rc) 2583 return rc; 2584 } 2585 2586 nfit_test = to_nfit_test(&pdev->dev); 2587 2588 /* common alloc */ 2589 if (nfit_test->num_dcr) { 2590 int num = nfit_test->num_dcr; 2591 2592 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *), 2593 GFP_KERNEL); 2594 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t), 2595 GFP_KERNEL); 2596 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *), 2597 GFP_KERNEL); 2598 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t), 2599 GFP_KERNEL); 2600 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *), 2601 GFP_KERNEL); 2602 nfit_test->label_dma = devm_kcalloc(dev, num, 2603 sizeof(dma_addr_t), GFP_KERNEL); 2604 nfit_test->dcr = devm_kcalloc(dev, num, 2605 sizeof(struct nfit_test_dcr *), GFP_KERNEL); 2606 nfit_test->dcr_dma = devm_kcalloc(dev, num, 2607 sizeof(dma_addr_t), GFP_KERNEL); 2608 nfit_test->smart = devm_kcalloc(dev, num, 2609 sizeof(struct nd_intel_smart), GFP_KERNEL); 2610 nfit_test->smart_threshold = devm_kcalloc(dev, num, 2611 sizeof(struct nd_intel_smart_threshold), 2612 GFP_KERNEL); 2613 nfit_test->fw = devm_kcalloc(dev, num, 2614 sizeof(struct nfit_test_fw), GFP_KERNEL); 2615 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label 2616 && nfit_test->label_dma && nfit_test->dcr 2617 && nfit_test->dcr_dma && nfit_test->flush 2618 && nfit_test->flush_dma 2619 && nfit_test->fw) 2620 /* pass */; 2621 else 2622 return -ENOMEM; 2623 } 2624 2625 if (nfit_test->num_pm) { 2626 int num = nfit_test->num_pm; 2627 2628 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *), 2629 GFP_KERNEL); 2630 nfit_test->spa_set_dma = devm_kcalloc(dev, num, 2631 sizeof(dma_addr_t), GFP_KERNEL); 2632 if (nfit_test->spa_set && nfit_test->spa_set_dma) 2633 /* pass */; 2634 else 2635 return -ENOMEM; 2636 } 2637 2638 /* per-nfit specific alloc */ 2639 if (nfit_test->alloc(nfit_test)) 2640 return -ENOMEM; 2641 2642 nfit_test->setup(nfit_test); 2643 acpi_desc = &nfit_test->acpi_desc; 2644 acpi_nfit_desc_init(acpi_desc, &pdev->dev); 2645 acpi_desc->blk_do_io = nfit_test_blk_do_io; 2646 nd_desc = &acpi_desc->nd_desc; 2647 nd_desc->provider_name = NULL; 2648 nd_desc->module = THIS_MODULE; 2649 nd_desc->ndctl = nfit_test_ctl; 2650 2651 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf, 2652 nfit_test->nfit_filled); 2653 if (rc) 2654 return rc; 2655 2656 rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc); 2657 if (rc) 2658 return rc; 2659 2660 if (nfit_test->setup != nfit_test0_setup) 2661 return 0; 2662 2663 nfit_test->setup_hotplug = 1; 2664 nfit_test->setup(nfit_test); 2665 2666 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 2667 if (!obj) 2668 return -ENOMEM; 2669 obj->type = ACPI_TYPE_BUFFER; 2670 obj->buffer.length = nfit_test->nfit_size; 2671 obj->buffer.pointer = nfit_test->nfit_buf; 2672 *(nfit_test->_fit) = obj; 2673 __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80); 2674 2675 /* associate dimm devices with nfit_mem data for notification testing */ 2676 mutex_lock(&acpi_desc->init_mutex); 2677 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) { 2678 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle; 2679 int i; 2680 2681 for (i = 0; i < NUM_DCR; i++) 2682 if (nfit_handle == handle[i]) 2683 dev_set_drvdata(nfit_test->dimm_dev[i], 2684 nfit_mem); 2685 } 2686 mutex_unlock(&acpi_desc->init_mutex); 2687 2688 return 0; 2689 } 2690 2691 static int nfit_test_remove(struct platform_device *pdev) 2692 { 2693 return 0; 2694 } 2695 2696 static void nfit_test_release(struct device *dev) 2697 { 2698 struct nfit_test *nfit_test = to_nfit_test(dev); 2699 2700 kfree(nfit_test); 2701 } 2702 2703 static const struct platform_device_id nfit_test_id[] = { 2704 { KBUILD_MODNAME }, 2705 { }, 2706 }; 2707 2708 static struct platform_driver nfit_test_driver = { 2709 .probe = nfit_test_probe, 2710 .remove = nfit_test_remove, 2711 .driver = { 2712 .name = KBUILD_MODNAME, 2713 }, 2714 .id_table = nfit_test_id, 2715 }; 2716 2717 static char mcsafe_buf[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE))); 2718 2719 enum INJECT { 2720 INJECT_NONE, 2721 INJECT_SRC, 2722 INJECT_DST, 2723 }; 2724 2725 static void mcsafe_test_init(char *dst, char *src, size_t size) 2726 { 2727 size_t i; 2728 2729 memset(dst, 0xff, size); 2730 for (i = 0; i < size; i++) 2731 src[i] = (char) i; 2732 } 2733 2734 static bool mcsafe_test_validate(unsigned char *dst, unsigned char *src, 2735 size_t size, unsigned long rem) 2736 { 2737 size_t i; 2738 2739 for (i = 0; i < size - rem; i++) 2740 if (dst[i] != (unsigned char) i) { 2741 pr_info_once("%s:%d: offset: %zd got: %#x expect: %#x\n", 2742 __func__, __LINE__, i, dst[i], 2743 (unsigned char) i); 2744 return false; 2745 } 2746 for (i = size - rem; i < size; i++) 2747 if (dst[i] != 0xffU) { 2748 pr_info_once("%s:%d: offset: %zd got: %#x expect: 0xff\n", 2749 __func__, __LINE__, i, dst[i]); 2750 return false; 2751 } 2752 return true; 2753 } 2754 2755 void mcsafe_test(void) 2756 { 2757 char *inject_desc[] = { "none", "source", "destination" }; 2758 enum INJECT inj; 2759 2760 if (IS_ENABLED(CONFIG_MCSAFE_TEST)) { 2761 pr_info("%s: run...\n", __func__); 2762 } else { 2763 pr_info("%s: disabled, skip.\n", __func__); 2764 return; 2765 } 2766 2767 for (inj = INJECT_NONE; inj <= INJECT_DST; inj++) { 2768 int i; 2769 2770 pr_info("%s: inject: %s\n", __func__, inject_desc[inj]); 2771 for (i = 0; i < 512; i++) { 2772 unsigned long expect, rem; 2773 void *src, *dst; 2774 bool valid; 2775 2776 switch (inj) { 2777 case INJECT_NONE: 2778 mcsafe_inject_src(NULL); 2779 mcsafe_inject_dst(NULL); 2780 dst = &mcsafe_buf[2048]; 2781 src = &mcsafe_buf[1024 - i]; 2782 expect = 0; 2783 break; 2784 case INJECT_SRC: 2785 mcsafe_inject_src(&mcsafe_buf[1024]); 2786 mcsafe_inject_dst(NULL); 2787 dst = &mcsafe_buf[2048]; 2788 src = &mcsafe_buf[1024 - i]; 2789 expect = 512 - i; 2790 break; 2791 case INJECT_DST: 2792 mcsafe_inject_src(NULL); 2793 mcsafe_inject_dst(&mcsafe_buf[2048]); 2794 dst = &mcsafe_buf[2048 - i]; 2795 src = &mcsafe_buf[1024]; 2796 expect = 512 - i; 2797 break; 2798 } 2799 2800 mcsafe_test_init(dst, src, 512); 2801 rem = __memcpy_mcsafe(dst, src, 512); 2802 valid = mcsafe_test_validate(dst, src, 512, expect); 2803 if (rem == expect && valid) 2804 continue; 2805 pr_info("%s: copy(%#lx, %#lx, %d) off: %d rem: %ld %s expect: %ld\n", 2806 __func__, 2807 ((unsigned long) dst) & ~PAGE_MASK, 2808 ((unsigned long ) src) & ~PAGE_MASK, 2809 512, i, rem, valid ? "valid" : "bad", 2810 expect); 2811 } 2812 } 2813 2814 mcsafe_inject_src(NULL); 2815 mcsafe_inject_dst(NULL); 2816 } 2817 2818 static __init int nfit_test_init(void) 2819 { 2820 int rc, i; 2821 2822 pmem_test(); 2823 libnvdimm_test(); 2824 acpi_nfit_test(); 2825 device_dax_test(); 2826 mcsafe_test(); 2827 2828 nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm); 2829 2830 nfit_wq = create_singlethread_workqueue("nfit"); 2831 if (!nfit_wq) 2832 return -ENOMEM; 2833 2834 nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm"); 2835 if (IS_ERR(nfit_test_dimm)) { 2836 rc = PTR_ERR(nfit_test_dimm); 2837 goto err_register; 2838 } 2839 2840 for (i = 0; i < NUM_NFITS; i++) { 2841 struct nfit_test *nfit_test; 2842 struct platform_device *pdev; 2843 2844 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL); 2845 if (!nfit_test) { 2846 rc = -ENOMEM; 2847 goto err_register; 2848 } 2849 INIT_LIST_HEAD(&nfit_test->resources); 2850 badrange_init(&nfit_test->badrange); 2851 switch (i) { 2852 case 0: 2853 nfit_test->num_pm = NUM_PM; 2854 nfit_test->dcr_idx = 0; 2855 nfit_test->num_dcr = NUM_DCR; 2856 nfit_test->alloc = nfit_test0_alloc; 2857 nfit_test->setup = nfit_test0_setup; 2858 break; 2859 case 1: 2860 nfit_test->num_pm = 2; 2861 nfit_test->dcr_idx = NUM_DCR; 2862 nfit_test->num_dcr = 2; 2863 nfit_test->alloc = nfit_test1_alloc; 2864 nfit_test->setup = nfit_test1_setup; 2865 break; 2866 default: 2867 rc = -EINVAL; 2868 goto err_register; 2869 } 2870 pdev = &nfit_test->pdev; 2871 pdev->name = KBUILD_MODNAME; 2872 pdev->id = i; 2873 pdev->dev.release = nfit_test_release; 2874 rc = platform_device_register(pdev); 2875 if (rc) { 2876 put_device(&pdev->dev); 2877 goto err_register; 2878 } 2879 get_device(&pdev->dev); 2880 2881 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2882 if (rc) 2883 goto err_register; 2884 2885 instances[i] = nfit_test; 2886 INIT_WORK(&nfit_test->work, uc_error_notify); 2887 } 2888 2889 rc = platform_driver_register(&nfit_test_driver); 2890 if (rc) 2891 goto err_register; 2892 return 0; 2893 2894 err_register: 2895 destroy_workqueue(nfit_wq); 2896 for (i = 0; i < NUM_NFITS; i++) 2897 if (instances[i]) 2898 platform_device_unregister(&instances[i]->pdev); 2899 nfit_test_teardown(); 2900 for (i = 0; i < NUM_NFITS; i++) 2901 if (instances[i]) 2902 put_device(&instances[i]->pdev.dev); 2903 2904 return rc; 2905 } 2906 2907 static __exit void nfit_test_exit(void) 2908 { 2909 int i; 2910 2911 flush_workqueue(nfit_wq); 2912 destroy_workqueue(nfit_wq); 2913 for (i = 0; i < NUM_NFITS; i++) 2914 platform_device_unregister(&instances[i]->pdev); 2915 platform_driver_unregister(&nfit_test_driver); 2916 nfit_test_teardown(); 2917 2918 for (i = 0; i < NUM_NFITS; i++) 2919 put_device(&instances[i]->pdev.dev); 2920 class_destroy(nfit_test_dimm); 2921 } 2922 2923 module_init(nfit_test_init); 2924 module_exit(nfit_test_exit); 2925 MODULE_LICENSE("GPL v2"); 2926 MODULE_AUTHOR("Intel Corporation"); 2927