1 /* 2 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License for more details. 12 */ 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/workqueue.h> 17 #include <linux/libnvdimm.h> 18 #include <linux/vmalloc.h> 19 #include <linux/device.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/ndctl.h> 23 #include <linux/sizes.h> 24 #include <linux/list.h> 25 #include <linux/slab.h> 26 #include <nd-core.h> 27 #include <intel.h> 28 #include <nfit.h> 29 #include <nd.h> 30 #include "nfit_test.h" 31 #include "../watermark.h" 32 33 #include <asm/mcsafe_test.h> 34 35 /* 36 * Generate an NFIT table to describe the following topology: 37 * 38 * BUS0: Interleaved PMEM regions, and aliasing with BLK regions 39 * 40 * (a) (b) DIMM BLK-REGION 41 * +----------+--------------+----------+---------+ 42 * +------+ | blk2.0 | pm0.0 | blk2.1 | pm1.0 | 0 region2 43 * | imc0 +--+- - - - - region0 - - - -+----------+ + 44 * +--+---+ | blk3.0 | pm0.0 | blk3.1 | pm1.0 | 1 region3 45 * | +----------+--------------v----------v v 46 * +--+---+ | | 47 * | cpu0 | region1 48 * +--+---+ | | 49 * | +-------------------------^----------^ ^ 50 * +--+---+ | blk4.0 | pm1.0 | 2 region4 51 * | imc1 +--+-------------------------+----------+ + 52 * +------+ | blk5.0 | pm1.0 | 3 region5 53 * +-------------------------+----------+-+-------+ 54 * 55 * +--+---+ 56 * | cpu1 | 57 * +--+---+ (Hotplug DIMM) 58 * | +----------------------------------------------+ 59 * +--+---+ | blk6.0/pm7.0 | 4 region6/7 60 * | imc0 +--+----------------------------------------------+ 61 * +------+ 62 * 63 * 64 * *) In this layout we have four dimms and two memory controllers in one 65 * socket. Each unique interface (BLK or PMEM) to DPA space 66 * is identified by a region device with a dynamically assigned id. 67 * 68 * *) The first portion of dimm0 and dimm1 are interleaved as REGION0. 69 * A single PMEM namespace "pm0.0" is created using half of the 70 * REGION0 SPA-range. REGION0 spans dimm0 and dimm1. PMEM namespace 71 * allocate from from the bottom of a region. The unallocated 72 * portion of REGION0 aliases with REGION2 and REGION3. That 73 * unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and 74 * "blk3.0") starting at the base of each DIMM to offset (a) in those 75 * DIMMs. "pm0.0", "blk2.0" and "blk3.0" are free-form readable 76 * names that can be assigned to a namespace. 77 * 78 * *) In the last portion of dimm0 and dimm1 we have an interleaved 79 * SPA range, REGION1, that spans those two dimms as well as dimm2 80 * and dimm3. Some of REGION1 allocated to a PMEM namespace named 81 * "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each 82 * dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and 83 * "blk5.0". 84 * 85 * *) The portion of dimm2 and dimm3 that do not participate in the 86 * REGION1 interleaved SPA range (i.e. the DPA address below offset 87 * (b) are also included in the "blk4.0" and "blk5.0" namespaces. 88 * Note, that BLK namespaces need not be contiguous in DPA-space, and 89 * can consume aliased capacity from multiple interleave sets. 90 * 91 * BUS1: Legacy NVDIMM (single contiguous range) 92 * 93 * region2 94 * +---------------------+ 95 * |---------------------| 96 * || pm2.0 || 97 * |---------------------| 98 * +---------------------+ 99 * 100 * *) A NFIT-table may describe a simple system-physical-address range 101 * with no BLK aliasing. This type of region may optionally 102 * reference an NVDIMM. 103 */ 104 enum { 105 NUM_PM = 3, 106 NUM_DCR = 5, 107 NUM_HINTS = 8, 108 NUM_BDW = NUM_DCR, 109 NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW, 110 NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */ 111 + 4 /* spa1 iset */ + 1 /* spa11 iset */, 112 DIMM_SIZE = SZ_32M, 113 LABEL_SIZE = SZ_128K, 114 SPA_VCD_SIZE = SZ_4M, 115 SPA0_SIZE = DIMM_SIZE, 116 SPA1_SIZE = DIMM_SIZE*2, 117 SPA2_SIZE = DIMM_SIZE, 118 BDW_SIZE = 64 << 8, 119 DCR_SIZE = 12, 120 NUM_NFITS = 2, /* permit testing multiple NFITs per system */ 121 }; 122 123 struct nfit_test_dcr { 124 __le64 bdw_addr; 125 __le32 bdw_status; 126 __u8 aperature[BDW_SIZE]; 127 }; 128 129 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \ 130 (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \ 131 | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf)) 132 133 static u32 handle[] = { 134 [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0), 135 [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1), 136 [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0), 137 [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1), 138 [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0), 139 [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0), 140 [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1), 141 }; 142 143 static unsigned long dimm_fail_cmd_flags[NUM_DCR]; 144 static int dimm_fail_cmd_code[NUM_DCR]; 145 146 static const struct nd_intel_smart smart_def = { 147 .flags = ND_INTEL_SMART_HEALTH_VALID 148 | ND_INTEL_SMART_SPARES_VALID 149 | ND_INTEL_SMART_ALARM_VALID 150 | ND_INTEL_SMART_USED_VALID 151 | ND_INTEL_SMART_SHUTDOWN_VALID 152 | ND_INTEL_SMART_SHUTDOWN_COUNT_VALID 153 | ND_INTEL_SMART_MTEMP_VALID 154 | ND_INTEL_SMART_CTEMP_VALID, 155 .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH, 156 .media_temperature = 23 * 16, 157 .ctrl_temperature = 25 * 16, 158 .pmic_temperature = 40 * 16, 159 .spares = 75, 160 .alarm_flags = ND_INTEL_SMART_SPARE_TRIP 161 | ND_INTEL_SMART_TEMP_TRIP, 162 .ait_status = 1, 163 .life_used = 5, 164 .shutdown_state = 0, 165 .shutdown_count = 42, 166 .vendor_size = 0, 167 }; 168 169 struct nfit_test_fw { 170 enum intel_fw_update_state state; 171 u32 context; 172 u64 version; 173 u32 size_received; 174 u64 end_time; 175 }; 176 177 struct nfit_test { 178 struct acpi_nfit_desc acpi_desc; 179 struct platform_device pdev; 180 struct list_head resources; 181 void *nfit_buf; 182 dma_addr_t nfit_dma; 183 size_t nfit_size; 184 size_t nfit_filled; 185 int dcr_idx; 186 int num_dcr; 187 int num_pm; 188 void **dimm; 189 dma_addr_t *dimm_dma; 190 void **flush; 191 dma_addr_t *flush_dma; 192 void **label; 193 dma_addr_t *label_dma; 194 void **spa_set; 195 dma_addr_t *spa_set_dma; 196 struct nfit_test_dcr **dcr; 197 dma_addr_t *dcr_dma; 198 int (*alloc)(struct nfit_test *t); 199 void (*setup)(struct nfit_test *t); 200 int setup_hotplug; 201 union acpi_object **_fit; 202 dma_addr_t _fit_dma; 203 struct ars_state { 204 struct nd_cmd_ars_status *ars_status; 205 unsigned long deadline; 206 spinlock_t lock; 207 } ars_state; 208 struct device *dimm_dev[NUM_DCR]; 209 struct nd_intel_smart *smart; 210 struct nd_intel_smart_threshold *smart_threshold; 211 struct badrange badrange; 212 struct work_struct work; 213 struct nfit_test_fw *fw; 214 }; 215 216 static struct workqueue_struct *nfit_wq; 217 218 static struct nfit_test *to_nfit_test(struct device *dev) 219 { 220 struct platform_device *pdev = to_platform_device(dev); 221 222 return container_of(pdev, struct nfit_test, pdev); 223 } 224 225 static int nd_intel_test_get_fw_info(struct nfit_test *t, 226 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len, 227 int idx) 228 { 229 struct device *dev = &t->pdev.dev; 230 struct nfit_test_fw *fw = &t->fw[idx]; 231 232 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n", 233 __func__, t, nd_cmd, buf_len, idx); 234 235 if (buf_len < sizeof(*nd_cmd)) 236 return -EINVAL; 237 238 nd_cmd->status = 0; 239 nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE; 240 nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN; 241 nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL; 242 nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME; 243 nd_cmd->update_cap = 0; 244 nd_cmd->fis_version = INTEL_FW_FIS_VERSION; 245 nd_cmd->run_version = 0; 246 nd_cmd->updated_version = fw->version; 247 248 return 0; 249 } 250 251 static int nd_intel_test_start_update(struct nfit_test *t, 252 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len, 253 int idx) 254 { 255 struct device *dev = &t->pdev.dev; 256 struct nfit_test_fw *fw = &t->fw[idx]; 257 258 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 259 __func__, t, nd_cmd, buf_len, idx); 260 261 if (buf_len < sizeof(*nd_cmd)) 262 return -EINVAL; 263 264 if (fw->state != FW_STATE_NEW) { 265 /* extended status, FW update in progress */ 266 nd_cmd->status = 0x10007; 267 return 0; 268 } 269 270 fw->state = FW_STATE_IN_PROGRESS; 271 fw->context++; 272 fw->size_received = 0; 273 nd_cmd->status = 0; 274 nd_cmd->context = fw->context; 275 276 dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context); 277 278 return 0; 279 } 280 281 static int nd_intel_test_send_data(struct nfit_test *t, 282 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len, 283 int idx) 284 { 285 struct device *dev = &t->pdev.dev; 286 struct nfit_test_fw *fw = &t->fw[idx]; 287 u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length]; 288 289 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 290 __func__, t, nd_cmd, buf_len, idx); 291 292 if (buf_len < sizeof(*nd_cmd)) 293 return -EINVAL; 294 295 296 dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status); 297 dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]); 298 dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1, 299 nd_cmd->data[nd_cmd->length-1]); 300 301 if (fw->state != FW_STATE_IN_PROGRESS) { 302 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__); 303 *status = 0x5; 304 return 0; 305 } 306 307 if (nd_cmd->context != fw->context) { 308 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 309 __func__, nd_cmd->context, fw->context); 310 *status = 0x10007; 311 return 0; 312 } 313 314 /* 315 * check offset + len > size of fw storage 316 * check length is > max send length 317 */ 318 if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE || 319 nd_cmd->length > INTEL_FW_MAX_SEND_LEN) { 320 *status = 0x3; 321 dev_dbg(dev, "%s: buffer boundary violation\n", __func__); 322 return 0; 323 } 324 325 fw->size_received += nd_cmd->length; 326 dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n", 327 __func__, nd_cmd->length, fw->size_received); 328 *status = 0; 329 return 0; 330 } 331 332 static int nd_intel_test_finish_fw(struct nfit_test *t, 333 struct nd_intel_fw_finish_update *nd_cmd, 334 unsigned int buf_len, int idx) 335 { 336 struct device *dev = &t->pdev.dev; 337 struct nfit_test_fw *fw = &t->fw[idx]; 338 339 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 340 __func__, t, nd_cmd, buf_len, idx); 341 342 if (fw->state == FW_STATE_UPDATED) { 343 /* update already done, need cold boot */ 344 nd_cmd->status = 0x20007; 345 return 0; 346 } 347 348 dev_dbg(dev, "%s: context: %#x ctrl_flags: %#x\n", 349 __func__, nd_cmd->context, nd_cmd->ctrl_flags); 350 351 switch (nd_cmd->ctrl_flags) { 352 case 0: /* finish */ 353 if (nd_cmd->context != fw->context) { 354 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 355 __func__, nd_cmd->context, 356 fw->context); 357 nd_cmd->status = 0x10007; 358 return 0; 359 } 360 nd_cmd->status = 0; 361 fw->state = FW_STATE_VERIFY; 362 /* set 1 second of time for firmware "update" */ 363 fw->end_time = jiffies + HZ; 364 break; 365 366 case 1: /* abort */ 367 fw->size_received = 0; 368 /* successfully aborted status */ 369 nd_cmd->status = 0x40007; 370 fw->state = FW_STATE_NEW; 371 dev_dbg(dev, "%s: abort successful\n", __func__); 372 break; 373 374 default: /* bad control flag */ 375 dev_warn(dev, "%s: unknown control flag: %#x\n", 376 __func__, nd_cmd->ctrl_flags); 377 return -EINVAL; 378 } 379 380 return 0; 381 } 382 383 static int nd_intel_test_finish_query(struct nfit_test *t, 384 struct nd_intel_fw_finish_query *nd_cmd, 385 unsigned int buf_len, int idx) 386 { 387 struct device *dev = &t->pdev.dev; 388 struct nfit_test_fw *fw = &t->fw[idx]; 389 390 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 391 __func__, t, nd_cmd, buf_len, idx); 392 393 if (buf_len < sizeof(*nd_cmd)) 394 return -EINVAL; 395 396 if (nd_cmd->context != fw->context) { 397 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 398 __func__, nd_cmd->context, fw->context); 399 nd_cmd->status = 0x10007; 400 return 0; 401 } 402 403 dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context); 404 405 switch (fw->state) { 406 case FW_STATE_NEW: 407 nd_cmd->updated_fw_rev = 0; 408 nd_cmd->status = 0; 409 dev_dbg(dev, "%s: new state\n", __func__); 410 break; 411 412 case FW_STATE_IN_PROGRESS: 413 /* sequencing error */ 414 nd_cmd->status = 0x40007; 415 nd_cmd->updated_fw_rev = 0; 416 dev_dbg(dev, "%s: sequence error\n", __func__); 417 break; 418 419 case FW_STATE_VERIFY: 420 if (time_is_after_jiffies64(fw->end_time)) { 421 nd_cmd->updated_fw_rev = 0; 422 nd_cmd->status = 0x20007; 423 dev_dbg(dev, "%s: still verifying\n", __func__); 424 break; 425 } 426 427 dev_dbg(dev, "%s: transition out verify\n", __func__); 428 fw->state = FW_STATE_UPDATED; 429 /* we are going to fall through if it's "done" */ 430 case FW_STATE_UPDATED: 431 nd_cmd->status = 0; 432 /* bogus test version */ 433 fw->version = nd_cmd->updated_fw_rev = 434 INTEL_FW_FAKE_VERSION; 435 dev_dbg(dev, "%s: updated\n", __func__); 436 break; 437 438 default: /* we should never get here */ 439 return -EINVAL; 440 } 441 442 return 0; 443 } 444 445 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd, 446 unsigned int buf_len) 447 { 448 if (buf_len < sizeof(*nd_cmd)) 449 return -EINVAL; 450 451 nd_cmd->status = 0; 452 nd_cmd->config_size = LABEL_SIZE; 453 nd_cmd->max_xfer = SZ_4K; 454 455 return 0; 456 } 457 458 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr 459 *nd_cmd, unsigned int buf_len, void *label) 460 { 461 unsigned int len, offset = nd_cmd->in_offset; 462 int rc; 463 464 if (buf_len < sizeof(*nd_cmd)) 465 return -EINVAL; 466 if (offset >= LABEL_SIZE) 467 return -EINVAL; 468 if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len) 469 return -EINVAL; 470 471 nd_cmd->status = 0; 472 len = min(nd_cmd->in_length, LABEL_SIZE - offset); 473 memcpy(nd_cmd->out_buf, label + offset, len); 474 rc = buf_len - sizeof(*nd_cmd) - len; 475 476 return rc; 477 } 478 479 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd, 480 unsigned int buf_len, void *label) 481 { 482 unsigned int len, offset = nd_cmd->in_offset; 483 u32 *status; 484 int rc; 485 486 if (buf_len < sizeof(*nd_cmd)) 487 return -EINVAL; 488 if (offset >= LABEL_SIZE) 489 return -EINVAL; 490 if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len) 491 return -EINVAL; 492 493 status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd); 494 *status = 0; 495 len = min(nd_cmd->in_length, LABEL_SIZE - offset); 496 memcpy(label + offset, nd_cmd->in_buf, len); 497 rc = buf_len - sizeof(*nd_cmd) - (len + 4); 498 499 return rc; 500 } 501 502 #define NFIT_TEST_CLEAR_ERR_UNIT 256 503 504 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd, 505 unsigned int buf_len) 506 { 507 int ars_recs; 508 509 if (buf_len < sizeof(*nd_cmd)) 510 return -EINVAL; 511 512 /* for testing, only store up to n records that fit within 4k */ 513 ars_recs = SZ_4K / sizeof(struct nd_ars_record); 514 515 nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status) 516 + ars_recs * sizeof(struct nd_ars_record); 517 nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16; 518 nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT; 519 520 return 0; 521 } 522 523 static void post_ars_status(struct ars_state *ars_state, 524 struct badrange *badrange, u64 addr, u64 len) 525 { 526 struct nd_cmd_ars_status *ars_status; 527 struct nd_ars_record *ars_record; 528 struct badrange_entry *be; 529 u64 end = addr + len - 1; 530 int i = 0; 531 532 ars_state->deadline = jiffies + 1*HZ; 533 ars_status = ars_state->ars_status; 534 ars_status->status = 0; 535 ars_status->address = addr; 536 ars_status->length = len; 537 ars_status->type = ND_ARS_PERSISTENT; 538 539 spin_lock(&badrange->lock); 540 list_for_each_entry(be, &badrange->list, list) { 541 u64 be_end = be->start + be->length - 1; 542 u64 rstart, rend; 543 544 /* skip entries outside the range */ 545 if (be_end < addr || be->start > end) 546 continue; 547 548 rstart = (be->start < addr) ? addr : be->start; 549 rend = (be_end < end) ? be_end : end; 550 ars_record = &ars_status->records[i]; 551 ars_record->handle = 0; 552 ars_record->err_address = rstart; 553 ars_record->length = rend - rstart + 1; 554 i++; 555 } 556 spin_unlock(&badrange->lock); 557 ars_status->num_records = i; 558 ars_status->out_length = sizeof(struct nd_cmd_ars_status) 559 + i * sizeof(struct nd_ars_record); 560 } 561 562 static int nfit_test_cmd_ars_start(struct nfit_test *t, 563 struct ars_state *ars_state, 564 struct nd_cmd_ars_start *ars_start, unsigned int buf_len, 565 int *cmd_rc) 566 { 567 if (buf_len < sizeof(*ars_start)) 568 return -EINVAL; 569 570 spin_lock(&ars_state->lock); 571 if (time_before(jiffies, ars_state->deadline)) { 572 ars_start->status = NFIT_ARS_START_BUSY; 573 *cmd_rc = -EBUSY; 574 } else { 575 ars_start->status = 0; 576 ars_start->scrub_time = 1; 577 post_ars_status(ars_state, &t->badrange, ars_start->address, 578 ars_start->length); 579 *cmd_rc = 0; 580 } 581 spin_unlock(&ars_state->lock); 582 583 return 0; 584 } 585 586 static int nfit_test_cmd_ars_status(struct ars_state *ars_state, 587 struct nd_cmd_ars_status *ars_status, unsigned int buf_len, 588 int *cmd_rc) 589 { 590 if (buf_len < ars_state->ars_status->out_length) 591 return -EINVAL; 592 593 spin_lock(&ars_state->lock); 594 if (time_before(jiffies, ars_state->deadline)) { 595 memset(ars_status, 0, buf_len); 596 ars_status->status = NFIT_ARS_STATUS_BUSY; 597 ars_status->out_length = sizeof(*ars_status); 598 *cmd_rc = -EBUSY; 599 } else { 600 memcpy(ars_status, ars_state->ars_status, 601 ars_state->ars_status->out_length); 602 *cmd_rc = 0; 603 } 604 spin_unlock(&ars_state->lock); 605 return 0; 606 } 607 608 static int nfit_test_cmd_clear_error(struct nfit_test *t, 609 struct nd_cmd_clear_error *clear_err, 610 unsigned int buf_len, int *cmd_rc) 611 { 612 const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1; 613 if (buf_len < sizeof(*clear_err)) 614 return -EINVAL; 615 616 if ((clear_err->address & mask) || (clear_err->length & mask)) 617 return -EINVAL; 618 619 badrange_forget(&t->badrange, clear_err->address, clear_err->length); 620 clear_err->status = 0; 621 clear_err->cleared = clear_err->length; 622 *cmd_rc = 0; 623 return 0; 624 } 625 626 struct region_search_spa { 627 u64 addr; 628 struct nd_region *region; 629 }; 630 631 static int is_region_device(struct device *dev) 632 { 633 return !strncmp(dev->kobj.name, "region", 6); 634 } 635 636 static int nfit_test_search_region_spa(struct device *dev, void *data) 637 { 638 struct region_search_spa *ctx = data; 639 struct nd_region *nd_region; 640 resource_size_t ndr_end; 641 642 if (!is_region_device(dev)) 643 return 0; 644 645 nd_region = to_nd_region(dev); 646 ndr_end = nd_region->ndr_start + nd_region->ndr_size; 647 648 if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) { 649 ctx->region = nd_region; 650 return 1; 651 } 652 653 return 0; 654 } 655 656 static int nfit_test_search_spa(struct nvdimm_bus *bus, 657 struct nd_cmd_translate_spa *spa) 658 { 659 int ret; 660 struct nd_region *nd_region = NULL; 661 struct nvdimm *nvdimm = NULL; 662 struct nd_mapping *nd_mapping = NULL; 663 struct region_search_spa ctx = { 664 .addr = spa->spa, 665 .region = NULL, 666 }; 667 u64 dpa; 668 669 ret = device_for_each_child(&bus->dev, &ctx, 670 nfit_test_search_region_spa); 671 672 if (!ret) 673 return -ENODEV; 674 675 nd_region = ctx.region; 676 677 dpa = ctx.addr - nd_region->ndr_start; 678 679 /* 680 * last dimm is selected for test 681 */ 682 nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1]; 683 nvdimm = nd_mapping->nvdimm; 684 685 spa->devices[0].nfit_device_handle = handle[nvdimm->id]; 686 spa->num_nvdimms = 1; 687 spa->devices[0].dpa = dpa; 688 689 return 0; 690 } 691 692 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus, 693 struct nd_cmd_translate_spa *spa, unsigned int buf_len) 694 { 695 if (buf_len < spa->translate_length) 696 return -EINVAL; 697 698 if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms) 699 spa->status = 2; 700 701 return 0; 702 } 703 704 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len, 705 struct nd_intel_smart *smart_data) 706 { 707 if (buf_len < sizeof(*smart)) 708 return -EINVAL; 709 memcpy(smart, smart_data, sizeof(*smart)); 710 return 0; 711 } 712 713 static int nfit_test_cmd_smart_threshold( 714 struct nd_intel_smart_threshold *out, 715 unsigned int buf_len, 716 struct nd_intel_smart_threshold *smart_t) 717 { 718 if (buf_len < sizeof(*smart_t)) 719 return -EINVAL; 720 memcpy(out, smart_t, sizeof(*smart_t)); 721 return 0; 722 } 723 724 static void smart_notify(struct device *bus_dev, 725 struct device *dimm_dev, struct nd_intel_smart *smart, 726 struct nd_intel_smart_threshold *thresh) 727 { 728 dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n", 729 __func__, thresh->alarm_control, thresh->spares, 730 smart->spares, thresh->media_temperature, 731 smart->media_temperature, thresh->ctrl_temperature, 732 smart->ctrl_temperature); 733 if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP) 734 && smart->spares 735 <= thresh->spares) 736 || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP) 737 && smart->media_temperature 738 >= thresh->media_temperature) 739 || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP) 740 && smart->ctrl_temperature 741 >= thresh->ctrl_temperature) 742 || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH) 743 || (smart->shutdown_state != 0)) { 744 device_lock(bus_dev); 745 __acpi_nvdimm_notify(dimm_dev, 0x81); 746 device_unlock(bus_dev); 747 } 748 } 749 750 static int nfit_test_cmd_smart_set_threshold( 751 struct nd_intel_smart_set_threshold *in, 752 unsigned int buf_len, 753 struct nd_intel_smart_threshold *thresh, 754 struct nd_intel_smart *smart, 755 struct device *bus_dev, struct device *dimm_dev) 756 { 757 unsigned int size; 758 759 size = sizeof(*in) - 4; 760 if (buf_len < size) 761 return -EINVAL; 762 memcpy(thresh->data, in, size); 763 in->status = 0; 764 smart_notify(bus_dev, dimm_dev, smart, thresh); 765 766 return 0; 767 } 768 769 static int nfit_test_cmd_smart_inject( 770 struct nd_intel_smart_inject *inj, 771 unsigned int buf_len, 772 struct nd_intel_smart_threshold *thresh, 773 struct nd_intel_smart *smart, 774 struct device *bus_dev, struct device *dimm_dev) 775 { 776 if (buf_len != sizeof(*inj)) 777 return -EINVAL; 778 779 if (inj->flags & ND_INTEL_SMART_INJECT_MTEMP) { 780 if (inj->mtemp_enable) 781 smart->media_temperature = inj->media_temperature; 782 else 783 smart->media_temperature = smart_def.media_temperature; 784 } 785 if (inj->flags & ND_INTEL_SMART_INJECT_SPARE) { 786 if (inj->spare_enable) 787 smart->spares = inj->spares; 788 else 789 smart->spares = smart_def.spares; 790 } 791 if (inj->flags & ND_INTEL_SMART_INJECT_FATAL) { 792 if (inj->fatal_enable) 793 smart->health = ND_INTEL_SMART_FATAL_HEALTH; 794 else 795 smart->health = ND_INTEL_SMART_NON_CRITICAL_HEALTH; 796 } 797 if (inj->flags & ND_INTEL_SMART_INJECT_SHUTDOWN) { 798 if (inj->unsafe_shutdown_enable) { 799 smart->shutdown_state = 1; 800 smart->shutdown_count++; 801 } else 802 smart->shutdown_state = 0; 803 } 804 inj->status = 0; 805 smart_notify(bus_dev, dimm_dev, smart, thresh); 806 807 return 0; 808 } 809 810 static void uc_error_notify(struct work_struct *work) 811 { 812 struct nfit_test *t = container_of(work, typeof(*t), work); 813 814 __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR); 815 } 816 817 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t, 818 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len) 819 { 820 int rc; 821 822 if (buf_len != sizeof(*err_inj)) { 823 rc = -EINVAL; 824 goto err; 825 } 826 827 if (err_inj->err_inj_spa_range_length <= 0) { 828 rc = -EINVAL; 829 goto err; 830 } 831 832 rc = badrange_add(&t->badrange, err_inj->err_inj_spa_range_base, 833 err_inj->err_inj_spa_range_length); 834 if (rc < 0) 835 goto err; 836 837 if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY)) 838 queue_work(nfit_wq, &t->work); 839 840 err_inj->status = 0; 841 return 0; 842 843 err: 844 err_inj->status = NFIT_ARS_INJECT_INVALID; 845 return rc; 846 } 847 848 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t, 849 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len) 850 { 851 int rc; 852 853 if (buf_len != sizeof(*err_clr)) { 854 rc = -EINVAL; 855 goto err; 856 } 857 858 if (err_clr->err_inj_clr_spa_range_length <= 0) { 859 rc = -EINVAL; 860 goto err; 861 } 862 863 badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base, 864 err_clr->err_inj_clr_spa_range_length); 865 866 err_clr->status = 0; 867 return 0; 868 869 err: 870 err_clr->status = NFIT_ARS_INJECT_INVALID; 871 return rc; 872 } 873 874 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t, 875 struct nd_cmd_ars_err_inj_stat *err_stat, 876 unsigned int buf_len) 877 { 878 struct badrange_entry *be; 879 int max = SZ_4K / sizeof(struct nd_error_stat_query_record); 880 int i = 0; 881 882 err_stat->status = 0; 883 spin_lock(&t->badrange.lock); 884 list_for_each_entry(be, &t->badrange.list, list) { 885 err_stat->record[i].err_inj_stat_spa_range_base = be->start; 886 err_stat->record[i].err_inj_stat_spa_range_length = be->length; 887 i++; 888 if (i > max) 889 break; 890 } 891 spin_unlock(&t->badrange.lock); 892 err_stat->inj_err_rec_count = i; 893 894 return 0; 895 } 896 897 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t, 898 struct nd_intel_lss *nd_cmd, unsigned int buf_len) 899 { 900 struct device *dev = &t->pdev.dev; 901 902 if (buf_len < sizeof(*nd_cmd)) 903 return -EINVAL; 904 905 switch (nd_cmd->enable) { 906 case 0: 907 nd_cmd->status = 0; 908 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n", 909 __func__); 910 break; 911 case 1: 912 nd_cmd->status = 0; 913 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n", 914 __func__); 915 break; 916 default: 917 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable); 918 nd_cmd->status = 0x3; 919 break; 920 } 921 922 923 return 0; 924 } 925 926 static int override_return_code(int dimm, unsigned int func, int rc) 927 { 928 if ((1 << func) & dimm_fail_cmd_flags[dimm]) { 929 if (dimm_fail_cmd_code[dimm]) 930 return dimm_fail_cmd_code[dimm]; 931 return -EIO; 932 } 933 return rc; 934 } 935 936 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func) 937 { 938 int i; 939 940 /* lookup per-dimm data */ 941 for (i = 0; i < ARRAY_SIZE(handle); i++) 942 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i]) 943 break; 944 if (i >= ARRAY_SIZE(handle)) 945 return -ENXIO; 946 return i; 947 } 948 949 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc, 950 struct nvdimm *nvdimm, unsigned int cmd, void *buf, 951 unsigned int buf_len, int *cmd_rc) 952 { 953 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); 954 struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc); 955 unsigned int func = cmd; 956 int i, rc = 0, __cmd_rc; 957 958 if (!cmd_rc) 959 cmd_rc = &__cmd_rc; 960 *cmd_rc = 0; 961 962 if (nvdimm) { 963 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); 964 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm); 965 966 if (!nfit_mem) 967 return -ENOTTY; 968 969 if (cmd == ND_CMD_CALL) { 970 struct nd_cmd_pkg *call_pkg = buf; 971 972 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out; 973 buf = (void *) call_pkg->nd_payload; 974 func = call_pkg->nd_command; 975 if (call_pkg->nd_family != nfit_mem->family) 976 return -ENOTTY; 977 978 i = get_dimm(nfit_mem, func); 979 if (i < 0) 980 return i; 981 982 switch (func) { 983 case ND_INTEL_ENABLE_LSS_STATUS: 984 rc = nd_intel_test_cmd_set_lss_status(t, 985 buf, buf_len); 986 break; 987 case ND_INTEL_FW_GET_INFO: 988 rc = nd_intel_test_get_fw_info(t, buf, 989 buf_len, i - t->dcr_idx); 990 break; 991 case ND_INTEL_FW_START_UPDATE: 992 rc = nd_intel_test_start_update(t, buf, 993 buf_len, i - t->dcr_idx); 994 break; 995 case ND_INTEL_FW_SEND_DATA: 996 rc = nd_intel_test_send_data(t, buf, 997 buf_len, i - t->dcr_idx); 998 break; 999 case ND_INTEL_FW_FINISH_UPDATE: 1000 rc = nd_intel_test_finish_fw(t, buf, 1001 buf_len, i - t->dcr_idx); 1002 break; 1003 case ND_INTEL_FW_FINISH_QUERY: 1004 rc = nd_intel_test_finish_query(t, buf, 1005 buf_len, i - t->dcr_idx); 1006 break; 1007 case ND_INTEL_SMART: 1008 rc = nfit_test_cmd_smart(buf, buf_len, 1009 &t->smart[i - t->dcr_idx]); 1010 break; 1011 case ND_INTEL_SMART_THRESHOLD: 1012 rc = nfit_test_cmd_smart_threshold(buf, 1013 buf_len, 1014 &t->smart_threshold[i - 1015 t->dcr_idx]); 1016 break; 1017 case ND_INTEL_SMART_SET_THRESHOLD: 1018 rc = nfit_test_cmd_smart_set_threshold(buf, 1019 buf_len, 1020 &t->smart_threshold[i - 1021 t->dcr_idx], 1022 &t->smart[i - t->dcr_idx], 1023 &t->pdev.dev, t->dimm_dev[i]); 1024 break; 1025 case ND_INTEL_SMART_INJECT: 1026 rc = nfit_test_cmd_smart_inject(buf, 1027 buf_len, 1028 &t->smart_threshold[i - 1029 t->dcr_idx], 1030 &t->smart[i - t->dcr_idx], 1031 &t->pdev.dev, t->dimm_dev[i]); 1032 break; 1033 default: 1034 return -ENOTTY; 1035 } 1036 return override_return_code(i, func, rc); 1037 } 1038 1039 if (!test_bit(cmd, &cmd_mask) 1040 || !test_bit(func, &nfit_mem->dsm_mask)) 1041 return -ENOTTY; 1042 1043 i = get_dimm(nfit_mem, func); 1044 if (i < 0) 1045 return i; 1046 1047 switch (func) { 1048 case ND_CMD_GET_CONFIG_SIZE: 1049 rc = nfit_test_cmd_get_config_size(buf, buf_len); 1050 break; 1051 case ND_CMD_GET_CONFIG_DATA: 1052 rc = nfit_test_cmd_get_config_data(buf, buf_len, 1053 t->label[i - t->dcr_idx]); 1054 break; 1055 case ND_CMD_SET_CONFIG_DATA: 1056 rc = nfit_test_cmd_set_config_data(buf, buf_len, 1057 t->label[i - t->dcr_idx]); 1058 break; 1059 default: 1060 return -ENOTTY; 1061 } 1062 return override_return_code(i, func, rc); 1063 } else { 1064 struct ars_state *ars_state = &t->ars_state; 1065 struct nd_cmd_pkg *call_pkg = buf; 1066 1067 if (!nd_desc) 1068 return -ENOTTY; 1069 1070 if (cmd == ND_CMD_CALL) { 1071 func = call_pkg->nd_command; 1072 1073 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out; 1074 buf = (void *) call_pkg->nd_payload; 1075 1076 switch (func) { 1077 case NFIT_CMD_TRANSLATE_SPA: 1078 rc = nfit_test_cmd_translate_spa( 1079 acpi_desc->nvdimm_bus, buf, buf_len); 1080 return rc; 1081 case NFIT_CMD_ARS_INJECT_SET: 1082 rc = nfit_test_cmd_ars_error_inject(t, buf, 1083 buf_len); 1084 return rc; 1085 case NFIT_CMD_ARS_INJECT_CLEAR: 1086 rc = nfit_test_cmd_ars_inject_clear(t, buf, 1087 buf_len); 1088 return rc; 1089 case NFIT_CMD_ARS_INJECT_GET: 1090 rc = nfit_test_cmd_ars_inject_status(t, buf, 1091 buf_len); 1092 return rc; 1093 default: 1094 return -ENOTTY; 1095 } 1096 } 1097 1098 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask)) 1099 return -ENOTTY; 1100 1101 switch (func) { 1102 case ND_CMD_ARS_CAP: 1103 rc = nfit_test_cmd_ars_cap(buf, buf_len); 1104 break; 1105 case ND_CMD_ARS_START: 1106 rc = nfit_test_cmd_ars_start(t, ars_state, buf, 1107 buf_len, cmd_rc); 1108 break; 1109 case ND_CMD_ARS_STATUS: 1110 rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len, 1111 cmd_rc); 1112 break; 1113 case ND_CMD_CLEAR_ERROR: 1114 rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc); 1115 break; 1116 default: 1117 return -ENOTTY; 1118 } 1119 } 1120 1121 return rc; 1122 } 1123 1124 static DEFINE_SPINLOCK(nfit_test_lock); 1125 static struct nfit_test *instances[NUM_NFITS]; 1126 1127 static void release_nfit_res(void *data) 1128 { 1129 struct nfit_test_resource *nfit_res = data; 1130 1131 spin_lock(&nfit_test_lock); 1132 list_del(&nfit_res->list); 1133 spin_unlock(&nfit_test_lock); 1134 1135 vfree(nfit_res->buf); 1136 kfree(nfit_res); 1137 } 1138 1139 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma, 1140 void *buf) 1141 { 1142 struct device *dev = &t->pdev.dev; 1143 struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res), 1144 GFP_KERNEL); 1145 int rc; 1146 1147 if (!buf || !nfit_res) 1148 goto err; 1149 rc = devm_add_action(dev, release_nfit_res, nfit_res); 1150 if (rc) 1151 goto err; 1152 INIT_LIST_HEAD(&nfit_res->list); 1153 memset(buf, 0, size); 1154 nfit_res->dev = dev; 1155 nfit_res->buf = buf; 1156 nfit_res->res.start = *dma; 1157 nfit_res->res.end = *dma + size - 1; 1158 nfit_res->res.name = "NFIT"; 1159 spin_lock_init(&nfit_res->lock); 1160 INIT_LIST_HEAD(&nfit_res->requests); 1161 spin_lock(&nfit_test_lock); 1162 list_add(&nfit_res->list, &t->resources); 1163 spin_unlock(&nfit_test_lock); 1164 1165 return nfit_res->buf; 1166 err: 1167 if (buf) 1168 vfree(buf); 1169 kfree(nfit_res); 1170 return NULL; 1171 } 1172 1173 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma) 1174 { 1175 void *buf = vmalloc(size); 1176 1177 *dma = (unsigned long) buf; 1178 return __test_alloc(t, size, dma, buf); 1179 } 1180 1181 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr) 1182 { 1183 int i; 1184 1185 for (i = 0; i < ARRAY_SIZE(instances); i++) { 1186 struct nfit_test_resource *n, *nfit_res = NULL; 1187 struct nfit_test *t = instances[i]; 1188 1189 if (!t) 1190 continue; 1191 spin_lock(&nfit_test_lock); 1192 list_for_each_entry(n, &t->resources, list) { 1193 if (addr >= n->res.start && (addr < n->res.start 1194 + resource_size(&n->res))) { 1195 nfit_res = n; 1196 break; 1197 } else if (addr >= (unsigned long) n->buf 1198 && (addr < (unsigned long) n->buf 1199 + resource_size(&n->res))) { 1200 nfit_res = n; 1201 break; 1202 } 1203 } 1204 spin_unlock(&nfit_test_lock); 1205 if (nfit_res) 1206 return nfit_res; 1207 } 1208 1209 return NULL; 1210 } 1211 1212 static int ars_state_init(struct device *dev, struct ars_state *ars_state) 1213 { 1214 /* for testing, only store up to n records that fit within 4k */ 1215 ars_state->ars_status = devm_kzalloc(dev, 1216 sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL); 1217 if (!ars_state->ars_status) 1218 return -ENOMEM; 1219 spin_lock_init(&ars_state->lock); 1220 return 0; 1221 } 1222 1223 static void put_dimms(void *data) 1224 { 1225 struct nfit_test *t = data; 1226 int i; 1227 1228 for (i = 0; i < t->num_dcr; i++) 1229 if (t->dimm_dev[i]) 1230 device_unregister(t->dimm_dev[i]); 1231 } 1232 1233 static struct class *nfit_test_dimm; 1234 1235 static int dimm_name_to_id(struct device *dev) 1236 { 1237 int dimm; 1238 1239 if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1) 1240 return -ENXIO; 1241 return dimm; 1242 } 1243 1244 static ssize_t handle_show(struct device *dev, struct device_attribute *attr, 1245 char *buf) 1246 { 1247 int dimm = dimm_name_to_id(dev); 1248 1249 if (dimm < 0) 1250 return dimm; 1251 1252 return sprintf(buf, "%#x\n", handle[dimm]); 1253 } 1254 DEVICE_ATTR_RO(handle); 1255 1256 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr, 1257 char *buf) 1258 { 1259 int dimm = dimm_name_to_id(dev); 1260 1261 if (dimm < 0) 1262 return dimm; 1263 1264 return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]); 1265 } 1266 1267 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr, 1268 const char *buf, size_t size) 1269 { 1270 int dimm = dimm_name_to_id(dev); 1271 unsigned long val; 1272 ssize_t rc; 1273 1274 if (dimm < 0) 1275 return dimm; 1276 1277 rc = kstrtol(buf, 0, &val); 1278 if (rc) 1279 return rc; 1280 1281 dimm_fail_cmd_flags[dimm] = val; 1282 return size; 1283 } 1284 static DEVICE_ATTR_RW(fail_cmd); 1285 1286 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr, 1287 char *buf) 1288 { 1289 int dimm = dimm_name_to_id(dev); 1290 1291 if (dimm < 0) 1292 return dimm; 1293 1294 return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]); 1295 } 1296 1297 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr, 1298 const char *buf, size_t size) 1299 { 1300 int dimm = dimm_name_to_id(dev); 1301 unsigned long val; 1302 ssize_t rc; 1303 1304 if (dimm < 0) 1305 return dimm; 1306 1307 rc = kstrtol(buf, 0, &val); 1308 if (rc) 1309 return rc; 1310 1311 dimm_fail_cmd_code[dimm] = val; 1312 return size; 1313 } 1314 static DEVICE_ATTR_RW(fail_cmd_code); 1315 1316 static struct attribute *nfit_test_dimm_attributes[] = { 1317 &dev_attr_fail_cmd.attr, 1318 &dev_attr_fail_cmd_code.attr, 1319 &dev_attr_handle.attr, 1320 NULL, 1321 }; 1322 1323 static struct attribute_group nfit_test_dimm_attribute_group = { 1324 .attrs = nfit_test_dimm_attributes, 1325 }; 1326 1327 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = { 1328 &nfit_test_dimm_attribute_group, 1329 NULL, 1330 }; 1331 1332 static int nfit_test_dimm_init(struct nfit_test *t) 1333 { 1334 int i; 1335 1336 if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t)) 1337 return -ENOMEM; 1338 for (i = 0; i < t->num_dcr; i++) { 1339 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm, 1340 &t->pdev.dev, 0, NULL, 1341 nfit_test_dimm_attribute_groups, 1342 "test_dimm%d", i + t->dcr_idx); 1343 if (!t->dimm_dev[i]) 1344 return -ENOMEM; 1345 } 1346 return 0; 1347 } 1348 1349 static void smart_init(struct nfit_test *t) 1350 { 1351 int i; 1352 const struct nd_intel_smart_threshold smart_t_data = { 1353 .alarm_control = ND_INTEL_SMART_SPARE_TRIP 1354 | ND_INTEL_SMART_TEMP_TRIP, 1355 .media_temperature = 40 * 16, 1356 .ctrl_temperature = 30 * 16, 1357 .spares = 5, 1358 }; 1359 1360 for (i = 0; i < t->num_dcr; i++) { 1361 memcpy(&t->smart[i], &smart_def, sizeof(smart_def)); 1362 memcpy(&t->smart_threshold[i], &smart_t_data, 1363 sizeof(smart_t_data)); 1364 } 1365 } 1366 1367 static int nfit_test0_alloc(struct nfit_test *t) 1368 { 1369 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA 1370 + sizeof(struct acpi_nfit_memory_map) * NUM_MEM 1371 + sizeof(struct acpi_nfit_control_region) * NUM_DCR 1372 + offsetof(struct acpi_nfit_control_region, 1373 window_size) * NUM_DCR 1374 + sizeof(struct acpi_nfit_data_region) * NUM_BDW 1375 + (sizeof(struct acpi_nfit_flush_address) 1376 + sizeof(u64) * NUM_HINTS) * NUM_DCR 1377 + sizeof(struct acpi_nfit_capabilities); 1378 int i; 1379 1380 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma); 1381 if (!t->nfit_buf) 1382 return -ENOMEM; 1383 t->nfit_size = nfit_size; 1384 1385 t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]); 1386 if (!t->spa_set[0]) 1387 return -ENOMEM; 1388 1389 t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]); 1390 if (!t->spa_set[1]) 1391 return -ENOMEM; 1392 1393 t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]); 1394 if (!t->spa_set[2]) 1395 return -ENOMEM; 1396 1397 for (i = 0; i < t->num_dcr; i++) { 1398 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]); 1399 if (!t->dimm[i]) 1400 return -ENOMEM; 1401 1402 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]); 1403 if (!t->label[i]) 1404 return -ENOMEM; 1405 sprintf(t->label[i], "label%d", i); 1406 1407 t->flush[i] = test_alloc(t, max(PAGE_SIZE, 1408 sizeof(u64) * NUM_HINTS), 1409 &t->flush_dma[i]); 1410 if (!t->flush[i]) 1411 return -ENOMEM; 1412 } 1413 1414 for (i = 0; i < t->num_dcr; i++) { 1415 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]); 1416 if (!t->dcr[i]) 1417 return -ENOMEM; 1418 } 1419 1420 t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma); 1421 if (!t->_fit) 1422 return -ENOMEM; 1423 1424 if (nfit_test_dimm_init(t)) 1425 return -ENOMEM; 1426 smart_init(t); 1427 return ars_state_init(&t->pdev.dev, &t->ars_state); 1428 } 1429 1430 static int nfit_test1_alloc(struct nfit_test *t) 1431 { 1432 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2 1433 + sizeof(struct acpi_nfit_memory_map) * 2 1434 + offsetof(struct acpi_nfit_control_region, window_size) * 2; 1435 int i; 1436 1437 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma); 1438 if (!t->nfit_buf) 1439 return -ENOMEM; 1440 t->nfit_size = nfit_size; 1441 1442 t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]); 1443 if (!t->spa_set[0]) 1444 return -ENOMEM; 1445 1446 for (i = 0; i < t->num_dcr; i++) { 1447 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]); 1448 if (!t->label[i]) 1449 return -ENOMEM; 1450 sprintf(t->label[i], "label%d", i); 1451 } 1452 1453 t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]); 1454 if (!t->spa_set[1]) 1455 return -ENOMEM; 1456 1457 if (nfit_test_dimm_init(t)) 1458 return -ENOMEM; 1459 smart_init(t); 1460 return ars_state_init(&t->pdev.dev, &t->ars_state); 1461 } 1462 1463 static void dcr_common_init(struct acpi_nfit_control_region *dcr) 1464 { 1465 dcr->vendor_id = 0xabcd; 1466 dcr->device_id = 0; 1467 dcr->revision_id = 1; 1468 dcr->valid_fields = 1; 1469 dcr->manufacturing_location = 0xa; 1470 dcr->manufacturing_date = cpu_to_be16(2016); 1471 } 1472 1473 static void nfit_test0_setup(struct nfit_test *t) 1474 { 1475 const int flush_hint_size = sizeof(struct acpi_nfit_flush_address) 1476 + (sizeof(u64) * NUM_HINTS); 1477 struct acpi_nfit_desc *acpi_desc; 1478 struct acpi_nfit_memory_map *memdev; 1479 void *nfit_buf = t->nfit_buf; 1480 struct acpi_nfit_system_address *spa; 1481 struct acpi_nfit_control_region *dcr; 1482 struct acpi_nfit_data_region *bdw; 1483 struct acpi_nfit_flush_address *flush; 1484 struct acpi_nfit_capabilities *pcap; 1485 unsigned int offset = 0, i; 1486 1487 /* 1488 * spa0 (interleave first half of dimm0 and dimm1, note storage 1489 * does not actually alias the related block-data-window 1490 * regions) 1491 */ 1492 spa = nfit_buf; 1493 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1494 spa->header.length = sizeof(*spa); 1495 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 1496 spa->range_index = 0+1; 1497 spa->address = t->spa_set_dma[0]; 1498 spa->length = SPA0_SIZE; 1499 offset += spa->header.length; 1500 1501 /* 1502 * spa1 (interleave last half of the 4 DIMMS, note storage 1503 * does not actually alias the related block-data-window 1504 * regions) 1505 */ 1506 spa = nfit_buf + offset; 1507 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1508 spa->header.length = sizeof(*spa); 1509 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 1510 spa->range_index = 1+1; 1511 spa->address = t->spa_set_dma[1]; 1512 spa->length = SPA1_SIZE; 1513 offset += spa->header.length; 1514 1515 /* spa2 (dcr0) dimm0 */ 1516 spa = nfit_buf + offset; 1517 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1518 spa->header.length = sizeof(*spa); 1519 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1520 spa->range_index = 2+1; 1521 spa->address = t->dcr_dma[0]; 1522 spa->length = DCR_SIZE; 1523 offset += spa->header.length; 1524 1525 /* spa3 (dcr1) dimm1 */ 1526 spa = nfit_buf + offset; 1527 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1528 spa->header.length = sizeof(*spa); 1529 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1530 spa->range_index = 3+1; 1531 spa->address = t->dcr_dma[1]; 1532 spa->length = DCR_SIZE; 1533 offset += spa->header.length; 1534 1535 /* spa4 (dcr2) dimm2 */ 1536 spa = nfit_buf + offset; 1537 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1538 spa->header.length = sizeof(*spa); 1539 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1540 spa->range_index = 4+1; 1541 spa->address = t->dcr_dma[2]; 1542 spa->length = DCR_SIZE; 1543 offset += spa->header.length; 1544 1545 /* spa5 (dcr3) dimm3 */ 1546 spa = nfit_buf + offset; 1547 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1548 spa->header.length = sizeof(*spa); 1549 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1550 spa->range_index = 5+1; 1551 spa->address = t->dcr_dma[3]; 1552 spa->length = DCR_SIZE; 1553 offset += spa->header.length; 1554 1555 /* spa6 (bdw for dcr0) dimm0 */ 1556 spa = nfit_buf + offset; 1557 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1558 spa->header.length = sizeof(*spa); 1559 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1560 spa->range_index = 6+1; 1561 spa->address = t->dimm_dma[0]; 1562 spa->length = DIMM_SIZE; 1563 offset += spa->header.length; 1564 1565 /* spa7 (bdw for dcr1) dimm1 */ 1566 spa = nfit_buf + offset; 1567 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1568 spa->header.length = sizeof(*spa); 1569 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1570 spa->range_index = 7+1; 1571 spa->address = t->dimm_dma[1]; 1572 spa->length = DIMM_SIZE; 1573 offset += spa->header.length; 1574 1575 /* spa8 (bdw for dcr2) dimm2 */ 1576 spa = nfit_buf + offset; 1577 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1578 spa->header.length = sizeof(*spa); 1579 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1580 spa->range_index = 8+1; 1581 spa->address = t->dimm_dma[2]; 1582 spa->length = DIMM_SIZE; 1583 offset += spa->header.length; 1584 1585 /* spa9 (bdw for dcr3) dimm3 */ 1586 spa = nfit_buf + offset; 1587 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1588 spa->header.length = sizeof(*spa); 1589 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1590 spa->range_index = 9+1; 1591 spa->address = t->dimm_dma[3]; 1592 spa->length = DIMM_SIZE; 1593 offset += spa->header.length; 1594 1595 /* mem-region0 (spa0, dimm0) */ 1596 memdev = nfit_buf + offset; 1597 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1598 memdev->header.length = sizeof(*memdev); 1599 memdev->device_handle = handle[0]; 1600 memdev->physical_id = 0; 1601 memdev->region_id = 0; 1602 memdev->range_index = 0+1; 1603 memdev->region_index = 4+1; 1604 memdev->region_size = SPA0_SIZE/2; 1605 memdev->region_offset = 1; 1606 memdev->address = 0; 1607 memdev->interleave_index = 0; 1608 memdev->interleave_ways = 2; 1609 offset += memdev->header.length; 1610 1611 /* mem-region1 (spa0, dimm1) */ 1612 memdev = nfit_buf + offset; 1613 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1614 memdev->header.length = sizeof(*memdev); 1615 memdev->device_handle = handle[1]; 1616 memdev->physical_id = 1; 1617 memdev->region_id = 0; 1618 memdev->range_index = 0+1; 1619 memdev->region_index = 5+1; 1620 memdev->region_size = SPA0_SIZE/2; 1621 memdev->region_offset = (1 << 8); 1622 memdev->address = 0; 1623 memdev->interleave_index = 0; 1624 memdev->interleave_ways = 2; 1625 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1626 offset += memdev->header.length; 1627 1628 /* mem-region2 (spa1, dimm0) */ 1629 memdev = nfit_buf + offset; 1630 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1631 memdev->header.length = sizeof(*memdev); 1632 memdev->device_handle = handle[0]; 1633 memdev->physical_id = 0; 1634 memdev->region_id = 1; 1635 memdev->range_index = 1+1; 1636 memdev->region_index = 4+1; 1637 memdev->region_size = SPA1_SIZE/4; 1638 memdev->region_offset = (1 << 16); 1639 memdev->address = SPA0_SIZE/2; 1640 memdev->interleave_index = 0; 1641 memdev->interleave_ways = 4; 1642 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1643 offset += memdev->header.length; 1644 1645 /* mem-region3 (spa1, dimm1) */ 1646 memdev = nfit_buf + offset; 1647 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1648 memdev->header.length = sizeof(*memdev); 1649 memdev->device_handle = handle[1]; 1650 memdev->physical_id = 1; 1651 memdev->region_id = 1; 1652 memdev->range_index = 1+1; 1653 memdev->region_index = 5+1; 1654 memdev->region_size = SPA1_SIZE/4; 1655 memdev->region_offset = (1 << 24); 1656 memdev->address = SPA0_SIZE/2; 1657 memdev->interleave_index = 0; 1658 memdev->interleave_ways = 4; 1659 offset += memdev->header.length; 1660 1661 /* mem-region4 (spa1, dimm2) */ 1662 memdev = nfit_buf + offset; 1663 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1664 memdev->header.length = sizeof(*memdev); 1665 memdev->device_handle = handle[2]; 1666 memdev->physical_id = 2; 1667 memdev->region_id = 0; 1668 memdev->range_index = 1+1; 1669 memdev->region_index = 6+1; 1670 memdev->region_size = SPA1_SIZE/4; 1671 memdev->region_offset = (1ULL << 32); 1672 memdev->address = SPA0_SIZE/2; 1673 memdev->interleave_index = 0; 1674 memdev->interleave_ways = 4; 1675 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1676 offset += memdev->header.length; 1677 1678 /* mem-region5 (spa1, dimm3) */ 1679 memdev = nfit_buf + offset; 1680 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1681 memdev->header.length = sizeof(*memdev); 1682 memdev->device_handle = handle[3]; 1683 memdev->physical_id = 3; 1684 memdev->region_id = 0; 1685 memdev->range_index = 1+1; 1686 memdev->region_index = 7+1; 1687 memdev->region_size = SPA1_SIZE/4; 1688 memdev->region_offset = (1ULL << 40); 1689 memdev->address = SPA0_SIZE/2; 1690 memdev->interleave_index = 0; 1691 memdev->interleave_ways = 4; 1692 offset += memdev->header.length; 1693 1694 /* mem-region6 (spa/dcr0, dimm0) */ 1695 memdev = nfit_buf + offset; 1696 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1697 memdev->header.length = sizeof(*memdev); 1698 memdev->device_handle = handle[0]; 1699 memdev->physical_id = 0; 1700 memdev->region_id = 0; 1701 memdev->range_index = 2+1; 1702 memdev->region_index = 0+1; 1703 memdev->region_size = 0; 1704 memdev->region_offset = 0; 1705 memdev->address = 0; 1706 memdev->interleave_index = 0; 1707 memdev->interleave_ways = 1; 1708 offset += memdev->header.length; 1709 1710 /* mem-region7 (spa/dcr1, dimm1) */ 1711 memdev = nfit_buf + offset; 1712 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1713 memdev->header.length = sizeof(*memdev); 1714 memdev->device_handle = handle[1]; 1715 memdev->physical_id = 1; 1716 memdev->region_id = 0; 1717 memdev->range_index = 3+1; 1718 memdev->region_index = 1+1; 1719 memdev->region_size = 0; 1720 memdev->region_offset = 0; 1721 memdev->address = 0; 1722 memdev->interleave_index = 0; 1723 memdev->interleave_ways = 1; 1724 offset += memdev->header.length; 1725 1726 /* mem-region8 (spa/dcr2, dimm2) */ 1727 memdev = nfit_buf + offset; 1728 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1729 memdev->header.length = sizeof(*memdev); 1730 memdev->device_handle = handle[2]; 1731 memdev->physical_id = 2; 1732 memdev->region_id = 0; 1733 memdev->range_index = 4+1; 1734 memdev->region_index = 2+1; 1735 memdev->region_size = 0; 1736 memdev->region_offset = 0; 1737 memdev->address = 0; 1738 memdev->interleave_index = 0; 1739 memdev->interleave_ways = 1; 1740 offset += memdev->header.length; 1741 1742 /* mem-region9 (spa/dcr3, dimm3) */ 1743 memdev = nfit_buf + offset; 1744 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1745 memdev->header.length = sizeof(*memdev); 1746 memdev->device_handle = handle[3]; 1747 memdev->physical_id = 3; 1748 memdev->region_id = 0; 1749 memdev->range_index = 5+1; 1750 memdev->region_index = 3+1; 1751 memdev->region_size = 0; 1752 memdev->region_offset = 0; 1753 memdev->address = 0; 1754 memdev->interleave_index = 0; 1755 memdev->interleave_ways = 1; 1756 offset += memdev->header.length; 1757 1758 /* mem-region10 (spa/bdw0, dimm0) */ 1759 memdev = nfit_buf + offset; 1760 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1761 memdev->header.length = sizeof(*memdev); 1762 memdev->device_handle = handle[0]; 1763 memdev->physical_id = 0; 1764 memdev->region_id = 0; 1765 memdev->range_index = 6+1; 1766 memdev->region_index = 0+1; 1767 memdev->region_size = 0; 1768 memdev->region_offset = 0; 1769 memdev->address = 0; 1770 memdev->interleave_index = 0; 1771 memdev->interleave_ways = 1; 1772 offset += memdev->header.length; 1773 1774 /* mem-region11 (spa/bdw1, dimm1) */ 1775 memdev = nfit_buf + offset; 1776 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1777 memdev->header.length = sizeof(*memdev); 1778 memdev->device_handle = handle[1]; 1779 memdev->physical_id = 1; 1780 memdev->region_id = 0; 1781 memdev->range_index = 7+1; 1782 memdev->region_index = 1+1; 1783 memdev->region_size = 0; 1784 memdev->region_offset = 0; 1785 memdev->address = 0; 1786 memdev->interleave_index = 0; 1787 memdev->interleave_ways = 1; 1788 offset += memdev->header.length; 1789 1790 /* mem-region12 (spa/bdw2, dimm2) */ 1791 memdev = nfit_buf + offset; 1792 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1793 memdev->header.length = sizeof(*memdev); 1794 memdev->device_handle = handle[2]; 1795 memdev->physical_id = 2; 1796 memdev->region_id = 0; 1797 memdev->range_index = 8+1; 1798 memdev->region_index = 2+1; 1799 memdev->region_size = 0; 1800 memdev->region_offset = 0; 1801 memdev->address = 0; 1802 memdev->interleave_index = 0; 1803 memdev->interleave_ways = 1; 1804 offset += memdev->header.length; 1805 1806 /* mem-region13 (spa/dcr3, dimm3) */ 1807 memdev = nfit_buf + offset; 1808 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1809 memdev->header.length = sizeof(*memdev); 1810 memdev->device_handle = handle[3]; 1811 memdev->physical_id = 3; 1812 memdev->region_id = 0; 1813 memdev->range_index = 9+1; 1814 memdev->region_index = 3+1; 1815 memdev->region_size = 0; 1816 memdev->region_offset = 0; 1817 memdev->address = 0; 1818 memdev->interleave_index = 0; 1819 memdev->interleave_ways = 1; 1820 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1821 offset += memdev->header.length; 1822 1823 /* dcr-descriptor0: blk */ 1824 dcr = nfit_buf + offset; 1825 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1826 dcr->header.length = sizeof(*dcr); 1827 dcr->region_index = 0+1; 1828 dcr_common_init(dcr); 1829 dcr->serial_number = ~handle[0]; 1830 dcr->code = NFIT_FIC_BLK; 1831 dcr->windows = 1; 1832 dcr->window_size = DCR_SIZE; 1833 dcr->command_offset = 0; 1834 dcr->command_size = 8; 1835 dcr->status_offset = 8; 1836 dcr->status_size = 4; 1837 offset += dcr->header.length; 1838 1839 /* dcr-descriptor1: blk */ 1840 dcr = nfit_buf + offset; 1841 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1842 dcr->header.length = sizeof(*dcr); 1843 dcr->region_index = 1+1; 1844 dcr_common_init(dcr); 1845 dcr->serial_number = ~handle[1]; 1846 dcr->code = NFIT_FIC_BLK; 1847 dcr->windows = 1; 1848 dcr->window_size = DCR_SIZE; 1849 dcr->command_offset = 0; 1850 dcr->command_size = 8; 1851 dcr->status_offset = 8; 1852 dcr->status_size = 4; 1853 offset += dcr->header.length; 1854 1855 /* dcr-descriptor2: blk */ 1856 dcr = nfit_buf + offset; 1857 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1858 dcr->header.length = sizeof(*dcr); 1859 dcr->region_index = 2+1; 1860 dcr_common_init(dcr); 1861 dcr->serial_number = ~handle[2]; 1862 dcr->code = NFIT_FIC_BLK; 1863 dcr->windows = 1; 1864 dcr->window_size = DCR_SIZE; 1865 dcr->command_offset = 0; 1866 dcr->command_size = 8; 1867 dcr->status_offset = 8; 1868 dcr->status_size = 4; 1869 offset += dcr->header.length; 1870 1871 /* dcr-descriptor3: blk */ 1872 dcr = nfit_buf + offset; 1873 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1874 dcr->header.length = sizeof(*dcr); 1875 dcr->region_index = 3+1; 1876 dcr_common_init(dcr); 1877 dcr->serial_number = ~handle[3]; 1878 dcr->code = NFIT_FIC_BLK; 1879 dcr->windows = 1; 1880 dcr->window_size = DCR_SIZE; 1881 dcr->command_offset = 0; 1882 dcr->command_size = 8; 1883 dcr->status_offset = 8; 1884 dcr->status_size = 4; 1885 offset += dcr->header.length; 1886 1887 /* dcr-descriptor0: pmem */ 1888 dcr = nfit_buf + offset; 1889 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1890 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1891 window_size); 1892 dcr->region_index = 4+1; 1893 dcr_common_init(dcr); 1894 dcr->serial_number = ~handle[0]; 1895 dcr->code = NFIT_FIC_BYTEN; 1896 dcr->windows = 0; 1897 offset += dcr->header.length; 1898 1899 /* dcr-descriptor1: pmem */ 1900 dcr = nfit_buf + offset; 1901 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1902 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1903 window_size); 1904 dcr->region_index = 5+1; 1905 dcr_common_init(dcr); 1906 dcr->serial_number = ~handle[1]; 1907 dcr->code = NFIT_FIC_BYTEN; 1908 dcr->windows = 0; 1909 offset += dcr->header.length; 1910 1911 /* dcr-descriptor2: pmem */ 1912 dcr = nfit_buf + offset; 1913 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1914 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1915 window_size); 1916 dcr->region_index = 6+1; 1917 dcr_common_init(dcr); 1918 dcr->serial_number = ~handle[2]; 1919 dcr->code = NFIT_FIC_BYTEN; 1920 dcr->windows = 0; 1921 offset += dcr->header.length; 1922 1923 /* dcr-descriptor3: pmem */ 1924 dcr = nfit_buf + offset; 1925 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1926 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1927 window_size); 1928 dcr->region_index = 7+1; 1929 dcr_common_init(dcr); 1930 dcr->serial_number = ~handle[3]; 1931 dcr->code = NFIT_FIC_BYTEN; 1932 dcr->windows = 0; 1933 offset += dcr->header.length; 1934 1935 /* bdw0 (spa/dcr0, dimm0) */ 1936 bdw = nfit_buf + offset; 1937 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1938 bdw->header.length = sizeof(*bdw); 1939 bdw->region_index = 0+1; 1940 bdw->windows = 1; 1941 bdw->offset = 0; 1942 bdw->size = BDW_SIZE; 1943 bdw->capacity = DIMM_SIZE; 1944 bdw->start_address = 0; 1945 offset += bdw->header.length; 1946 1947 /* bdw1 (spa/dcr1, dimm1) */ 1948 bdw = nfit_buf + offset; 1949 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1950 bdw->header.length = sizeof(*bdw); 1951 bdw->region_index = 1+1; 1952 bdw->windows = 1; 1953 bdw->offset = 0; 1954 bdw->size = BDW_SIZE; 1955 bdw->capacity = DIMM_SIZE; 1956 bdw->start_address = 0; 1957 offset += bdw->header.length; 1958 1959 /* bdw2 (spa/dcr2, dimm2) */ 1960 bdw = nfit_buf + offset; 1961 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1962 bdw->header.length = sizeof(*bdw); 1963 bdw->region_index = 2+1; 1964 bdw->windows = 1; 1965 bdw->offset = 0; 1966 bdw->size = BDW_SIZE; 1967 bdw->capacity = DIMM_SIZE; 1968 bdw->start_address = 0; 1969 offset += bdw->header.length; 1970 1971 /* bdw3 (spa/dcr3, dimm3) */ 1972 bdw = nfit_buf + offset; 1973 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1974 bdw->header.length = sizeof(*bdw); 1975 bdw->region_index = 3+1; 1976 bdw->windows = 1; 1977 bdw->offset = 0; 1978 bdw->size = BDW_SIZE; 1979 bdw->capacity = DIMM_SIZE; 1980 bdw->start_address = 0; 1981 offset += bdw->header.length; 1982 1983 /* flush0 (dimm0) */ 1984 flush = nfit_buf + offset; 1985 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 1986 flush->header.length = flush_hint_size; 1987 flush->device_handle = handle[0]; 1988 flush->hint_count = NUM_HINTS; 1989 for (i = 0; i < NUM_HINTS; i++) 1990 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64); 1991 offset += flush->header.length; 1992 1993 /* flush1 (dimm1) */ 1994 flush = nfit_buf + offset; 1995 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 1996 flush->header.length = flush_hint_size; 1997 flush->device_handle = handle[1]; 1998 flush->hint_count = NUM_HINTS; 1999 for (i = 0; i < NUM_HINTS; i++) 2000 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64); 2001 offset += flush->header.length; 2002 2003 /* flush2 (dimm2) */ 2004 flush = nfit_buf + offset; 2005 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2006 flush->header.length = flush_hint_size; 2007 flush->device_handle = handle[2]; 2008 flush->hint_count = NUM_HINTS; 2009 for (i = 0; i < NUM_HINTS; i++) 2010 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64); 2011 offset += flush->header.length; 2012 2013 /* flush3 (dimm3) */ 2014 flush = nfit_buf + offset; 2015 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2016 flush->header.length = flush_hint_size; 2017 flush->device_handle = handle[3]; 2018 flush->hint_count = NUM_HINTS; 2019 for (i = 0; i < NUM_HINTS; i++) 2020 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64); 2021 offset += flush->header.length; 2022 2023 /* platform capabilities */ 2024 pcap = nfit_buf + offset; 2025 pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES; 2026 pcap->header.length = sizeof(*pcap); 2027 pcap->highest_capability = 1; 2028 pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH; 2029 offset += pcap->header.length; 2030 2031 if (t->setup_hotplug) { 2032 /* dcr-descriptor4: blk */ 2033 dcr = nfit_buf + offset; 2034 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2035 dcr->header.length = sizeof(*dcr); 2036 dcr->region_index = 8+1; 2037 dcr_common_init(dcr); 2038 dcr->serial_number = ~handle[4]; 2039 dcr->code = NFIT_FIC_BLK; 2040 dcr->windows = 1; 2041 dcr->window_size = DCR_SIZE; 2042 dcr->command_offset = 0; 2043 dcr->command_size = 8; 2044 dcr->status_offset = 8; 2045 dcr->status_size = 4; 2046 offset += dcr->header.length; 2047 2048 /* dcr-descriptor4: pmem */ 2049 dcr = nfit_buf + offset; 2050 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2051 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2052 window_size); 2053 dcr->region_index = 9+1; 2054 dcr_common_init(dcr); 2055 dcr->serial_number = ~handle[4]; 2056 dcr->code = NFIT_FIC_BYTEN; 2057 dcr->windows = 0; 2058 offset += dcr->header.length; 2059 2060 /* bdw4 (spa/dcr4, dimm4) */ 2061 bdw = nfit_buf + offset; 2062 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 2063 bdw->header.length = sizeof(*bdw); 2064 bdw->region_index = 8+1; 2065 bdw->windows = 1; 2066 bdw->offset = 0; 2067 bdw->size = BDW_SIZE; 2068 bdw->capacity = DIMM_SIZE; 2069 bdw->start_address = 0; 2070 offset += bdw->header.length; 2071 2072 /* spa10 (dcr4) dimm4 */ 2073 spa = nfit_buf + offset; 2074 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2075 spa->header.length = sizeof(*spa); 2076 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 2077 spa->range_index = 10+1; 2078 spa->address = t->dcr_dma[4]; 2079 spa->length = DCR_SIZE; 2080 offset += spa->header.length; 2081 2082 /* 2083 * spa11 (single-dimm interleave for hotplug, note storage 2084 * does not actually alias the related block-data-window 2085 * regions) 2086 */ 2087 spa = nfit_buf + offset; 2088 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2089 spa->header.length = sizeof(*spa); 2090 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 2091 spa->range_index = 11+1; 2092 spa->address = t->spa_set_dma[2]; 2093 spa->length = SPA0_SIZE; 2094 offset += spa->header.length; 2095 2096 /* spa12 (bdw for dcr4) dimm4 */ 2097 spa = nfit_buf + offset; 2098 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2099 spa->header.length = sizeof(*spa); 2100 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 2101 spa->range_index = 12+1; 2102 spa->address = t->dimm_dma[4]; 2103 spa->length = DIMM_SIZE; 2104 offset += spa->header.length; 2105 2106 /* mem-region14 (spa/dcr4, dimm4) */ 2107 memdev = nfit_buf + offset; 2108 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2109 memdev->header.length = sizeof(*memdev); 2110 memdev->device_handle = handle[4]; 2111 memdev->physical_id = 4; 2112 memdev->region_id = 0; 2113 memdev->range_index = 10+1; 2114 memdev->region_index = 8+1; 2115 memdev->region_size = 0; 2116 memdev->region_offset = 0; 2117 memdev->address = 0; 2118 memdev->interleave_index = 0; 2119 memdev->interleave_ways = 1; 2120 offset += memdev->header.length; 2121 2122 /* mem-region15 (spa11, dimm4) */ 2123 memdev = nfit_buf + offset; 2124 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2125 memdev->header.length = sizeof(*memdev); 2126 memdev->device_handle = handle[4]; 2127 memdev->physical_id = 4; 2128 memdev->region_id = 0; 2129 memdev->range_index = 11+1; 2130 memdev->region_index = 9+1; 2131 memdev->region_size = SPA0_SIZE; 2132 memdev->region_offset = (1ULL << 48); 2133 memdev->address = 0; 2134 memdev->interleave_index = 0; 2135 memdev->interleave_ways = 1; 2136 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 2137 offset += memdev->header.length; 2138 2139 /* mem-region16 (spa/bdw4, dimm4) */ 2140 memdev = nfit_buf + offset; 2141 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2142 memdev->header.length = sizeof(*memdev); 2143 memdev->device_handle = handle[4]; 2144 memdev->physical_id = 4; 2145 memdev->region_id = 0; 2146 memdev->range_index = 12+1; 2147 memdev->region_index = 8+1; 2148 memdev->region_size = 0; 2149 memdev->region_offset = 0; 2150 memdev->address = 0; 2151 memdev->interleave_index = 0; 2152 memdev->interleave_ways = 1; 2153 offset += memdev->header.length; 2154 2155 /* flush3 (dimm4) */ 2156 flush = nfit_buf + offset; 2157 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2158 flush->header.length = flush_hint_size; 2159 flush->device_handle = handle[4]; 2160 flush->hint_count = NUM_HINTS; 2161 for (i = 0; i < NUM_HINTS; i++) 2162 flush->hint_address[i] = t->flush_dma[4] 2163 + i * sizeof(u64); 2164 offset += flush->header.length; 2165 2166 /* sanity check to make sure we've filled the buffer */ 2167 WARN_ON(offset != t->nfit_size); 2168 } 2169 2170 t->nfit_filled = offset; 2171 2172 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0], 2173 SPA0_SIZE); 2174 2175 acpi_desc = &t->acpi_desc; 2176 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en); 2177 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2178 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2179 set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en); 2180 set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en); 2181 set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en); 2182 set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en); 2183 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en); 2184 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en); 2185 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en); 2186 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en); 2187 set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en); 2188 set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_nfit_cmd_force_en); 2189 set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_nfit_cmd_force_en); 2190 set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_nfit_cmd_force_en); 2191 set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_nfit_cmd_force_en); 2192 set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en); 2193 set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en); 2194 set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en); 2195 set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en); 2196 set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en); 2197 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en); 2198 } 2199 2200 static void nfit_test1_setup(struct nfit_test *t) 2201 { 2202 size_t offset; 2203 void *nfit_buf = t->nfit_buf; 2204 struct acpi_nfit_memory_map *memdev; 2205 struct acpi_nfit_control_region *dcr; 2206 struct acpi_nfit_system_address *spa; 2207 struct acpi_nfit_desc *acpi_desc; 2208 2209 offset = 0; 2210 /* spa0 (flat range with no bdw aliasing) */ 2211 spa = nfit_buf + offset; 2212 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2213 spa->header.length = sizeof(*spa); 2214 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 2215 spa->range_index = 0+1; 2216 spa->address = t->spa_set_dma[0]; 2217 spa->length = SPA2_SIZE; 2218 offset += spa->header.length; 2219 2220 /* virtual cd region */ 2221 spa = nfit_buf + offset; 2222 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2223 spa->header.length = sizeof(*spa); 2224 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16); 2225 spa->range_index = 0; 2226 spa->address = t->spa_set_dma[1]; 2227 spa->length = SPA_VCD_SIZE; 2228 offset += spa->header.length; 2229 2230 /* mem-region0 (spa0, dimm0) */ 2231 memdev = nfit_buf + offset; 2232 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2233 memdev->header.length = sizeof(*memdev); 2234 memdev->device_handle = handle[5]; 2235 memdev->physical_id = 0; 2236 memdev->region_id = 0; 2237 memdev->range_index = 0+1; 2238 memdev->region_index = 0+1; 2239 memdev->region_size = SPA2_SIZE; 2240 memdev->region_offset = 0; 2241 memdev->address = 0; 2242 memdev->interleave_index = 0; 2243 memdev->interleave_ways = 1; 2244 memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED 2245 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED 2246 | ACPI_NFIT_MEM_NOT_ARMED; 2247 offset += memdev->header.length; 2248 2249 /* dcr-descriptor0 */ 2250 dcr = nfit_buf + offset; 2251 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2252 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2253 window_size); 2254 dcr->region_index = 0+1; 2255 dcr_common_init(dcr); 2256 dcr->serial_number = ~handle[5]; 2257 dcr->code = NFIT_FIC_BYTE; 2258 dcr->windows = 0; 2259 offset += dcr->header.length; 2260 2261 memdev = nfit_buf + offset; 2262 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2263 memdev->header.length = sizeof(*memdev); 2264 memdev->device_handle = handle[6]; 2265 memdev->physical_id = 0; 2266 memdev->region_id = 0; 2267 memdev->range_index = 0; 2268 memdev->region_index = 0+2; 2269 memdev->region_size = SPA2_SIZE; 2270 memdev->region_offset = 0; 2271 memdev->address = 0; 2272 memdev->interleave_index = 0; 2273 memdev->interleave_ways = 1; 2274 memdev->flags = ACPI_NFIT_MEM_MAP_FAILED; 2275 offset += memdev->header.length; 2276 2277 /* dcr-descriptor1 */ 2278 dcr = nfit_buf + offset; 2279 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2280 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2281 window_size); 2282 dcr->region_index = 0+2; 2283 dcr_common_init(dcr); 2284 dcr->serial_number = ~handle[6]; 2285 dcr->code = NFIT_FIC_BYTE; 2286 dcr->windows = 0; 2287 offset += dcr->header.length; 2288 2289 /* sanity check to make sure we've filled the buffer */ 2290 WARN_ON(offset != t->nfit_size); 2291 2292 t->nfit_filled = offset; 2293 2294 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0], 2295 SPA2_SIZE); 2296 2297 acpi_desc = &t->acpi_desc; 2298 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en); 2299 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en); 2300 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en); 2301 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en); 2302 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en); 2303 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en); 2304 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2305 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2306 } 2307 2308 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa, 2309 void *iobuf, u64 len, int rw) 2310 { 2311 struct nfit_blk *nfit_blk = ndbr->blk_provider_data; 2312 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW]; 2313 struct nd_region *nd_region = &ndbr->nd_region; 2314 unsigned int lane; 2315 2316 lane = nd_region_acquire_lane(nd_region); 2317 if (rw) 2318 memcpy(mmio->addr.base + dpa, iobuf, len); 2319 else { 2320 memcpy(iobuf, mmio->addr.base + dpa, len); 2321 2322 /* give us some some coverage of the arch_invalidate_pmem() API */ 2323 arch_invalidate_pmem(mmio->addr.base + dpa, len); 2324 } 2325 nd_region_release_lane(nd_region, lane); 2326 2327 return 0; 2328 } 2329 2330 static unsigned long nfit_ctl_handle; 2331 2332 union acpi_object *result; 2333 2334 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle, 2335 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4) 2336 { 2337 if (handle != &nfit_ctl_handle) 2338 return ERR_PTR(-ENXIO); 2339 2340 return result; 2341 } 2342 2343 static int setup_result(void *buf, size_t size) 2344 { 2345 result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL); 2346 if (!result) 2347 return -ENOMEM; 2348 result->package.type = ACPI_TYPE_BUFFER, 2349 result->buffer.pointer = (void *) (result + 1); 2350 result->buffer.length = size; 2351 memcpy(result->buffer.pointer, buf, size); 2352 memset(buf, 0, size); 2353 return 0; 2354 } 2355 2356 static int nfit_ctl_test(struct device *dev) 2357 { 2358 int rc, cmd_rc; 2359 struct nvdimm *nvdimm; 2360 struct acpi_device *adev; 2361 struct nfit_mem *nfit_mem; 2362 struct nd_ars_record *record; 2363 struct acpi_nfit_desc *acpi_desc; 2364 const u64 test_val = 0x0123456789abcdefULL; 2365 unsigned long mask, cmd_size, offset; 2366 union { 2367 struct nd_cmd_get_config_size cfg_size; 2368 struct nd_cmd_clear_error clear_err; 2369 struct nd_cmd_ars_status ars_stat; 2370 struct nd_cmd_ars_cap ars_cap; 2371 char buf[sizeof(struct nd_cmd_ars_status) 2372 + sizeof(struct nd_ars_record)]; 2373 } cmds; 2374 2375 adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL); 2376 if (!adev) 2377 return -ENOMEM; 2378 *adev = (struct acpi_device) { 2379 .handle = &nfit_ctl_handle, 2380 .dev = { 2381 .init_name = "test-adev", 2382 }, 2383 }; 2384 2385 acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL); 2386 if (!acpi_desc) 2387 return -ENOMEM; 2388 *acpi_desc = (struct acpi_nfit_desc) { 2389 .nd_desc = { 2390 .cmd_mask = 1UL << ND_CMD_ARS_CAP 2391 | 1UL << ND_CMD_ARS_START 2392 | 1UL << ND_CMD_ARS_STATUS 2393 | 1UL << ND_CMD_CLEAR_ERROR 2394 | 1UL << ND_CMD_CALL, 2395 .module = THIS_MODULE, 2396 .provider_name = "ACPI.NFIT", 2397 .ndctl = acpi_nfit_ctl, 2398 .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA 2399 | 1UL << NFIT_CMD_ARS_INJECT_SET 2400 | 1UL << NFIT_CMD_ARS_INJECT_CLEAR 2401 | 1UL << NFIT_CMD_ARS_INJECT_GET, 2402 }, 2403 .dev = &adev->dev, 2404 }; 2405 2406 nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL); 2407 if (!nfit_mem) 2408 return -ENOMEM; 2409 2410 mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD 2411 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE 2412 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA 2413 | 1UL << ND_CMD_VENDOR; 2414 *nfit_mem = (struct nfit_mem) { 2415 .adev = adev, 2416 .family = NVDIMM_FAMILY_INTEL, 2417 .dsm_mask = mask, 2418 }; 2419 2420 nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL); 2421 if (!nvdimm) 2422 return -ENOMEM; 2423 *nvdimm = (struct nvdimm) { 2424 .provider_data = nfit_mem, 2425 .cmd_mask = mask, 2426 .dev = { 2427 .init_name = "test-dimm", 2428 }, 2429 }; 2430 2431 2432 /* basic checkout of a typical 'get config size' command */ 2433 cmd_size = sizeof(cmds.cfg_size); 2434 cmds.cfg_size = (struct nd_cmd_get_config_size) { 2435 .status = 0, 2436 .config_size = SZ_128K, 2437 .max_xfer = SZ_4K, 2438 }; 2439 rc = setup_result(cmds.buf, cmd_size); 2440 if (rc) 2441 return rc; 2442 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE, 2443 cmds.buf, cmd_size, &cmd_rc); 2444 2445 if (rc < 0 || cmd_rc || cmds.cfg_size.status != 0 2446 || cmds.cfg_size.config_size != SZ_128K 2447 || cmds.cfg_size.max_xfer != SZ_4K) { 2448 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2449 __func__, __LINE__, rc, cmd_rc); 2450 return -EIO; 2451 } 2452 2453 2454 /* test ars_status with zero output */ 2455 cmd_size = offsetof(struct nd_cmd_ars_status, address); 2456 cmds.ars_stat = (struct nd_cmd_ars_status) { 2457 .out_length = 0, 2458 }; 2459 rc = setup_result(cmds.buf, cmd_size); 2460 if (rc) 2461 return rc; 2462 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2463 cmds.buf, cmd_size, &cmd_rc); 2464 2465 if (rc < 0 || cmd_rc) { 2466 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2467 __func__, __LINE__, rc, cmd_rc); 2468 return -EIO; 2469 } 2470 2471 2472 /* test ars_cap with benign extended status */ 2473 cmd_size = sizeof(cmds.ars_cap); 2474 cmds.ars_cap = (struct nd_cmd_ars_cap) { 2475 .status = ND_ARS_PERSISTENT << 16, 2476 }; 2477 offset = offsetof(struct nd_cmd_ars_cap, status); 2478 rc = setup_result(cmds.buf + offset, cmd_size - offset); 2479 if (rc) 2480 return rc; 2481 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP, 2482 cmds.buf, cmd_size, &cmd_rc); 2483 2484 if (rc < 0 || cmd_rc) { 2485 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2486 __func__, __LINE__, rc, cmd_rc); 2487 return -EIO; 2488 } 2489 2490 2491 /* test ars_status with 'status' trimmed from 'out_length' */ 2492 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record); 2493 cmds.ars_stat = (struct nd_cmd_ars_status) { 2494 .out_length = cmd_size - 4, 2495 }; 2496 record = &cmds.ars_stat.records[0]; 2497 *record = (struct nd_ars_record) { 2498 .length = test_val, 2499 }; 2500 rc = setup_result(cmds.buf, cmd_size); 2501 if (rc) 2502 return rc; 2503 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2504 cmds.buf, cmd_size, &cmd_rc); 2505 2506 if (rc < 0 || cmd_rc || record->length != test_val) { 2507 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2508 __func__, __LINE__, rc, cmd_rc); 2509 return -EIO; 2510 } 2511 2512 2513 /* test ars_status with 'Output (Size)' including 'status' */ 2514 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record); 2515 cmds.ars_stat = (struct nd_cmd_ars_status) { 2516 .out_length = cmd_size, 2517 }; 2518 record = &cmds.ars_stat.records[0]; 2519 *record = (struct nd_ars_record) { 2520 .length = test_val, 2521 }; 2522 rc = setup_result(cmds.buf, cmd_size); 2523 if (rc) 2524 return rc; 2525 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2526 cmds.buf, cmd_size, &cmd_rc); 2527 2528 if (rc < 0 || cmd_rc || record->length != test_val) { 2529 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2530 __func__, __LINE__, rc, cmd_rc); 2531 return -EIO; 2532 } 2533 2534 2535 /* test extended status for get_config_size results in failure */ 2536 cmd_size = sizeof(cmds.cfg_size); 2537 cmds.cfg_size = (struct nd_cmd_get_config_size) { 2538 .status = 1 << 16, 2539 }; 2540 rc = setup_result(cmds.buf, cmd_size); 2541 if (rc) 2542 return rc; 2543 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE, 2544 cmds.buf, cmd_size, &cmd_rc); 2545 2546 if (rc < 0 || cmd_rc >= 0) { 2547 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2548 __func__, __LINE__, rc, cmd_rc); 2549 return -EIO; 2550 } 2551 2552 /* test clear error */ 2553 cmd_size = sizeof(cmds.clear_err); 2554 cmds.clear_err = (struct nd_cmd_clear_error) { 2555 .length = 512, 2556 .cleared = 512, 2557 }; 2558 rc = setup_result(cmds.buf, cmd_size); 2559 if (rc) 2560 return rc; 2561 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR, 2562 cmds.buf, cmd_size, &cmd_rc); 2563 if (rc < 0 || cmd_rc) { 2564 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2565 __func__, __LINE__, rc, cmd_rc); 2566 return -EIO; 2567 } 2568 2569 return 0; 2570 } 2571 2572 static int nfit_test_probe(struct platform_device *pdev) 2573 { 2574 struct nvdimm_bus_descriptor *nd_desc; 2575 struct acpi_nfit_desc *acpi_desc; 2576 struct device *dev = &pdev->dev; 2577 struct nfit_test *nfit_test; 2578 struct nfit_mem *nfit_mem; 2579 union acpi_object *obj; 2580 int rc; 2581 2582 if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) { 2583 rc = nfit_ctl_test(&pdev->dev); 2584 if (rc) 2585 return rc; 2586 } 2587 2588 nfit_test = to_nfit_test(&pdev->dev); 2589 2590 /* common alloc */ 2591 if (nfit_test->num_dcr) { 2592 int num = nfit_test->num_dcr; 2593 2594 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *), 2595 GFP_KERNEL); 2596 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t), 2597 GFP_KERNEL); 2598 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *), 2599 GFP_KERNEL); 2600 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t), 2601 GFP_KERNEL); 2602 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *), 2603 GFP_KERNEL); 2604 nfit_test->label_dma = devm_kcalloc(dev, num, 2605 sizeof(dma_addr_t), GFP_KERNEL); 2606 nfit_test->dcr = devm_kcalloc(dev, num, 2607 sizeof(struct nfit_test_dcr *), GFP_KERNEL); 2608 nfit_test->dcr_dma = devm_kcalloc(dev, num, 2609 sizeof(dma_addr_t), GFP_KERNEL); 2610 nfit_test->smart = devm_kcalloc(dev, num, 2611 sizeof(struct nd_intel_smart), GFP_KERNEL); 2612 nfit_test->smart_threshold = devm_kcalloc(dev, num, 2613 sizeof(struct nd_intel_smart_threshold), 2614 GFP_KERNEL); 2615 nfit_test->fw = devm_kcalloc(dev, num, 2616 sizeof(struct nfit_test_fw), GFP_KERNEL); 2617 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label 2618 && nfit_test->label_dma && nfit_test->dcr 2619 && nfit_test->dcr_dma && nfit_test->flush 2620 && nfit_test->flush_dma 2621 && nfit_test->fw) 2622 /* pass */; 2623 else 2624 return -ENOMEM; 2625 } 2626 2627 if (nfit_test->num_pm) { 2628 int num = nfit_test->num_pm; 2629 2630 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *), 2631 GFP_KERNEL); 2632 nfit_test->spa_set_dma = devm_kcalloc(dev, num, 2633 sizeof(dma_addr_t), GFP_KERNEL); 2634 if (nfit_test->spa_set && nfit_test->spa_set_dma) 2635 /* pass */; 2636 else 2637 return -ENOMEM; 2638 } 2639 2640 /* per-nfit specific alloc */ 2641 if (nfit_test->alloc(nfit_test)) 2642 return -ENOMEM; 2643 2644 nfit_test->setup(nfit_test); 2645 acpi_desc = &nfit_test->acpi_desc; 2646 acpi_nfit_desc_init(acpi_desc, &pdev->dev); 2647 acpi_desc->blk_do_io = nfit_test_blk_do_io; 2648 nd_desc = &acpi_desc->nd_desc; 2649 nd_desc->provider_name = NULL; 2650 nd_desc->module = THIS_MODULE; 2651 nd_desc->ndctl = nfit_test_ctl; 2652 2653 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf, 2654 nfit_test->nfit_filled); 2655 if (rc) 2656 return rc; 2657 2658 rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc); 2659 if (rc) 2660 return rc; 2661 2662 if (nfit_test->setup != nfit_test0_setup) 2663 return 0; 2664 2665 nfit_test->setup_hotplug = 1; 2666 nfit_test->setup(nfit_test); 2667 2668 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 2669 if (!obj) 2670 return -ENOMEM; 2671 obj->type = ACPI_TYPE_BUFFER; 2672 obj->buffer.length = nfit_test->nfit_size; 2673 obj->buffer.pointer = nfit_test->nfit_buf; 2674 *(nfit_test->_fit) = obj; 2675 __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80); 2676 2677 /* associate dimm devices with nfit_mem data for notification testing */ 2678 mutex_lock(&acpi_desc->init_mutex); 2679 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) { 2680 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle; 2681 int i; 2682 2683 for (i = 0; i < NUM_DCR; i++) 2684 if (nfit_handle == handle[i]) 2685 dev_set_drvdata(nfit_test->dimm_dev[i], 2686 nfit_mem); 2687 } 2688 mutex_unlock(&acpi_desc->init_mutex); 2689 2690 return 0; 2691 } 2692 2693 static int nfit_test_remove(struct platform_device *pdev) 2694 { 2695 return 0; 2696 } 2697 2698 static void nfit_test_release(struct device *dev) 2699 { 2700 struct nfit_test *nfit_test = to_nfit_test(dev); 2701 2702 kfree(nfit_test); 2703 } 2704 2705 static const struct platform_device_id nfit_test_id[] = { 2706 { KBUILD_MODNAME }, 2707 { }, 2708 }; 2709 2710 static struct platform_driver nfit_test_driver = { 2711 .probe = nfit_test_probe, 2712 .remove = nfit_test_remove, 2713 .driver = { 2714 .name = KBUILD_MODNAME, 2715 }, 2716 .id_table = nfit_test_id, 2717 }; 2718 2719 static char mcsafe_buf[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE))); 2720 2721 enum INJECT { 2722 INJECT_NONE, 2723 INJECT_SRC, 2724 INJECT_DST, 2725 }; 2726 2727 static void mcsafe_test_init(char *dst, char *src, size_t size) 2728 { 2729 size_t i; 2730 2731 memset(dst, 0xff, size); 2732 for (i = 0; i < size; i++) 2733 src[i] = (char) i; 2734 } 2735 2736 static bool mcsafe_test_validate(unsigned char *dst, unsigned char *src, 2737 size_t size, unsigned long rem) 2738 { 2739 size_t i; 2740 2741 for (i = 0; i < size - rem; i++) 2742 if (dst[i] != (unsigned char) i) { 2743 pr_info_once("%s:%d: offset: %zd got: %#x expect: %#x\n", 2744 __func__, __LINE__, i, dst[i], 2745 (unsigned char) i); 2746 return false; 2747 } 2748 for (i = size - rem; i < size; i++) 2749 if (dst[i] != 0xffU) { 2750 pr_info_once("%s:%d: offset: %zd got: %#x expect: 0xff\n", 2751 __func__, __LINE__, i, dst[i]); 2752 return false; 2753 } 2754 return true; 2755 } 2756 2757 void mcsafe_test(void) 2758 { 2759 char *inject_desc[] = { "none", "source", "destination" }; 2760 enum INJECT inj; 2761 2762 if (IS_ENABLED(CONFIG_MCSAFE_TEST)) { 2763 pr_info("%s: run...\n", __func__); 2764 } else { 2765 pr_info("%s: disabled, skip.\n", __func__); 2766 return; 2767 } 2768 2769 for (inj = INJECT_NONE; inj <= INJECT_DST; inj++) { 2770 int i; 2771 2772 pr_info("%s: inject: %s\n", __func__, inject_desc[inj]); 2773 for (i = 0; i < 512; i++) { 2774 unsigned long expect, rem; 2775 void *src, *dst; 2776 bool valid; 2777 2778 switch (inj) { 2779 case INJECT_NONE: 2780 mcsafe_inject_src(NULL); 2781 mcsafe_inject_dst(NULL); 2782 dst = &mcsafe_buf[2048]; 2783 src = &mcsafe_buf[1024 - i]; 2784 expect = 0; 2785 break; 2786 case INJECT_SRC: 2787 mcsafe_inject_src(&mcsafe_buf[1024]); 2788 mcsafe_inject_dst(NULL); 2789 dst = &mcsafe_buf[2048]; 2790 src = &mcsafe_buf[1024 - i]; 2791 expect = 512 - i; 2792 break; 2793 case INJECT_DST: 2794 mcsafe_inject_src(NULL); 2795 mcsafe_inject_dst(&mcsafe_buf[2048]); 2796 dst = &mcsafe_buf[2048 - i]; 2797 src = &mcsafe_buf[1024]; 2798 expect = 512 - i; 2799 break; 2800 } 2801 2802 mcsafe_test_init(dst, src, 512); 2803 rem = __memcpy_mcsafe(dst, src, 512); 2804 valid = mcsafe_test_validate(dst, src, 512, expect); 2805 if (rem == expect && valid) 2806 continue; 2807 pr_info("%s: copy(%#lx, %#lx, %d) off: %d rem: %ld %s expect: %ld\n", 2808 __func__, 2809 ((unsigned long) dst) & ~PAGE_MASK, 2810 ((unsigned long ) src) & ~PAGE_MASK, 2811 512, i, rem, valid ? "valid" : "bad", 2812 expect); 2813 } 2814 } 2815 2816 mcsafe_inject_src(NULL); 2817 mcsafe_inject_dst(NULL); 2818 } 2819 2820 static __init int nfit_test_init(void) 2821 { 2822 int rc, i; 2823 2824 pmem_test(); 2825 libnvdimm_test(); 2826 acpi_nfit_test(); 2827 device_dax_test(); 2828 mcsafe_test(); 2829 2830 nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm); 2831 2832 nfit_wq = create_singlethread_workqueue("nfit"); 2833 if (!nfit_wq) 2834 return -ENOMEM; 2835 2836 nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm"); 2837 if (IS_ERR(nfit_test_dimm)) { 2838 rc = PTR_ERR(nfit_test_dimm); 2839 goto err_register; 2840 } 2841 2842 for (i = 0; i < NUM_NFITS; i++) { 2843 struct nfit_test *nfit_test; 2844 struct platform_device *pdev; 2845 2846 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL); 2847 if (!nfit_test) { 2848 rc = -ENOMEM; 2849 goto err_register; 2850 } 2851 INIT_LIST_HEAD(&nfit_test->resources); 2852 badrange_init(&nfit_test->badrange); 2853 switch (i) { 2854 case 0: 2855 nfit_test->num_pm = NUM_PM; 2856 nfit_test->dcr_idx = 0; 2857 nfit_test->num_dcr = NUM_DCR; 2858 nfit_test->alloc = nfit_test0_alloc; 2859 nfit_test->setup = nfit_test0_setup; 2860 break; 2861 case 1: 2862 nfit_test->num_pm = 2; 2863 nfit_test->dcr_idx = NUM_DCR; 2864 nfit_test->num_dcr = 2; 2865 nfit_test->alloc = nfit_test1_alloc; 2866 nfit_test->setup = nfit_test1_setup; 2867 break; 2868 default: 2869 rc = -EINVAL; 2870 goto err_register; 2871 } 2872 pdev = &nfit_test->pdev; 2873 pdev->name = KBUILD_MODNAME; 2874 pdev->id = i; 2875 pdev->dev.release = nfit_test_release; 2876 rc = platform_device_register(pdev); 2877 if (rc) { 2878 put_device(&pdev->dev); 2879 goto err_register; 2880 } 2881 get_device(&pdev->dev); 2882 2883 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2884 if (rc) 2885 goto err_register; 2886 2887 instances[i] = nfit_test; 2888 INIT_WORK(&nfit_test->work, uc_error_notify); 2889 } 2890 2891 rc = platform_driver_register(&nfit_test_driver); 2892 if (rc) 2893 goto err_register; 2894 return 0; 2895 2896 err_register: 2897 destroy_workqueue(nfit_wq); 2898 for (i = 0; i < NUM_NFITS; i++) 2899 if (instances[i]) 2900 platform_device_unregister(&instances[i]->pdev); 2901 nfit_test_teardown(); 2902 for (i = 0; i < NUM_NFITS; i++) 2903 if (instances[i]) 2904 put_device(&instances[i]->pdev.dev); 2905 2906 return rc; 2907 } 2908 2909 static __exit void nfit_test_exit(void) 2910 { 2911 int i; 2912 2913 flush_workqueue(nfit_wq); 2914 destroy_workqueue(nfit_wq); 2915 for (i = 0; i < NUM_NFITS; i++) 2916 platform_device_unregister(&instances[i]->pdev); 2917 platform_driver_unregister(&nfit_test_driver); 2918 nfit_test_teardown(); 2919 2920 for (i = 0; i < NUM_NFITS; i++) 2921 put_device(&instances[i]->pdev.dev); 2922 class_destroy(nfit_test_dimm); 2923 } 2924 2925 module_init(nfit_test_init); 2926 module_exit(nfit_test_exit); 2927 MODULE_LICENSE("GPL v2"); 2928 MODULE_AUTHOR("Intel Corporation"); 2929