1 /* 2 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License for more details. 12 */ 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/workqueue.h> 17 #include <linux/libnvdimm.h> 18 #include <linux/genalloc.h> 19 #include <linux/vmalloc.h> 20 #include <linux/device.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/ndctl.h> 24 #include <linux/sizes.h> 25 #include <linux/list.h> 26 #include <linux/slab.h> 27 #include <nd-core.h> 28 #include <intel.h> 29 #include <nfit.h> 30 #include <nd.h> 31 #include "nfit_test.h" 32 #include "../watermark.h" 33 34 #include <asm/mcsafe_test.h> 35 36 /* 37 * Generate an NFIT table to describe the following topology: 38 * 39 * BUS0: Interleaved PMEM regions, and aliasing with BLK regions 40 * 41 * (a) (b) DIMM BLK-REGION 42 * +----------+--------------+----------+---------+ 43 * +------+ | blk2.0 | pm0.0 | blk2.1 | pm1.0 | 0 region2 44 * | imc0 +--+- - - - - region0 - - - -+----------+ + 45 * +--+---+ | blk3.0 | pm0.0 | blk3.1 | pm1.0 | 1 region3 46 * | +----------+--------------v----------v v 47 * +--+---+ | | 48 * | cpu0 | region1 49 * +--+---+ | | 50 * | +-------------------------^----------^ ^ 51 * +--+---+ | blk4.0 | pm1.0 | 2 region4 52 * | imc1 +--+-------------------------+----------+ + 53 * +------+ | blk5.0 | pm1.0 | 3 region5 54 * +-------------------------+----------+-+-------+ 55 * 56 * +--+---+ 57 * | cpu1 | 58 * +--+---+ (Hotplug DIMM) 59 * | +----------------------------------------------+ 60 * +--+---+ | blk6.0/pm7.0 | 4 region6/7 61 * | imc0 +--+----------------------------------------------+ 62 * +------+ 63 * 64 * 65 * *) In this layout we have four dimms and two memory controllers in one 66 * socket. Each unique interface (BLK or PMEM) to DPA space 67 * is identified by a region device with a dynamically assigned id. 68 * 69 * *) The first portion of dimm0 and dimm1 are interleaved as REGION0. 70 * A single PMEM namespace "pm0.0" is created using half of the 71 * REGION0 SPA-range. REGION0 spans dimm0 and dimm1. PMEM namespace 72 * allocate from from the bottom of a region. The unallocated 73 * portion of REGION0 aliases with REGION2 and REGION3. That 74 * unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and 75 * "blk3.0") starting at the base of each DIMM to offset (a) in those 76 * DIMMs. "pm0.0", "blk2.0" and "blk3.0" are free-form readable 77 * names that can be assigned to a namespace. 78 * 79 * *) In the last portion of dimm0 and dimm1 we have an interleaved 80 * SPA range, REGION1, that spans those two dimms as well as dimm2 81 * and dimm3. Some of REGION1 allocated to a PMEM namespace named 82 * "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each 83 * dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and 84 * "blk5.0". 85 * 86 * *) The portion of dimm2 and dimm3 that do not participate in the 87 * REGION1 interleaved SPA range (i.e. the DPA address below offset 88 * (b) are also included in the "blk4.0" and "blk5.0" namespaces. 89 * Note, that BLK namespaces need not be contiguous in DPA-space, and 90 * can consume aliased capacity from multiple interleave sets. 91 * 92 * BUS1: Legacy NVDIMM (single contiguous range) 93 * 94 * region2 95 * +---------------------+ 96 * |---------------------| 97 * || pm2.0 || 98 * |---------------------| 99 * +---------------------+ 100 * 101 * *) A NFIT-table may describe a simple system-physical-address range 102 * with no BLK aliasing. This type of region may optionally 103 * reference an NVDIMM. 104 */ 105 enum { 106 NUM_PM = 3, 107 NUM_DCR = 5, 108 NUM_HINTS = 8, 109 NUM_BDW = NUM_DCR, 110 NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW, 111 NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */ 112 + 4 /* spa1 iset */ + 1 /* spa11 iset */, 113 DIMM_SIZE = SZ_32M, 114 LABEL_SIZE = SZ_128K, 115 SPA_VCD_SIZE = SZ_4M, 116 SPA0_SIZE = DIMM_SIZE, 117 SPA1_SIZE = DIMM_SIZE*2, 118 SPA2_SIZE = DIMM_SIZE, 119 BDW_SIZE = 64 << 8, 120 DCR_SIZE = 12, 121 NUM_NFITS = 2, /* permit testing multiple NFITs per system */ 122 }; 123 124 struct nfit_test_dcr { 125 __le64 bdw_addr; 126 __le32 bdw_status; 127 __u8 aperature[BDW_SIZE]; 128 }; 129 130 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \ 131 (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \ 132 | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf)) 133 134 static u32 handle[] = { 135 [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0), 136 [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1), 137 [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0), 138 [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1), 139 [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0), 140 [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0), 141 [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1), 142 }; 143 144 static unsigned long dimm_fail_cmd_flags[ARRAY_SIZE(handle)]; 145 static int dimm_fail_cmd_code[ARRAY_SIZE(handle)]; 146 struct nfit_test_sec { 147 u8 state; 148 u8 ext_state; 149 u8 passphrase[32]; 150 u8 master_passphrase[32]; 151 u64 overwrite_end_time; 152 } dimm_sec_info[NUM_DCR]; 153 154 static const struct nd_intel_smart smart_def = { 155 .flags = ND_INTEL_SMART_HEALTH_VALID 156 | ND_INTEL_SMART_SPARES_VALID 157 | ND_INTEL_SMART_ALARM_VALID 158 | ND_INTEL_SMART_USED_VALID 159 | ND_INTEL_SMART_SHUTDOWN_VALID 160 | ND_INTEL_SMART_SHUTDOWN_COUNT_VALID 161 | ND_INTEL_SMART_MTEMP_VALID 162 | ND_INTEL_SMART_CTEMP_VALID, 163 .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH, 164 .media_temperature = 23 * 16, 165 .ctrl_temperature = 25 * 16, 166 .pmic_temperature = 40 * 16, 167 .spares = 75, 168 .alarm_flags = ND_INTEL_SMART_SPARE_TRIP 169 | ND_INTEL_SMART_TEMP_TRIP, 170 .ait_status = 1, 171 .life_used = 5, 172 .shutdown_state = 0, 173 .shutdown_count = 42, 174 .vendor_size = 0, 175 }; 176 177 struct nfit_test_fw { 178 enum intel_fw_update_state state; 179 u32 context; 180 u64 version; 181 u32 size_received; 182 u64 end_time; 183 }; 184 185 struct nfit_test { 186 struct acpi_nfit_desc acpi_desc; 187 struct platform_device pdev; 188 struct list_head resources; 189 void *nfit_buf; 190 dma_addr_t nfit_dma; 191 size_t nfit_size; 192 size_t nfit_filled; 193 int dcr_idx; 194 int num_dcr; 195 int num_pm; 196 void **dimm; 197 dma_addr_t *dimm_dma; 198 void **flush; 199 dma_addr_t *flush_dma; 200 void **label; 201 dma_addr_t *label_dma; 202 void **spa_set; 203 dma_addr_t *spa_set_dma; 204 struct nfit_test_dcr **dcr; 205 dma_addr_t *dcr_dma; 206 int (*alloc)(struct nfit_test *t); 207 void (*setup)(struct nfit_test *t); 208 int setup_hotplug; 209 union acpi_object **_fit; 210 dma_addr_t _fit_dma; 211 struct ars_state { 212 struct nd_cmd_ars_status *ars_status; 213 unsigned long deadline; 214 spinlock_t lock; 215 } ars_state; 216 struct device *dimm_dev[ARRAY_SIZE(handle)]; 217 struct nd_intel_smart *smart; 218 struct nd_intel_smart_threshold *smart_threshold; 219 struct badrange badrange; 220 struct work_struct work; 221 struct nfit_test_fw *fw; 222 }; 223 224 static struct workqueue_struct *nfit_wq; 225 226 static struct gen_pool *nfit_pool; 227 228 static struct nfit_test *to_nfit_test(struct device *dev) 229 { 230 struct platform_device *pdev = to_platform_device(dev); 231 232 return container_of(pdev, struct nfit_test, pdev); 233 } 234 235 static int nd_intel_test_get_fw_info(struct nfit_test *t, 236 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len, 237 int idx) 238 { 239 struct device *dev = &t->pdev.dev; 240 struct nfit_test_fw *fw = &t->fw[idx]; 241 242 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n", 243 __func__, t, nd_cmd, buf_len, idx); 244 245 if (buf_len < sizeof(*nd_cmd)) 246 return -EINVAL; 247 248 nd_cmd->status = 0; 249 nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE; 250 nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN; 251 nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL; 252 nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME; 253 nd_cmd->update_cap = 0; 254 nd_cmd->fis_version = INTEL_FW_FIS_VERSION; 255 nd_cmd->run_version = 0; 256 nd_cmd->updated_version = fw->version; 257 258 return 0; 259 } 260 261 static int nd_intel_test_start_update(struct nfit_test *t, 262 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len, 263 int idx) 264 { 265 struct device *dev = &t->pdev.dev; 266 struct nfit_test_fw *fw = &t->fw[idx]; 267 268 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 269 __func__, t, nd_cmd, buf_len, idx); 270 271 if (buf_len < sizeof(*nd_cmd)) 272 return -EINVAL; 273 274 if (fw->state != FW_STATE_NEW) { 275 /* extended status, FW update in progress */ 276 nd_cmd->status = 0x10007; 277 return 0; 278 } 279 280 fw->state = FW_STATE_IN_PROGRESS; 281 fw->context++; 282 fw->size_received = 0; 283 nd_cmd->status = 0; 284 nd_cmd->context = fw->context; 285 286 dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context); 287 288 return 0; 289 } 290 291 static int nd_intel_test_send_data(struct nfit_test *t, 292 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len, 293 int idx) 294 { 295 struct device *dev = &t->pdev.dev; 296 struct nfit_test_fw *fw = &t->fw[idx]; 297 u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length]; 298 299 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 300 __func__, t, nd_cmd, buf_len, idx); 301 302 if (buf_len < sizeof(*nd_cmd)) 303 return -EINVAL; 304 305 306 dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status); 307 dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]); 308 dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1, 309 nd_cmd->data[nd_cmd->length-1]); 310 311 if (fw->state != FW_STATE_IN_PROGRESS) { 312 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__); 313 *status = 0x5; 314 return 0; 315 } 316 317 if (nd_cmd->context != fw->context) { 318 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 319 __func__, nd_cmd->context, fw->context); 320 *status = 0x10007; 321 return 0; 322 } 323 324 /* 325 * check offset + len > size of fw storage 326 * check length is > max send length 327 */ 328 if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE || 329 nd_cmd->length > INTEL_FW_MAX_SEND_LEN) { 330 *status = 0x3; 331 dev_dbg(dev, "%s: buffer boundary violation\n", __func__); 332 return 0; 333 } 334 335 fw->size_received += nd_cmd->length; 336 dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n", 337 __func__, nd_cmd->length, fw->size_received); 338 *status = 0; 339 return 0; 340 } 341 342 static int nd_intel_test_finish_fw(struct nfit_test *t, 343 struct nd_intel_fw_finish_update *nd_cmd, 344 unsigned int buf_len, int idx) 345 { 346 struct device *dev = &t->pdev.dev; 347 struct nfit_test_fw *fw = &t->fw[idx]; 348 349 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 350 __func__, t, nd_cmd, buf_len, idx); 351 352 if (fw->state == FW_STATE_UPDATED) { 353 /* update already done, need cold boot */ 354 nd_cmd->status = 0x20007; 355 return 0; 356 } 357 358 dev_dbg(dev, "%s: context: %#x ctrl_flags: %#x\n", 359 __func__, nd_cmd->context, nd_cmd->ctrl_flags); 360 361 switch (nd_cmd->ctrl_flags) { 362 case 0: /* finish */ 363 if (nd_cmd->context != fw->context) { 364 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 365 __func__, nd_cmd->context, 366 fw->context); 367 nd_cmd->status = 0x10007; 368 return 0; 369 } 370 nd_cmd->status = 0; 371 fw->state = FW_STATE_VERIFY; 372 /* set 1 second of time for firmware "update" */ 373 fw->end_time = jiffies + HZ; 374 break; 375 376 case 1: /* abort */ 377 fw->size_received = 0; 378 /* successfully aborted status */ 379 nd_cmd->status = 0x40007; 380 fw->state = FW_STATE_NEW; 381 dev_dbg(dev, "%s: abort successful\n", __func__); 382 break; 383 384 default: /* bad control flag */ 385 dev_warn(dev, "%s: unknown control flag: %#x\n", 386 __func__, nd_cmd->ctrl_flags); 387 return -EINVAL; 388 } 389 390 return 0; 391 } 392 393 static int nd_intel_test_finish_query(struct nfit_test *t, 394 struct nd_intel_fw_finish_query *nd_cmd, 395 unsigned int buf_len, int idx) 396 { 397 struct device *dev = &t->pdev.dev; 398 struct nfit_test_fw *fw = &t->fw[idx]; 399 400 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 401 __func__, t, nd_cmd, buf_len, idx); 402 403 if (buf_len < sizeof(*nd_cmd)) 404 return -EINVAL; 405 406 if (nd_cmd->context != fw->context) { 407 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 408 __func__, nd_cmd->context, fw->context); 409 nd_cmd->status = 0x10007; 410 return 0; 411 } 412 413 dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context); 414 415 switch (fw->state) { 416 case FW_STATE_NEW: 417 nd_cmd->updated_fw_rev = 0; 418 nd_cmd->status = 0; 419 dev_dbg(dev, "%s: new state\n", __func__); 420 break; 421 422 case FW_STATE_IN_PROGRESS: 423 /* sequencing error */ 424 nd_cmd->status = 0x40007; 425 nd_cmd->updated_fw_rev = 0; 426 dev_dbg(dev, "%s: sequence error\n", __func__); 427 break; 428 429 case FW_STATE_VERIFY: 430 if (time_is_after_jiffies64(fw->end_time)) { 431 nd_cmd->updated_fw_rev = 0; 432 nd_cmd->status = 0x20007; 433 dev_dbg(dev, "%s: still verifying\n", __func__); 434 break; 435 } 436 437 dev_dbg(dev, "%s: transition out verify\n", __func__); 438 fw->state = FW_STATE_UPDATED; 439 /* we are going to fall through if it's "done" */ 440 case FW_STATE_UPDATED: 441 nd_cmd->status = 0; 442 /* bogus test version */ 443 fw->version = nd_cmd->updated_fw_rev = 444 INTEL_FW_FAKE_VERSION; 445 dev_dbg(dev, "%s: updated\n", __func__); 446 break; 447 448 default: /* we should never get here */ 449 return -EINVAL; 450 } 451 452 return 0; 453 } 454 455 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd, 456 unsigned int buf_len) 457 { 458 if (buf_len < sizeof(*nd_cmd)) 459 return -EINVAL; 460 461 nd_cmd->status = 0; 462 nd_cmd->config_size = LABEL_SIZE; 463 nd_cmd->max_xfer = SZ_4K; 464 465 return 0; 466 } 467 468 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr 469 *nd_cmd, unsigned int buf_len, void *label) 470 { 471 unsigned int len, offset = nd_cmd->in_offset; 472 int rc; 473 474 if (buf_len < sizeof(*nd_cmd)) 475 return -EINVAL; 476 if (offset >= LABEL_SIZE) 477 return -EINVAL; 478 if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len) 479 return -EINVAL; 480 481 nd_cmd->status = 0; 482 len = min(nd_cmd->in_length, LABEL_SIZE - offset); 483 memcpy(nd_cmd->out_buf, label + offset, len); 484 rc = buf_len - sizeof(*nd_cmd) - len; 485 486 return rc; 487 } 488 489 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd, 490 unsigned int buf_len, void *label) 491 { 492 unsigned int len, offset = nd_cmd->in_offset; 493 u32 *status; 494 int rc; 495 496 if (buf_len < sizeof(*nd_cmd)) 497 return -EINVAL; 498 if (offset >= LABEL_SIZE) 499 return -EINVAL; 500 if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len) 501 return -EINVAL; 502 503 status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd); 504 *status = 0; 505 len = min(nd_cmd->in_length, LABEL_SIZE - offset); 506 memcpy(label + offset, nd_cmd->in_buf, len); 507 rc = buf_len - sizeof(*nd_cmd) - (len + 4); 508 509 return rc; 510 } 511 512 #define NFIT_TEST_CLEAR_ERR_UNIT 256 513 514 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd, 515 unsigned int buf_len) 516 { 517 int ars_recs; 518 519 if (buf_len < sizeof(*nd_cmd)) 520 return -EINVAL; 521 522 /* for testing, only store up to n records that fit within 4k */ 523 ars_recs = SZ_4K / sizeof(struct nd_ars_record); 524 525 nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status) 526 + ars_recs * sizeof(struct nd_ars_record); 527 nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16; 528 nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT; 529 530 return 0; 531 } 532 533 static void post_ars_status(struct ars_state *ars_state, 534 struct badrange *badrange, u64 addr, u64 len) 535 { 536 struct nd_cmd_ars_status *ars_status; 537 struct nd_ars_record *ars_record; 538 struct badrange_entry *be; 539 u64 end = addr + len - 1; 540 int i = 0; 541 542 ars_state->deadline = jiffies + 1*HZ; 543 ars_status = ars_state->ars_status; 544 ars_status->status = 0; 545 ars_status->address = addr; 546 ars_status->length = len; 547 ars_status->type = ND_ARS_PERSISTENT; 548 549 spin_lock(&badrange->lock); 550 list_for_each_entry(be, &badrange->list, list) { 551 u64 be_end = be->start + be->length - 1; 552 u64 rstart, rend; 553 554 /* skip entries outside the range */ 555 if (be_end < addr || be->start > end) 556 continue; 557 558 rstart = (be->start < addr) ? addr : be->start; 559 rend = (be_end < end) ? be_end : end; 560 ars_record = &ars_status->records[i]; 561 ars_record->handle = 0; 562 ars_record->err_address = rstart; 563 ars_record->length = rend - rstart + 1; 564 i++; 565 } 566 spin_unlock(&badrange->lock); 567 ars_status->num_records = i; 568 ars_status->out_length = sizeof(struct nd_cmd_ars_status) 569 + i * sizeof(struct nd_ars_record); 570 } 571 572 static int nfit_test_cmd_ars_start(struct nfit_test *t, 573 struct ars_state *ars_state, 574 struct nd_cmd_ars_start *ars_start, unsigned int buf_len, 575 int *cmd_rc) 576 { 577 if (buf_len < sizeof(*ars_start)) 578 return -EINVAL; 579 580 spin_lock(&ars_state->lock); 581 if (time_before(jiffies, ars_state->deadline)) { 582 ars_start->status = NFIT_ARS_START_BUSY; 583 *cmd_rc = -EBUSY; 584 } else { 585 ars_start->status = 0; 586 ars_start->scrub_time = 1; 587 post_ars_status(ars_state, &t->badrange, ars_start->address, 588 ars_start->length); 589 *cmd_rc = 0; 590 } 591 spin_unlock(&ars_state->lock); 592 593 return 0; 594 } 595 596 static int nfit_test_cmd_ars_status(struct ars_state *ars_state, 597 struct nd_cmd_ars_status *ars_status, unsigned int buf_len, 598 int *cmd_rc) 599 { 600 if (buf_len < ars_state->ars_status->out_length) 601 return -EINVAL; 602 603 spin_lock(&ars_state->lock); 604 if (time_before(jiffies, ars_state->deadline)) { 605 memset(ars_status, 0, buf_len); 606 ars_status->status = NFIT_ARS_STATUS_BUSY; 607 ars_status->out_length = sizeof(*ars_status); 608 *cmd_rc = -EBUSY; 609 } else { 610 memcpy(ars_status, ars_state->ars_status, 611 ars_state->ars_status->out_length); 612 *cmd_rc = 0; 613 } 614 spin_unlock(&ars_state->lock); 615 return 0; 616 } 617 618 static int nfit_test_cmd_clear_error(struct nfit_test *t, 619 struct nd_cmd_clear_error *clear_err, 620 unsigned int buf_len, int *cmd_rc) 621 { 622 const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1; 623 if (buf_len < sizeof(*clear_err)) 624 return -EINVAL; 625 626 if ((clear_err->address & mask) || (clear_err->length & mask)) 627 return -EINVAL; 628 629 badrange_forget(&t->badrange, clear_err->address, clear_err->length); 630 clear_err->status = 0; 631 clear_err->cleared = clear_err->length; 632 *cmd_rc = 0; 633 return 0; 634 } 635 636 struct region_search_spa { 637 u64 addr; 638 struct nd_region *region; 639 }; 640 641 static int is_region_device(struct device *dev) 642 { 643 return !strncmp(dev->kobj.name, "region", 6); 644 } 645 646 static int nfit_test_search_region_spa(struct device *dev, void *data) 647 { 648 struct region_search_spa *ctx = data; 649 struct nd_region *nd_region; 650 resource_size_t ndr_end; 651 652 if (!is_region_device(dev)) 653 return 0; 654 655 nd_region = to_nd_region(dev); 656 ndr_end = nd_region->ndr_start + nd_region->ndr_size; 657 658 if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) { 659 ctx->region = nd_region; 660 return 1; 661 } 662 663 return 0; 664 } 665 666 static int nfit_test_search_spa(struct nvdimm_bus *bus, 667 struct nd_cmd_translate_spa *spa) 668 { 669 int ret; 670 struct nd_region *nd_region = NULL; 671 struct nvdimm *nvdimm = NULL; 672 struct nd_mapping *nd_mapping = NULL; 673 struct region_search_spa ctx = { 674 .addr = spa->spa, 675 .region = NULL, 676 }; 677 u64 dpa; 678 679 ret = device_for_each_child(&bus->dev, &ctx, 680 nfit_test_search_region_spa); 681 682 if (!ret) 683 return -ENODEV; 684 685 nd_region = ctx.region; 686 687 dpa = ctx.addr - nd_region->ndr_start; 688 689 /* 690 * last dimm is selected for test 691 */ 692 nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1]; 693 nvdimm = nd_mapping->nvdimm; 694 695 spa->devices[0].nfit_device_handle = handle[nvdimm->id]; 696 spa->num_nvdimms = 1; 697 spa->devices[0].dpa = dpa; 698 699 return 0; 700 } 701 702 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus, 703 struct nd_cmd_translate_spa *spa, unsigned int buf_len) 704 { 705 if (buf_len < spa->translate_length) 706 return -EINVAL; 707 708 if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms) 709 spa->status = 2; 710 711 return 0; 712 } 713 714 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len, 715 struct nd_intel_smart *smart_data) 716 { 717 if (buf_len < sizeof(*smart)) 718 return -EINVAL; 719 memcpy(smart, smart_data, sizeof(*smart)); 720 return 0; 721 } 722 723 static int nfit_test_cmd_smart_threshold( 724 struct nd_intel_smart_threshold *out, 725 unsigned int buf_len, 726 struct nd_intel_smart_threshold *smart_t) 727 { 728 if (buf_len < sizeof(*smart_t)) 729 return -EINVAL; 730 memcpy(out, smart_t, sizeof(*smart_t)); 731 return 0; 732 } 733 734 static void smart_notify(struct device *bus_dev, 735 struct device *dimm_dev, struct nd_intel_smart *smart, 736 struct nd_intel_smart_threshold *thresh) 737 { 738 dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n", 739 __func__, thresh->alarm_control, thresh->spares, 740 smart->spares, thresh->media_temperature, 741 smart->media_temperature, thresh->ctrl_temperature, 742 smart->ctrl_temperature); 743 if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP) 744 && smart->spares 745 <= thresh->spares) 746 || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP) 747 && smart->media_temperature 748 >= thresh->media_temperature) 749 || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP) 750 && smart->ctrl_temperature 751 >= thresh->ctrl_temperature) 752 || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH) 753 || (smart->shutdown_state != 0)) { 754 device_lock(bus_dev); 755 __acpi_nvdimm_notify(dimm_dev, 0x81); 756 device_unlock(bus_dev); 757 } 758 } 759 760 static int nfit_test_cmd_smart_set_threshold( 761 struct nd_intel_smart_set_threshold *in, 762 unsigned int buf_len, 763 struct nd_intel_smart_threshold *thresh, 764 struct nd_intel_smart *smart, 765 struct device *bus_dev, struct device *dimm_dev) 766 { 767 unsigned int size; 768 769 size = sizeof(*in) - 4; 770 if (buf_len < size) 771 return -EINVAL; 772 memcpy(thresh->data, in, size); 773 in->status = 0; 774 smart_notify(bus_dev, dimm_dev, smart, thresh); 775 776 return 0; 777 } 778 779 static int nfit_test_cmd_smart_inject( 780 struct nd_intel_smart_inject *inj, 781 unsigned int buf_len, 782 struct nd_intel_smart_threshold *thresh, 783 struct nd_intel_smart *smart, 784 struct device *bus_dev, struct device *dimm_dev) 785 { 786 if (buf_len != sizeof(*inj)) 787 return -EINVAL; 788 789 if (inj->flags & ND_INTEL_SMART_INJECT_MTEMP) { 790 if (inj->mtemp_enable) 791 smart->media_temperature = inj->media_temperature; 792 else 793 smart->media_temperature = smart_def.media_temperature; 794 } 795 if (inj->flags & ND_INTEL_SMART_INJECT_SPARE) { 796 if (inj->spare_enable) 797 smart->spares = inj->spares; 798 else 799 smart->spares = smart_def.spares; 800 } 801 if (inj->flags & ND_INTEL_SMART_INJECT_FATAL) { 802 if (inj->fatal_enable) 803 smart->health = ND_INTEL_SMART_FATAL_HEALTH; 804 else 805 smart->health = ND_INTEL_SMART_NON_CRITICAL_HEALTH; 806 } 807 if (inj->flags & ND_INTEL_SMART_INJECT_SHUTDOWN) { 808 if (inj->unsafe_shutdown_enable) { 809 smart->shutdown_state = 1; 810 smart->shutdown_count++; 811 } else 812 smart->shutdown_state = 0; 813 } 814 inj->status = 0; 815 smart_notify(bus_dev, dimm_dev, smart, thresh); 816 817 return 0; 818 } 819 820 static void uc_error_notify(struct work_struct *work) 821 { 822 struct nfit_test *t = container_of(work, typeof(*t), work); 823 824 __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR); 825 } 826 827 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t, 828 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len) 829 { 830 int rc; 831 832 if (buf_len != sizeof(*err_inj)) { 833 rc = -EINVAL; 834 goto err; 835 } 836 837 if (err_inj->err_inj_spa_range_length <= 0) { 838 rc = -EINVAL; 839 goto err; 840 } 841 842 rc = badrange_add(&t->badrange, err_inj->err_inj_spa_range_base, 843 err_inj->err_inj_spa_range_length); 844 if (rc < 0) 845 goto err; 846 847 if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY)) 848 queue_work(nfit_wq, &t->work); 849 850 err_inj->status = 0; 851 return 0; 852 853 err: 854 err_inj->status = NFIT_ARS_INJECT_INVALID; 855 return rc; 856 } 857 858 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t, 859 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len) 860 { 861 int rc; 862 863 if (buf_len != sizeof(*err_clr)) { 864 rc = -EINVAL; 865 goto err; 866 } 867 868 if (err_clr->err_inj_clr_spa_range_length <= 0) { 869 rc = -EINVAL; 870 goto err; 871 } 872 873 badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base, 874 err_clr->err_inj_clr_spa_range_length); 875 876 err_clr->status = 0; 877 return 0; 878 879 err: 880 err_clr->status = NFIT_ARS_INJECT_INVALID; 881 return rc; 882 } 883 884 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t, 885 struct nd_cmd_ars_err_inj_stat *err_stat, 886 unsigned int buf_len) 887 { 888 struct badrange_entry *be; 889 int max = SZ_4K / sizeof(struct nd_error_stat_query_record); 890 int i = 0; 891 892 err_stat->status = 0; 893 spin_lock(&t->badrange.lock); 894 list_for_each_entry(be, &t->badrange.list, list) { 895 err_stat->record[i].err_inj_stat_spa_range_base = be->start; 896 err_stat->record[i].err_inj_stat_spa_range_length = be->length; 897 i++; 898 if (i > max) 899 break; 900 } 901 spin_unlock(&t->badrange.lock); 902 err_stat->inj_err_rec_count = i; 903 904 return 0; 905 } 906 907 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t, 908 struct nd_intel_lss *nd_cmd, unsigned int buf_len) 909 { 910 struct device *dev = &t->pdev.dev; 911 912 if (buf_len < sizeof(*nd_cmd)) 913 return -EINVAL; 914 915 switch (nd_cmd->enable) { 916 case 0: 917 nd_cmd->status = 0; 918 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n", 919 __func__); 920 break; 921 case 1: 922 nd_cmd->status = 0; 923 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n", 924 __func__); 925 break; 926 default: 927 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable); 928 nd_cmd->status = 0x3; 929 break; 930 } 931 932 933 return 0; 934 } 935 936 static int override_return_code(int dimm, unsigned int func, int rc) 937 { 938 if ((1 << func) & dimm_fail_cmd_flags[dimm]) { 939 if (dimm_fail_cmd_code[dimm]) 940 return dimm_fail_cmd_code[dimm]; 941 return -EIO; 942 } 943 return rc; 944 } 945 946 static int nd_intel_test_cmd_security_status(struct nfit_test *t, 947 struct nd_intel_get_security_state *nd_cmd, 948 unsigned int buf_len, int dimm) 949 { 950 struct device *dev = &t->pdev.dev; 951 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 952 953 nd_cmd->status = 0; 954 nd_cmd->state = sec->state; 955 nd_cmd->extended_state = sec->ext_state; 956 dev_dbg(dev, "security state (%#x) returned\n", nd_cmd->state); 957 958 return 0; 959 } 960 961 static int nd_intel_test_cmd_unlock_unit(struct nfit_test *t, 962 struct nd_intel_unlock_unit *nd_cmd, 963 unsigned int buf_len, int dimm) 964 { 965 struct device *dev = &t->pdev.dev; 966 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 967 968 if (!(sec->state & ND_INTEL_SEC_STATE_LOCKED) || 969 (sec->state & ND_INTEL_SEC_STATE_FROZEN)) { 970 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE; 971 dev_dbg(dev, "unlock unit: invalid state: %#x\n", 972 sec->state); 973 } else if (memcmp(nd_cmd->passphrase, sec->passphrase, 974 ND_INTEL_PASSPHRASE_SIZE) != 0) { 975 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS; 976 dev_dbg(dev, "unlock unit: invalid passphrase\n"); 977 } else { 978 nd_cmd->status = 0; 979 sec->state = ND_INTEL_SEC_STATE_ENABLED; 980 dev_dbg(dev, "Unit unlocked\n"); 981 } 982 983 dev_dbg(dev, "unlocking status returned: %#x\n", nd_cmd->status); 984 return 0; 985 } 986 987 static int nd_intel_test_cmd_set_pass(struct nfit_test *t, 988 struct nd_intel_set_passphrase *nd_cmd, 989 unsigned int buf_len, int dimm) 990 { 991 struct device *dev = &t->pdev.dev; 992 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 993 994 if (sec->state & ND_INTEL_SEC_STATE_FROZEN) { 995 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE; 996 dev_dbg(dev, "set passphrase: wrong security state\n"); 997 } else if (memcmp(nd_cmd->old_pass, sec->passphrase, 998 ND_INTEL_PASSPHRASE_SIZE) != 0) { 999 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS; 1000 dev_dbg(dev, "set passphrase: wrong passphrase\n"); 1001 } else { 1002 memcpy(sec->passphrase, nd_cmd->new_pass, 1003 ND_INTEL_PASSPHRASE_SIZE); 1004 sec->state |= ND_INTEL_SEC_STATE_ENABLED; 1005 nd_cmd->status = 0; 1006 dev_dbg(dev, "passphrase updated\n"); 1007 } 1008 1009 return 0; 1010 } 1011 1012 static int nd_intel_test_cmd_freeze_lock(struct nfit_test *t, 1013 struct nd_intel_freeze_lock *nd_cmd, 1014 unsigned int buf_len, int dimm) 1015 { 1016 struct device *dev = &t->pdev.dev; 1017 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 1018 1019 if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED)) { 1020 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE; 1021 dev_dbg(dev, "freeze lock: wrong security state\n"); 1022 } else { 1023 sec->state |= ND_INTEL_SEC_STATE_FROZEN; 1024 nd_cmd->status = 0; 1025 dev_dbg(dev, "security frozen\n"); 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int nd_intel_test_cmd_disable_pass(struct nfit_test *t, 1032 struct nd_intel_disable_passphrase *nd_cmd, 1033 unsigned int buf_len, int dimm) 1034 { 1035 struct device *dev = &t->pdev.dev; 1036 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 1037 1038 if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED) || 1039 (sec->state & ND_INTEL_SEC_STATE_FROZEN)) { 1040 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE; 1041 dev_dbg(dev, "disable passphrase: wrong security state\n"); 1042 } else if (memcmp(nd_cmd->passphrase, sec->passphrase, 1043 ND_INTEL_PASSPHRASE_SIZE) != 0) { 1044 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS; 1045 dev_dbg(dev, "disable passphrase: wrong passphrase\n"); 1046 } else { 1047 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE); 1048 sec->state = 0; 1049 dev_dbg(dev, "disable passphrase: done\n"); 1050 } 1051 1052 return 0; 1053 } 1054 1055 static int nd_intel_test_cmd_secure_erase(struct nfit_test *t, 1056 struct nd_intel_secure_erase *nd_cmd, 1057 unsigned int buf_len, int dimm) 1058 { 1059 struct device *dev = &t->pdev.dev; 1060 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 1061 1062 if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED) || 1063 (sec->state & ND_INTEL_SEC_STATE_FROZEN)) { 1064 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE; 1065 dev_dbg(dev, "secure erase: wrong security state\n"); 1066 } else if (memcmp(nd_cmd->passphrase, sec->passphrase, 1067 ND_INTEL_PASSPHRASE_SIZE) != 0) { 1068 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS; 1069 dev_dbg(dev, "secure erase: wrong passphrase\n"); 1070 } else { 1071 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE); 1072 memset(sec->master_passphrase, 0, ND_INTEL_PASSPHRASE_SIZE); 1073 sec->state = 0; 1074 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED; 1075 dev_dbg(dev, "secure erase: done\n"); 1076 } 1077 1078 return 0; 1079 } 1080 1081 static int nd_intel_test_cmd_overwrite(struct nfit_test *t, 1082 struct nd_intel_overwrite *nd_cmd, 1083 unsigned int buf_len, int dimm) 1084 { 1085 struct device *dev = &t->pdev.dev; 1086 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 1087 1088 if ((sec->state & ND_INTEL_SEC_STATE_ENABLED) && 1089 memcmp(nd_cmd->passphrase, sec->passphrase, 1090 ND_INTEL_PASSPHRASE_SIZE) != 0) { 1091 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS; 1092 dev_dbg(dev, "overwrite: wrong passphrase\n"); 1093 return 0; 1094 } 1095 1096 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE); 1097 sec->state = ND_INTEL_SEC_STATE_OVERWRITE; 1098 dev_dbg(dev, "overwrite progressing.\n"); 1099 sec->overwrite_end_time = get_jiffies_64() + 5 * HZ; 1100 1101 return 0; 1102 } 1103 1104 static int nd_intel_test_cmd_query_overwrite(struct nfit_test *t, 1105 struct nd_intel_query_overwrite *nd_cmd, 1106 unsigned int buf_len, int dimm) 1107 { 1108 struct device *dev = &t->pdev.dev; 1109 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 1110 1111 if (!(sec->state & ND_INTEL_SEC_STATE_OVERWRITE)) { 1112 nd_cmd->status = ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR; 1113 return 0; 1114 } 1115 1116 if (time_is_before_jiffies64(sec->overwrite_end_time)) { 1117 sec->overwrite_end_time = 0; 1118 sec->state = 0; 1119 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED; 1120 dev_dbg(dev, "overwrite is complete\n"); 1121 } else 1122 nd_cmd->status = ND_INTEL_STATUS_OQUERY_INPROGRESS; 1123 return 0; 1124 } 1125 1126 static int nd_intel_test_cmd_master_set_pass(struct nfit_test *t, 1127 struct nd_intel_set_master_passphrase *nd_cmd, 1128 unsigned int buf_len, int dimm) 1129 { 1130 struct device *dev = &t->pdev.dev; 1131 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 1132 1133 if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) { 1134 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED; 1135 dev_dbg(dev, "master set passphrase: in wrong state\n"); 1136 } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) { 1137 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE; 1138 dev_dbg(dev, "master set passphrase: in wrong security state\n"); 1139 } else if (memcmp(nd_cmd->old_pass, sec->master_passphrase, 1140 ND_INTEL_PASSPHRASE_SIZE) != 0) { 1141 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS; 1142 dev_dbg(dev, "master set passphrase: wrong passphrase\n"); 1143 } else { 1144 memcpy(sec->master_passphrase, nd_cmd->new_pass, 1145 ND_INTEL_PASSPHRASE_SIZE); 1146 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED; 1147 dev_dbg(dev, "master passphrase: updated\n"); 1148 } 1149 1150 return 0; 1151 } 1152 1153 static int nd_intel_test_cmd_master_secure_erase(struct nfit_test *t, 1154 struct nd_intel_master_secure_erase *nd_cmd, 1155 unsigned int buf_len, int dimm) 1156 { 1157 struct device *dev = &t->pdev.dev; 1158 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 1159 1160 if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) { 1161 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED; 1162 dev_dbg(dev, "master secure erase: in wrong state\n"); 1163 } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) { 1164 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE; 1165 dev_dbg(dev, "master secure erase: in wrong security state\n"); 1166 } else if (memcmp(nd_cmd->passphrase, sec->master_passphrase, 1167 ND_INTEL_PASSPHRASE_SIZE) != 0) { 1168 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS; 1169 dev_dbg(dev, "master secure erase: wrong passphrase\n"); 1170 } else { 1171 /* we do not erase master state passphrase ever */ 1172 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED; 1173 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE); 1174 sec->state = 0; 1175 dev_dbg(dev, "master secure erase: done\n"); 1176 } 1177 1178 return 0; 1179 } 1180 1181 1182 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func) 1183 { 1184 int i; 1185 1186 /* lookup per-dimm data */ 1187 for (i = 0; i < ARRAY_SIZE(handle); i++) 1188 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i]) 1189 break; 1190 if (i >= ARRAY_SIZE(handle)) 1191 return -ENXIO; 1192 return i; 1193 } 1194 1195 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc, 1196 struct nvdimm *nvdimm, unsigned int cmd, void *buf, 1197 unsigned int buf_len, int *cmd_rc) 1198 { 1199 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); 1200 struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc); 1201 unsigned int func = cmd; 1202 int i, rc = 0, __cmd_rc; 1203 1204 if (!cmd_rc) 1205 cmd_rc = &__cmd_rc; 1206 *cmd_rc = 0; 1207 1208 if (nvdimm) { 1209 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); 1210 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm); 1211 1212 if (!nfit_mem) 1213 return -ENOTTY; 1214 1215 if (cmd == ND_CMD_CALL) { 1216 struct nd_cmd_pkg *call_pkg = buf; 1217 1218 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out; 1219 buf = (void *) call_pkg->nd_payload; 1220 func = call_pkg->nd_command; 1221 if (call_pkg->nd_family != nfit_mem->family) 1222 return -ENOTTY; 1223 1224 i = get_dimm(nfit_mem, func); 1225 if (i < 0) 1226 return i; 1227 1228 switch (func) { 1229 case NVDIMM_INTEL_GET_SECURITY_STATE: 1230 rc = nd_intel_test_cmd_security_status(t, 1231 buf, buf_len, i); 1232 break; 1233 case NVDIMM_INTEL_UNLOCK_UNIT: 1234 rc = nd_intel_test_cmd_unlock_unit(t, 1235 buf, buf_len, i); 1236 break; 1237 case NVDIMM_INTEL_SET_PASSPHRASE: 1238 rc = nd_intel_test_cmd_set_pass(t, 1239 buf, buf_len, i); 1240 break; 1241 case NVDIMM_INTEL_DISABLE_PASSPHRASE: 1242 rc = nd_intel_test_cmd_disable_pass(t, 1243 buf, buf_len, i); 1244 break; 1245 case NVDIMM_INTEL_FREEZE_LOCK: 1246 rc = nd_intel_test_cmd_freeze_lock(t, 1247 buf, buf_len, i); 1248 break; 1249 case NVDIMM_INTEL_SECURE_ERASE: 1250 rc = nd_intel_test_cmd_secure_erase(t, 1251 buf, buf_len, i); 1252 break; 1253 case NVDIMM_INTEL_OVERWRITE: 1254 rc = nd_intel_test_cmd_overwrite(t, 1255 buf, buf_len, i - t->dcr_idx); 1256 break; 1257 case NVDIMM_INTEL_QUERY_OVERWRITE: 1258 rc = nd_intel_test_cmd_query_overwrite(t, 1259 buf, buf_len, i - t->dcr_idx); 1260 break; 1261 case NVDIMM_INTEL_SET_MASTER_PASSPHRASE: 1262 rc = nd_intel_test_cmd_master_set_pass(t, 1263 buf, buf_len, i); 1264 break; 1265 case NVDIMM_INTEL_MASTER_SECURE_ERASE: 1266 rc = nd_intel_test_cmd_master_secure_erase(t, 1267 buf, buf_len, i); 1268 break; 1269 case ND_INTEL_ENABLE_LSS_STATUS: 1270 rc = nd_intel_test_cmd_set_lss_status(t, 1271 buf, buf_len); 1272 break; 1273 case ND_INTEL_FW_GET_INFO: 1274 rc = nd_intel_test_get_fw_info(t, buf, 1275 buf_len, i - t->dcr_idx); 1276 break; 1277 case ND_INTEL_FW_START_UPDATE: 1278 rc = nd_intel_test_start_update(t, buf, 1279 buf_len, i - t->dcr_idx); 1280 break; 1281 case ND_INTEL_FW_SEND_DATA: 1282 rc = nd_intel_test_send_data(t, buf, 1283 buf_len, i - t->dcr_idx); 1284 break; 1285 case ND_INTEL_FW_FINISH_UPDATE: 1286 rc = nd_intel_test_finish_fw(t, buf, 1287 buf_len, i - t->dcr_idx); 1288 break; 1289 case ND_INTEL_FW_FINISH_QUERY: 1290 rc = nd_intel_test_finish_query(t, buf, 1291 buf_len, i - t->dcr_idx); 1292 break; 1293 case ND_INTEL_SMART: 1294 rc = nfit_test_cmd_smart(buf, buf_len, 1295 &t->smart[i - t->dcr_idx]); 1296 break; 1297 case ND_INTEL_SMART_THRESHOLD: 1298 rc = nfit_test_cmd_smart_threshold(buf, 1299 buf_len, 1300 &t->smart_threshold[i - 1301 t->dcr_idx]); 1302 break; 1303 case ND_INTEL_SMART_SET_THRESHOLD: 1304 rc = nfit_test_cmd_smart_set_threshold(buf, 1305 buf_len, 1306 &t->smart_threshold[i - 1307 t->dcr_idx], 1308 &t->smart[i - t->dcr_idx], 1309 &t->pdev.dev, t->dimm_dev[i]); 1310 break; 1311 case ND_INTEL_SMART_INJECT: 1312 rc = nfit_test_cmd_smart_inject(buf, 1313 buf_len, 1314 &t->smart_threshold[i - 1315 t->dcr_idx], 1316 &t->smart[i - t->dcr_idx], 1317 &t->pdev.dev, t->dimm_dev[i]); 1318 break; 1319 default: 1320 return -ENOTTY; 1321 } 1322 return override_return_code(i, func, rc); 1323 } 1324 1325 if (!test_bit(cmd, &cmd_mask) 1326 || !test_bit(func, &nfit_mem->dsm_mask)) 1327 return -ENOTTY; 1328 1329 i = get_dimm(nfit_mem, func); 1330 if (i < 0) 1331 return i; 1332 1333 switch (func) { 1334 case ND_CMD_GET_CONFIG_SIZE: 1335 rc = nfit_test_cmd_get_config_size(buf, buf_len); 1336 break; 1337 case ND_CMD_GET_CONFIG_DATA: 1338 rc = nfit_test_cmd_get_config_data(buf, buf_len, 1339 t->label[i - t->dcr_idx]); 1340 break; 1341 case ND_CMD_SET_CONFIG_DATA: 1342 rc = nfit_test_cmd_set_config_data(buf, buf_len, 1343 t->label[i - t->dcr_idx]); 1344 break; 1345 default: 1346 return -ENOTTY; 1347 } 1348 return override_return_code(i, func, rc); 1349 } else { 1350 struct ars_state *ars_state = &t->ars_state; 1351 struct nd_cmd_pkg *call_pkg = buf; 1352 1353 if (!nd_desc) 1354 return -ENOTTY; 1355 1356 if (cmd == ND_CMD_CALL) { 1357 func = call_pkg->nd_command; 1358 1359 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out; 1360 buf = (void *) call_pkg->nd_payload; 1361 1362 switch (func) { 1363 case NFIT_CMD_TRANSLATE_SPA: 1364 rc = nfit_test_cmd_translate_spa( 1365 acpi_desc->nvdimm_bus, buf, buf_len); 1366 return rc; 1367 case NFIT_CMD_ARS_INJECT_SET: 1368 rc = nfit_test_cmd_ars_error_inject(t, buf, 1369 buf_len); 1370 return rc; 1371 case NFIT_CMD_ARS_INJECT_CLEAR: 1372 rc = nfit_test_cmd_ars_inject_clear(t, buf, 1373 buf_len); 1374 return rc; 1375 case NFIT_CMD_ARS_INJECT_GET: 1376 rc = nfit_test_cmd_ars_inject_status(t, buf, 1377 buf_len); 1378 return rc; 1379 default: 1380 return -ENOTTY; 1381 } 1382 } 1383 1384 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask)) 1385 return -ENOTTY; 1386 1387 switch (func) { 1388 case ND_CMD_ARS_CAP: 1389 rc = nfit_test_cmd_ars_cap(buf, buf_len); 1390 break; 1391 case ND_CMD_ARS_START: 1392 rc = nfit_test_cmd_ars_start(t, ars_state, buf, 1393 buf_len, cmd_rc); 1394 break; 1395 case ND_CMD_ARS_STATUS: 1396 rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len, 1397 cmd_rc); 1398 break; 1399 case ND_CMD_CLEAR_ERROR: 1400 rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc); 1401 break; 1402 default: 1403 return -ENOTTY; 1404 } 1405 } 1406 1407 return rc; 1408 } 1409 1410 static DEFINE_SPINLOCK(nfit_test_lock); 1411 static struct nfit_test *instances[NUM_NFITS]; 1412 1413 static void release_nfit_res(void *data) 1414 { 1415 struct nfit_test_resource *nfit_res = data; 1416 1417 spin_lock(&nfit_test_lock); 1418 list_del(&nfit_res->list); 1419 spin_unlock(&nfit_test_lock); 1420 1421 if (resource_size(&nfit_res->res) >= DIMM_SIZE) 1422 gen_pool_free(nfit_pool, nfit_res->res.start, 1423 resource_size(&nfit_res->res)); 1424 vfree(nfit_res->buf); 1425 kfree(nfit_res); 1426 } 1427 1428 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma, 1429 void *buf) 1430 { 1431 struct device *dev = &t->pdev.dev; 1432 struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res), 1433 GFP_KERNEL); 1434 int rc; 1435 1436 if (!buf || !nfit_res || !*dma) 1437 goto err; 1438 rc = devm_add_action(dev, release_nfit_res, nfit_res); 1439 if (rc) 1440 goto err; 1441 INIT_LIST_HEAD(&nfit_res->list); 1442 memset(buf, 0, size); 1443 nfit_res->dev = dev; 1444 nfit_res->buf = buf; 1445 nfit_res->res.start = *dma; 1446 nfit_res->res.end = *dma + size - 1; 1447 nfit_res->res.name = "NFIT"; 1448 spin_lock_init(&nfit_res->lock); 1449 INIT_LIST_HEAD(&nfit_res->requests); 1450 spin_lock(&nfit_test_lock); 1451 list_add(&nfit_res->list, &t->resources); 1452 spin_unlock(&nfit_test_lock); 1453 1454 return nfit_res->buf; 1455 err: 1456 if (*dma && size >= DIMM_SIZE) 1457 gen_pool_free(nfit_pool, *dma, size); 1458 if (buf) 1459 vfree(buf); 1460 kfree(nfit_res); 1461 return NULL; 1462 } 1463 1464 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma) 1465 { 1466 struct genpool_data_align data = { 1467 .align = SZ_128M, 1468 }; 1469 void *buf = vmalloc(size); 1470 1471 if (size >= DIMM_SIZE) 1472 *dma = gen_pool_alloc_algo(nfit_pool, size, 1473 gen_pool_first_fit_align, &data); 1474 else 1475 *dma = (unsigned long) buf; 1476 return __test_alloc(t, size, dma, buf); 1477 } 1478 1479 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr) 1480 { 1481 int i; 1482 1483 for (i = 0; i < ARRAY_SIZE(instances); i++) { 1484 struct nfit_test_resource *n, *nfit_res = NULL; 1485 struct nfit_test *t = instances[i]; 1486 1487 if (!t) 1488 continue; 1489 spin_lock(&nfit_test_lock); 1490 list_for_each_entry(n, &t->resources, list) { 1491 if (addr >= n->res.start && (addr < n->res.start 1492 + resource_size(&n->res))) { 1493 nfit_res = n; 1494 break; 1495 } else if (addr >= (unsigned long) n->buf 1496 && (addr < (unsigned long) n->buf 1497 + resource_size(&n->res))) { 1498 nfit_res = n; 1499 break; 1500 } 1501 } 1502 spin_unlock(&nfit_test_lock); 1503 if (nfit_res) 1504 return nfit_res; 1505 } 1506 1507 return NULL; 1508 } 1509 1510 static int ars_state_init(struct device *dev, struct ars_state *ars_state) 1511 { 1512 /* for testing, only store up to n records that fit within 4k */ 1513 ars_state->ars_status = devm_kzalloc(dev, 1514 sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL); 1515 if (!ars_state->ars_status) 1516 return -ENOMEM; 1517 spin_lock_init(&ars_state->lock); 1518 return 0; 1519 } 1520 1521 static void put_dimms(void *data) 1522 { 1523 struct nfit_test *t = data; 1524 int i; 1525 1526 for (i = 0; i < t->num_dcr; i++) 1527 if (t->dimm_dev[i]) 1528 device_unregister(t->dimm_dev[i]); 1529 } 1530 1531 static struct class *nfit_test_dimm; 1532 1533 static int dimm_name_to_id(struct device *dev) 1534 { 1535 int dimm; 1536 1537 if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1) 1538 return -ENXIO; 1539 return dimm; 1540 } 1541 1542 static ssize_t handle_show(struct device *dev, struct device_attribute *attr, 1543 char *buf) 1544 { 1545 int dimm = dimm_name_to_id(dev); 1546 1547 if (dimm < 0) 1548 return dimm; 1549 1550 return sprintf(buf, "%#x\n", handle[dimm]); 1551 } 1552 DEVICE_ATTR_RO(handle); 1553 1554 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr, 1555 char *buf) 1556 { 1557 int dimm = dimm_name_to_id(dev); 1558 1559 if (dimm < 0) 1560 return dimm; 1561 1562 return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]); 1563 } 1564 1565 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr, 1566 const char *buf, size_t size) 1567 { 1568 int dimm = dimm_name_to_id(dev); 1569 unsigned long val; 1570 ssize_t rc; 1571 1572 if (dimm < 0) 1573 return dimm; 1574 1575 rc = kstrtol(buf, 0, &val); 1576 if (rc) 1577 return rc; 1578 1579 dimm_fail_cmd_flags[dimm] = val; 1580 return size; 1581 } 1582 static DEVICE_ATTR_RW(fail_cmd); 1583 1584 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr, 1585 char *buf) 1586 { 1587 int dimm = dimm_name_to_id(dev); 1588 1589 if (dimm < 0) 1590 return dimm; 1591 1592 return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]); 1593 } 1594 1595 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr, 1596 const char *buf, size_t size) 1597 { 1598 int dimm = dimm_name_to_id(dev); 1599 unsigned long val; 1600 ssize_t rc; 1601 1602 if (dimm < 0) 1603 return dimm; 1604 1605 rc = kstrtol(buf, 0, &val); 1606 if (rc) 1607 return rc; 1608 1609 dimm_fail_cmd_code[dimm] = val; 1610 return size; 1611 } 1612 static DEVICE_ATTR_RW(fail_cmd_code); 1613 1614 static ssize_t lock_dimm_store(struct device *dev, 1615 struct device_attribute *attr, const char *buf, size_t size) 1616 { 1617 int dimm = dimm_name_to_id(dev); 1618 struct nfit_test_sec *sec = &dimm_sec_info[dimm]; 1619 1620 sec->state = ND_INTEL_SEC_STATE_ENABLED | ND_INTEL_SEC_STATE_LOCKED; 1621 return size; 1622 } 1623 static DEVICE_ATTR_WO(lock_dimm); 1624 1625 static struct attribute *nfit_test_dimm_attributes[] = { 1626 &dev_attr_fail_cmd.attr, 1627 &dev_attr_fail_cmd_code.attr, 1628 &dev_attr_handle.attr, 1629 &dev_attr_lock_dimm.attr, 1630 NULL, 1631 }; 1632 1633 static struct attribute_group nfit_test_dimm_attribute_group = { 1634 .attrs = nfit_test_dimm_attributes, 1635 }; 1636 1637 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = { 1638 &nfit_test_dimm_attribute_group, 1639 NULL, 1640 }; 1641 1642 static int nfit_test_dimm_init(struct nfit_test *t) 1643 { 1644 int i; 1645 1646 if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t)) 1647 return -ENOMEM; 1648 for (i = 0; i < t->num_dcr; i++) { 1649 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm, 1650 &t->pdev.dev, 0, NULL, 1651 nfit_test_dimm_attribute_groups, 1652 "test_dimm%d", i + t->dcr_idx); 1653 if (!t->dimm_dev[i]) 1654 return -ENOMEM; 1655 } 1656 return 0; 1657 } 1658 1659 static void security_init(struct nfit_test *t) 1660 { 1661 int i; 1662 1663 for (i = 0; i < t->num_dcr; i++) { 1664 struct nfit_test_sec *sec = &dimm_sec_info[i]; 1665 1666 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED; 1667 } 1668 } 1669 1670 static void smart_init(struct nfit_test *t) 1671 { 1672 int i; 1673 const struct nd_intel_smart_threshold smart_t_data = { 1674 .alarm_control = ND_INTEL_SMART_SPARE_TRIP 1675 | ND_INTEL_SMART_TEMP_TRIP, 1676 .media_temperature = 40 * 16, 1677 .ctrl_temperature = 30 * 16, 1678 .spares = 5, 1679 }; 1680 1681 for (i = 0; i < t->num_dcr; i++) { 1682 memcpy(&t->smart[i], &smart_def, sizeof(smart_def)); 1683 memcpy(&t->smart_threshold[i], &smart_t_data, 1684 sizeof(smart_t_data)); 1685 } 1686 } 1687 1688 static int nfit_test0_alloc(struct nfit_test *t) 1689 { 1690 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA 1691 + sizeof(struct acpi_nfit_memory_map) * NUM_MEM 1692 + sizeof(struct acpi_nfit_control_region) * NUM_DCR 1693 + offsetof(struct acpi_nfit_control_region, 1694 window_size) * NUM_DCR 1695 + sizeof(struct acpi_nfit_data_region) * NUM_BDW 1696 + (sizeof(struct acpi_nfit_flush_address) 1697 + sizeof(u64) * NUM_HINTS) * NUM_DCR 1698 + sizeof(struct acpi_nfit_capabilities); 1699 int i; 1700 1701 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma); 1702 if (!t->nfit_buf) 1703 return -ENOMEM; 1704 t->nfit_size = nfit_size; 1705 1706 t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]); 1707 if (!t->spa_set[0]) 1708 return -ENOMEM; 1709 1710 t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]); 1711 if (!t->spa_set[1]) 1712 return -ENOMEM; 1713 1714 t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]); 1715 if (!t->spa_set[2]) 1716 return -ENOMEM; 1717 1718 for (i = 0; i < t->num_dcr; i++) { 1719 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]); 1720 if (!t->dimm[i]) 1721 return -ENOMEM; 1722 1723 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]); 1724 if (!t->label[i]) 1725 return -ENOMEM; 1726 sprintf(t->label[i], "label%d", i); 1727 1728 t->flush[i] = test_alloc(t, max(PAGE_SIZE, 1729 sizeof(u64) * NUM_HINTS), 1730 &t->flush_dma[i]); 1731 if (!t->flush[i]) 1732 return -ENOMEM; 1733 } 1734 1735 for (i = 0; i < t->num_dcr; i++) { 1736 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]); 1737 if (!t->dcr[i]) 1738 return -ENOMEM; 1739 } 1740 1741 t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma); 1742 if (!t->_fit) 1743 return -ENOMEM; 1744 1745 if (nfit_test_dimm_init(t)) 1746 return -ENOMEM; 1747 smart_init(t); 1748 security_init(t); 1749 return ars_state_init(&t->pdev.dev, &t->ars_state); 1750 } 1751 1752 static int nfit_test1_alloc(struct nfit_test *t) 1753 { 1754 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2 1755 + sizeof(struct acpi_nfit_memory_map) * 2 1756 + offsetof(struct acpi_nfit_control_region, window_size) * 2; 1757 int i; 1758 1759 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma); 1760 if (!t->nfit_buf) 1761 return -ENOMEM; 1762 t->nfit_size = nfit_size; 1763 1764 t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]); 1765 if (!t->spa_set[0]) 1766 return -ENOMEM; 1767 1768 for (i = 0; i < t->num_dcr; i++) { 1769 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]); 1770 if (!t->label[i]) 1771 return -ENOMEM; 1772 sprintf(t->label[i], "label%d", i); 1773 } 1774 1775 t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]); 1776 if (!t->spa_set[1]) 1777 return -ENOMEM; 1778 1779 if (nfit_test_dimm_init(t)) 1780 return -ENOMEM; 1781 smart_init(t); 1782 return ars_state_init(&t->pdev.dev, &t->ars_state); 1783 } 1784 1785 static void dcr_common_init(struct acpi_nfit_control_region *dcr) 1786 { 1787 dcr->vendor_id = 0xabcd; 1788 dcr->device_id = 0; 1789 dcr->revision_id = 1; 1790 dcr->valid_fields = 1; 1791 dcr->manufacturing_location = 0xa; 1792 dcr->manufacturing_date = cpu_to_be16(2016); 1793 } 1794 1795 static void nfit_test0_setup(struct nfit_test *t) 1796 { 1797 const int flush_hint_size = sizeof(struct acpi_nfit_flush_address) 1798 + (sizeof(u64) * NUM_HINTS); 1799 struct acpi_nfit_desc *acpi_desc; 1800 struct acpi_nfit_memory_map *memdev; 1801 void *nfit_buf = t->nfit_buf; 1802 struct acpi_nfit_system_address *spa; 1803 struct acpi_nfit_control_region *dcr; 1804 struct acpi_nfit_data_region *bdw; 1805 struct acpi_nfit_flush_address *flush; 1806 struct acpi_nfit_capabilities *pcap; 1807 unsigned int offset = 0, i; 1808 1809 /* 1810 * spa0 (interleave first half of dimm0 and dimm1, note storage 1811 * does not actually alias the related block-data-window 1812 * regions) 1813 */ 1814 spa = nfit_buf; 1815 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1816 spa->header.length = sizeof(*spa); 1817 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 1818 spa->range_index = 0+1; 1819 spa->address = t->spa_set_dma[0]; 1820 spa->length = SPA0_SIZE; 1821 offset += spa->header.length; 1822 1823 /* 1824 * spa1 (interleave last half of the 4 DIMMS, note storage 1825 * does not actually alias the related block-data-window 1826 * regions) 1827 */ 1828 spa = nfit_buf + offset; 1829 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1830 spa->header.length = sizeof(*spa); 1831 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 1832 spa->range_index = 1+1; 1833 spa->address = t->spa_set_dma[1]; 1834 spa->length = SPA1_SIZE; 1835 offset += spa->header.length; 1836 1837 /* spa2 (dcr0) dimm0 */ 1838 spa = nfit_buf + offset; 1839 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1840 spa->header.length = sizeof(*spa); 1841 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1842 spa->range_index = 2+1; 1843 spa->address = t->dcr_dma[0]; 1844 spa->length = DCR_SIZE; 1845 offset += spa->header.length; 1846 1847 /* spa3 (dcr1) dimm1 */ 1848 spa = nfit_buf + offset; 1849 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1850 spa->header.length = sizeof(*spa); 1851 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1852 spa->range_index = 3+1; 1853 spa->address = t->dcr_dma[1]; 1854 spa->length = DCR_SIZE; 1855 offset += spa->header.length; 1856 1857 /* spa4 (dcr2) dimm2 */ 1858 spa = nfit_buf + offset; 1859 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1860 spa->header.length = sizeof(*spa); 1861 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1862 spa->range_index = 4+1; 1863 spa->address = t->dcr_dma[2]; 1864 spa->length = DCR_SIZE; 1865 offset += spa->header.length; 1866 1867 /* spa5 (dcr3) dimm3 */ 1868 spa = nfit_buf + offset; 1869 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1870 spa->header.length = sizeof(*spa); 1871 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1872 spa->range_index = 5+1; 1873 spa->address = t->dcr_dma[3]; 1874 spa->length = DCR_SIZE; 1875 offset += spa->header.length; 1876 1877 /* spa6 (bdw for dcr0) dimm0 */ 1878 spa = nfit_buf + offset; 1879 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1880 spa->header.length = sizeof(*spa); 1881 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1882 spa->range_index = 6+1; 1883 spa->address = t->dimm_dma[0]; 1884 spa->length = DIMM_SIZE; 1885 offset += spa->header.length; 1886 1887 /* spa7 (bdw for dcr1) dimm1 */ 1888 spa = nfit_buf + offset; 1889 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1890 spa->header.length = sizeof(*spa); 1891 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1892 spa->range_index = 7+1; 1893 spa->address = t->dimm_dma[1]; 1894 spa->length = DIMM_SIZE; 1895 offset += spa->header.length; 1896 1897 /* spa8 (bdw for dcr2) dimm2 */ 1898 spa = nfit_buf + offset; 1899 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1900 spa->header.length = sizeof(*spa); 1901 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1902 spa->range_index = 8+1; 1903 spa->address = t->dimm_dma[2]; 1904 spa->length = DIMM_SIZE; 1905 offset += spa->header.length; 1906 1907 /* spa9 (bdw for dcr3) dimm3 */ 1908 spa = nfit_buf + offset; 1909 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1910 spa->header.length = sizeof(*spa); 1911 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1912 spa->range_index = 9+1; 1913 spa->address = t->dimm_dma[3]; 1914 spa->length = DIMM_SIZE; 1915 offset += spa->header.length; 1916 1917 /* mem-region0 (spa0, dimm0) */ 1918 memdev = nfit_buf + offset; 1919 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1920 memdev->header.length = sizeof(*memdev); 1921 memdev->device_handle = handle[0]; 1922 memdev->physical_id = 0; 1923 memdev->region_id = 0; 1924 memdev->range_index = 0+1; 1925 memdev->region_index = 4+1; 1926 memdev->region_size = SPA0_SIZE/2; 1927 memdev->region_offset = 1; 1928 memdev->address = 0; 1929 memdev->interleave_index = 0; 1930 memdev->interleave_ways = 2; 1931 offset += memdev->header.length; 1932 1933 /* mem-region1 (spa0, dimm1) */ 1934 memdev = nfit_buf + offset; 1935 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1936 memdev->header.length = sizeof(*memdev); 1937 memdev->device_handle = handle[1]; 1938 memdev->physical_id = 1; 1939 memdev->region_id = 0; 1940 memdev->range_index = 0+1; 1941 memdev->region_index = 5+1; 1942 memdev->region_size = SPA0_SIZE/2; 1943 memdev->region_offset = (1 << 8); 1944 memdev->address = 0; 1945 memdev->interleave_index = 0; 1946 memdev->interleave_ways = 2; 1947 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1948 offset += memdev->header.length; 1949 1950 /* mem-region2 (spa1, dimm0) */ 1951 memdev = nfit_buf + offset; 1952 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1953 memdev->header.length = sizeof(*memdev); 1954 memdev->device_handle = handle[0]; 1955 memdev->physical_id = 0; 1956 memdev->region_id = 1; 1957 memdev->range_index = 1+1; 1958 memdev->region_index = 4+1; 1959 memdev->region_size = SPA1_SIZE/4; 1960 memdev->region_offset = (1 << 16); 1961 memdev->address = SPA0_SIZE/2; 1962 memdev->interleave_index = 0; 1963 memdev->interleave_ways = 4; 1964 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1965 offset += memdev->header.length; 1966 1967 /* mem-region3 (spa1, dimm1) */ 1968 memdev = nfit_buf + offset; 1969 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1970 memdev->header.length = sizeof(*memdev); 1971 memdev->device_handle = handle[1]; 1972 memdev->physical_id = 1; 1973 memdev->region_id = 1; 1974 memdev->range_index = 1+1; 1975 memdev->region_index = 5+1; 1976 memdev->region_size = SPA1_SIZE/4; 1977 memdev->region_offset = (1 << 24); 1978 memdev->address = SPA0_SIZE/2; 1979 memdev->interleave_index = 0; 1980 memdev->interleave_ways = 4; 1981 offset += memdev->header.length; 1982 1983 /* mem-region4 (spa1, dimm2) */ 1984 memdev = nfit_buf + offset; 1985 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1986 memdev->header.length = sizeof(*memdev); 1987 memdev->device_handle = handle[2]; 1988 memdev->physical_id = 2; 1989 memdev->region_id = 0; 1990 memdev->range_index = 1+1; 1991 memdev->region_index = 6+1; 1992 memdev->region_size = SPA1_SIZE/4; 1993 memdev->region_offset = (1ULL << 32); 1994 memdev->address = SPA0_SIZE/2; 1995 memdev->interleave_index = 0; 1996 memdev->interleave_ways = 4; 1997 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1998 offset += memdev->header.length; 1999 2000 /* mem-region5 (spa1, dimm3) */ 2001 memdev = nfit_buf + offset; 2002 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2003 memdev->header.length = sizeof(*memdev); 2004 memdev->device_handle = handle[3]; 2005 memdev->physical_id = 3; 2006 memdev->region_id = 0; 2007 memdev->range_index = 1+1; 2008 memdev->region_index = 7+1; 2009 memdev->region_size = SPA1_SIZE/4; 2010 memdev->region_offset = (1ULL << 40); 2011 memdev->address = SPA0_SIZE/2; 2012 memdev->interleave_index = 0; 2013 memdev->interleave_ways = 4; 2014 offset += memdev->header.length; 2015 2016 /* mem-region6 (spa/dcr0, dimm0) */ 2017 memdev = nfit_buf + offset; 2018 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2019 memdev->header.length = sizeof(*memdev); 2020 memdev->device_handle = handle[0]; 2021 memdev->physical_id = 0; 2022 memdev->region_id = 0; 2023 memdev->range_index = 2+1; 2024 memdev->region_index = 0+1; 2025 memdev->region_size = 0; 2026 memdev->region_offset = 0; 2027 memdev->address = 0; 2028 memdev->interleave_index = 0; 2029 memdev->interleave_ways = 1; 2030 offset += memdev->header.length; 2031 2032 /* mem-region7 (spa/dcr1, dimm1) */ 2033 memdev = nfit_buf + offset; 2034 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2035 memdev->header.length = sizeof(*memdev); 2036 memdev->device_handle = handle[1]; 2037 memdev->physical_id = 1; 2038 memdev->region_id = 0; 2039 memdev->range_index = 3+1; 2040 memdev->region_index = 1+1; 2041 memdev->region_size = 0; 2042 memdev->region_offset = 0; 2043 memdev->address = 0; 2044 memdev->interleave_index = 0; 2045 memdev->interleave_ways = 1; 2046 offset += memdev->header.length; 2047 2048 /* mem-region8 (spa/dcr2, dimm2) */ 2049 memdev = nfit_buf + offset; 2050 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2051 memdev->header.length = sizeof(*memdev); 2052 memdev->device_handle = handle[2]; 2053 memdev->physical_id = 2; 2054 memdev->region_id = 0; 2055 memdev->range_index = 4+1; 2056 memdev->region_index = 2+1; 2057 memdev->region_size = 0; 2058 memdev->region_offset = 0; 2059 memdev->address = 0; 2060 memdev->interleave_index = 0; 2061 memdev->interleave_ways = 1; 2062 offset += memdev->header.length; 2063 2064 /* mem-region9 (spa/dcr3, dimm3) */ 2065 memdev = nfit_buf + offset; 2066 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2067 memdev->header.length = sizeof(*memdev); 2068 memdev->device_handle = handle[3]; 2069 memdev->physical_id = 3; 2070 memdev->region_id = 0; 2071 memdev->range_index = 5+1; 2072 memdev->region_index = 3+1; 2073 memdev->region_size = 0; 2074 memdev->region_offset = 0; 2075 memdev->address = 0; 2076 memdev->interleave_index = 0; 2077 memdev->interleave_ways = 1; 2078 offset += memdev->header.length; 2079 2080 /* mem-region10 (spa/bdw0, dimm0) */ 2081 memdev = nfit_buf + offset; 2082 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2083 memdev->header.length = sizeof(*memdev); 2084 memdev->device_handle = handle[0]; 2085 memdev->physical_id = 0; 2086 memdev->region_id = 0; 2087 memdev->range_index = 6+1; 2088 memdev->region_index = 0+1; 2089 memdev->region_size = 0; 2090 memdev->region_offset = 0; 2091 memdev->address = 0; 2092 memdev->interleave_index = 0; 2093 memdev->interleave_ways = 1; 2094 offset += memdev->header.length; 2095 2096 /* mem-region11 (spa/bdw1, dimm1) */ 2097 memdev = nfit_buf + offset; 2098 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2099 memdev->header.length = sizeof(*memdev); 2100 memdev->device_handle = handle[1]; 2101 memdev->physical_id = 1; 2102 memdev->region_id = 0; 2103 memdev->range_index = 7+1; 2104 memdev->region_index = 1+1; 2105 memdev->region_size = 0; 2106 memdev->region_offset = 0; 2107 memdev->address = 0; 2108 memdev->interleave_index = 0; 2109 memdev->interleave_ways = 1; 2110 offset += memdev->header.length; 2111 2112 /* mem-region12 (spa/bdw2, dimm2) */ 2113 memdev = nfit_buf + offset; 2114 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2115 memdev->header.length = sizeof(*memdev); 2116 memdev->device_handle = handle[2]; 2117 memdev->physical_id = 2; 2118 memdev->region_id = 0; 2119 memdev->range_index = 8+1; 2120 memdev->region_index = 2+1; 2121 memdev->region_size = 0; 2122 memdev->region_offset = 0; 2123 memdev->address = 0; 2124 memdev->interleave_index = 0; 2125 memdev->interleave_ways = 1; 2126 offset += memdev->header.length; 2127 2128 /* mem-region13 (spa/dcr3, dimm3) */ 2129 memdev = nfit_buf + offset; 2130 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2131 memdev->header.length = sizeof(*memdev); 2132 memdev->device_handle = handle[3]; 2133 memdev->physical_id = 3; 2134 memdev->region_id = 0; 2135 memdev->range_index = 9+1; 2136 memdev->region_index = 3+1; 2137 memdev->region_size = 0; 2138 memdev->region_offset = 0; 2139 memdev->address = 0; 2140 memdev->interleave_index = 0; 2141 memdev->interleave_ways = 1; 2142 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 2143 offset += memdev->header.length; 2144 2145 /* dcr-descriptor0: blk */ 2146 dcr = nfit_buf + offset; 2147 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2148 dcr->header.length = sizeof(*dcr); 2149 dcr->region_index = 0+1; 2150 dcr_common_init(dcr); 2151 dcr->serial_number = ~handle[0]; 2152 dcr->code = NFIT_FIC_BLK; 2153 dcr->windows = 1; 2154 dcr->window_size = DCR_SIZE; 2155 dcr->command_offset = 0; 2156 dcr->command_size = 8; 2157 dcr->status_offset = 8; 2158 dcr->status_size = 4; 2159 offset += dcr->header.length; 2160 2161 /* dcr-descriptor1: blk */ 2162 dcr = nfit_buf + offset; 2163 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2164 dcr->header.length = sizeof(*dcr); 2165 dcr->region_index = 1+1; 2166 dcr_common_init(dcr); 2167 dcr->serial_number = ~handle[1]; 2168 dcr->code = NFIT_FIC_BLK; 2169 dcr->windows = 1; 2170 dcr->window_size = DCR_SIZE; 2171 dcr->command_offset = 0; 2172 dcr->command_size = 8; 2173 dcr->status_offset = 8; 2174 dcr->status_size = 4; 2175 offset += dcr->header.length; 2176 2177 /* dcr-descriptor2: blk */ 2178 dcr = nfit_buf + offset; 2179 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2180 dcr->header.length = sizeof(*dcr); 2181 dcr->region_index = 2+1; 2182 dcr_common_init(dcr); 2183 dcr->serial_number = ~handle[2]; 2184 dcr->code = NFIT_FIC_BLK; 2185 dcr->windows = 1; 2186 dcr->window_size = DCR_SIZE; 2187 dcr->command_offset = 0; 2188 dcr->command_size = 8; 2189 dcr->status_offset = 8; 2190 dcr->status_size = 4; 2191 offset += dcr->header.length; 2192 2193 /* dcr-descriptor3: blk */ 2194 dcr = nfit_buf + offset; 2195 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2196 dcr->header.length = sizeof(*dcr); 2197 dcr->region_index = 3+1; 2198 dcr_common_init(dcr); 2199 dcr->serial_number = ~handle[3]; 2200 dcr->code = NFIT_FIC_BLK; 2201 dcr->windows = 1; 2202 dcr->window_size = DCR_SIZE; 2203 dcr->command_offset = 0; 2204 dcr->command_size = 8; 2205 dcr->status_offset = 8; 2206 dcr->status_size = 4; 2207 offset += dcr->header.length; 2208 2209 /* dcr-descriptor0: pmem */ 2210 dcr = nfit_buf + offset; 2211 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2212 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2213 window_size); 2214 dcr->region_index = 4+1; 2215 dcr_common_init(dcr); 2216 dcr->serial_number = ~handle[0]; 2217 dcr->code = NFIT_FIC_BYTEN; 2218 dcr->windows = 0; 2219 offset += dcr->header.length; 2220 2221 /* dcr-descriptor1: pmem */ 2222 dcr = nfit_buf + offset; 2223 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2224 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2225 window_size); 2226 dcr->region_index = 5+1; 2227 dcr_common_init(dcr); 2228 dcr->serial_number = ~handle[1]; 2229 dcr->code = NFIT_FIC_BYTEN; 2230 dcr->windows = 0; 2231 offset += dcr->header.length; 2232 2233 /* dcr-descriptor2: pmem */ 2234 dcr = nfit_buf + offset; 2235 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2236 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2237 window_size); 2238 dcr->region_index = 6+1; 2239 dcr_common_init(dcr); 2240 dcr->serial_number = ~handle[2]; 2241 dcr->code = NFIT_FIC_BYTEN; 2242 dcr->windows = 0; 2243 offset += dcr->header.length; 2244 2245 /* dcr-descriptor3: pmem */ 2246 dcr = nfit_buf + offset; 2247 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2248 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2249 window_size); 2250 dcr->region_index = 7+1; 2251 dcr_common_init(dcr); 2252 dcr->serial_number = ~handle[3]; 2253 dcr->code = NFIT_FIC_BYTEN; 2254 dcr->windows = 0; 2255 offset += dcr->header.length; 2256 2257 /* bdw0 (spa/dcr0, dimm0) */ 2258 bdw = nfit_buf + offset; 2259 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 2260 bdw->header.length = sizeof(*bdw); 2261 bdw->region_index = 0+1; 2262 bdw->windows = 1; 2263 bdw->offset = 0; 2264 bdw->size = BDW_SIZE; 2265 bdw->capacity = DIMM_SIZE; 2266 bdw->start_address = 0; 2267 offset += bdw->header.length; 2268 2269 /* bdw1 (spa/dcr1, dimm1) */ 2270 bdw = nfit_buf + offset; 2271 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 2272 bdw->header.length = sizeof(*bdw); 2273 bdw->region_index = 1+1; 2274 bdw->windows = 1; 2275 bdw->offset = 0; 2276 bdw->size = BDW_SIZE; 2277 bdw->capacity = DIMM_SIZE; 2278 bdw->start_address = 0; 2279 offset += bdw->header.length; 2280 2281 /* bdw2 (spa/dcr2, dimm2) */ 2282 bdw = nfit_buf + offset; 2283 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 2284 bdw->header.length = sizeof(*bdw); 2285 bdw->region_index = 2+1; 2286 bdw->windows = 1; 2287 bdw->offset = 0; 2288 bdw->size = BDW_SIZE; 2289 bdw->capacity = DIMM_SIZE; 2290 bdw->start_address = 0; 2291 offset += bdw->header.length; 2292 2293 /* bdw3 (spa/dcr3, dimm3) */ 2294 bdw = nfit_buf + offset; 2295 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 2296 bdw->header.length = sizeof(*bdw); 2297 bdw->region_index = 3+1; 2298 bdw->windows = 1; 2299 bdw->offset = 0; 2300 bdw->size = BDW_SIZE; 2301 bdw->capacity = DIMM_SIZE; 2302 bdw->start_address = 0; 2303 offset += bdw->header.length; 2304 2305 /* flush0 (dimm0) */ 2306 flush = nfit_buf + offset; 2307 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2308 flush->header.length = flush_hint_size; 2309 flush->device_handle = handle[0]; 2310 flush->hint_count = NUM_HINTS; 2311 for (i = 0; i < NUM_HINTS; i++) 2312 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64); 2313 offset += flush->header.length; 2314 2315 /* flush1 (dimm1) */ 2316 flush = nfit_buf + offset; 2317 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2318 flush->header.length = flush_hint_size; 2319 flush->device_handle = handle[1]; 2320 flush->hint_count = NUM_HINTS; 2321 for (i = 0; i < NUM_HINTS; i++) 2322 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64); 2323 offset += flush->header.length; 2324 2325 /* flush2 (dimm2) */ 2326 flush = nfit_buf + offset; 2327 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2328 flush->header.length = flush_hint_size; 2329 flush->device_handle = handle[2]; 2330 flush->hint_count = NUM_HINTS; 2331 for (i = 0; i < NUM_HINTS; i++) 2332 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64); 2333 offset += flush->header.length; 2334 2335 /* flush3 (dimm3) */ 2336 flush = nfit_buf + offset; 2337 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2338 flush->header.length = flush_hint_size; 2339 flush->device_handle = handle[3]; 2340 flush->hint_count = NUM_HINTS; 2341 for (i = 0; i < NUM_HINTS; i++) 2342 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64); 2343 offset += flush->header.length; 2344 2345 /* platform capabilities */ 2346 pcap = nfit_buf + offset; 2347 pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES; 2348 pcap->header.length = sizeof(*pcap); 2349 pcap->highest_capability = 1; 2350 pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH; 2351 offset += pcap->header.length; 2352 2353 if (t->setup_hotplug) { 2354 /* dcr-descriptor4: blk */ 2355 dcr = nfit_buf + offset; 2356 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2357 dcr->header.length = sizeof(*dcr); 2358 dcr->region_index = 8+1; 2359 dcr_common_init(dcr); 2360 dcr->serial_number = ~handle[4]; 2361 dcr->code = NFIT_FIC_BLK; 2362 dcr->windows = 1; 2363 dcr->window_size = DCR_SIZE; 2364 dcr->command_offset = 0; 2365 dcr->command_size = 8; 2366 dcr->status_offset = 8; 2367 dcr->status_size = 4; 2368 offset += dcr->header.length; 2369 2370 /* dcr-descriptor4: pmem */ 2371 dcr = nfit_buf + offset; 2372 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2373 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2374 window_size); 2375 dcr->region_index = 9+1; 2376 dcr_common_init(dcr); 2377 dcr->serial_number = ~handle[4]; 2378 dcr->code = NFIT_FIC_BYTEN; 2379 dcr->windows = 0; 2380 offset += dcr->header.length; 2381 2382 /* bdw4 (spa/dcr4, dimm4) */ 2383 bdw = nfit_buf + offset; 2384 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 2385 bdw->header.length = sizeof(*bdw); 2386 bdw->region_index = 8+1; 2387 bdw->windows = 1; 2388 bdw->offset = 0; 2389 bdw->size = BDW_SIZE; 2390 bdw->capacity = DIMM_SIZE; 2391 bdw->start_address = 0; 2392 offset += bdw->header.length; 2393 2394 /* spa10 (dcr4) dimm4 */ 2395 spa = nfit_buf + offset; 2396 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2397 spa->header.length = sizeof(*spa); 2398 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 2399 spa->range_index = 10+1; 2400 spa->address = t->dcr_dma[4]; 2401 spa->length = DCR_SIZE; 2402 offset += spa->header.length; 2403 2404 /* 2405 * spa11 (single-dimm interleave for hotplug, note storage 2406 * does not actually alias the related block-data-window 2407 * regions) 2408 */ 2409 spa = nfit_buf + offset; 2410 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2411 spa->header.length = sizeof(*spa); 2412 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 2413 spa->range_index = 11+1; 2414 spa->address = t->spa_set_dma[2]; 2415 spa->length = SPA0_SIZE; 2416 offset += spa->header.length; 2417 2418 /* spa12 (bdw for dcr4) dimm4 */ 2419 spa = nfit_buf + offset; 2420 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2421 spa->header.length = sizeof(*spa); 2422 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 2423 spa->range_index = 12+1; 2424 spa->address = t->dimm_dma[4]; 2425 spa->length = DIMM_SIZE; 2426 offset += spa->header.length; 2427 2428 /* mem-region14 (spa/dcr4, dimm4) */ 2429 memdev = nfit_buf + offset; 2430 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2431 memdev->header.length = sizeof(*memdev); 2432 memdev->device_handle = handle[4]; 2433 memdev->physical_id = 4; 2434 memdev->region_id = 0; 2435 memdev->range_index = 10+1; 2436 memdev->region_index = 8+1; 2437 memdev->region_size = 0; 2438 memdev->region_offset = 0; 2439 memdev->address = 0; 2440 memdev->interleave_index = 0; 2441 memdev->interleave_ways = 1; 2442 offset += memdev->header.length; 2443 2444 /* mem-region15 (spa11, dimm4) */ 2445 memdev = nfit_buf + offset; 2446 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2447 memdev->header.length = sizeof(*memdev); 2448 memdev->device_handle = handle[4]; 2449 memdev->physical_id = 4; 2450 memdev->region_id = 0; 2451 memdev->range_index = 11+1; 2452 memdev->region_index = 9+1; 2453 memdev->region_size = SPA0_SIZE; 2454 memdev->region_offset = (1ULL << 48); 2455 memdev->address = 0; 2456 memdev->interleave_index = 0; 2457 memdev->interleave_ways = 1; 2458 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 2459 offset += memdev->header.length; 2460 2461 /* mem-region16 (spa/bdw4, dimm4) */ 2462 memdev = nfit_buf + offset; 2463 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2464 memdev->header.length = sizeof(*memdev); 2465 memdev->device_handle = handle[4]; 2466 memdev->physical_id = 4; 2467 memdev->region_id = 0; 2468 memdev->range_index = 12+1; 2469 memdev->region_index = 8+1; 2470 memdev->region_size = 0; 2471 memdev->region_offset = 0; 2472 memdev->address = 0; 2473 memdev->interleave_index = 0; 2474 memdev->interleave_ways = 1; 2475 offset += memdev->header.length; 2476 2477 /* flush3 (dimm4) */ 2478 flush = nfit_buf + offset; 2479 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2480 flush->header.length = flush_hint_size; 2481 flush->device_handle = handle[4]; 2482 flush->hint_count = NUM_HINTS; 2483 for (i = 0; i < NUM_HINTS; i++) 2484 flush->hint_address[i] = t->flush_dma[4] 2485 + i * sizeof(u64); 2486 offset += flush->header.length; 2487 2488 /* sanity check to make sure we've filled the buffer */ 2489 WARN_ON(offset != t->nfit_size); 2490 } 2491 2492 t->nfit_filled = offset; 2493 2494 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0], 2495 SPA0_SIZE); 2496 2497 acpi_desc = &t->acpi_desc; 2498 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en); 2499 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2500 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2501 set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en); 2502 set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en); 2503 set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en); 2504 set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en); 2505 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en); 2506 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en); 2507 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en); 2508 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en); 2509 set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en); 2510 set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_nfit_cmd_force_en); 2511 set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_nfit_cmd_force_en); 2512 set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_nfit_cmd_force_en); 2513 set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_nfit_cmd_force_en); 2514 set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en); 2515 set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en); 2516 set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en); 2517 set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en); 2518 set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en); 2519 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en); 2520 set_bit(NVDIMM_INTEL_GET_SECURITY_STATE, 2521 &acpi_desc->dimm_cmd_force_en); 2522 set_bit(NVDIMM_INTEL_SET_PASSPHRASE, &acpi_desc->dimm_cmd_force_en); 2523 set_bit(NVDIMM_INTEL_DISABLE_PASSPHRASE, 2524 &acpi_desc->dimm_cmd_force_en); 2525 set_bit(NVDIMM_INTEL_UNLOCK_UNIT, &acpi_desc->dimm_cmd_force_en); 2526 set_bit(NVDIMM_INTEL_FREEZE_LOCK, &acpi_desc->dimm_cmd_force_en); 2527 set_bit(NVDIMM_INTEL_SECURE_ERASE, &acpi_desc->dimm_cmd_force_en); 2528 set_bit(NVDIMM_INTEL_OVERWRITE, &acpi_desc->dimm_cmd_force_en); 2529 set_bit(NVDIMM_INTEL_QUERY_OVERWRITE, &acpi_desc->dimm_cmd_force_en); 2530 set_bit(NVDIMM_INTEL_SET_MASTER_PASSPHRASE, 2531 &acpi_desc->dimm_cmd_force_en); 2532 set_bit(NVDIMM_INTEL_MASTER_SECURE_ERASE, 2533 &acpi_desc->dimm_cmd_force_en); 2534 } 2535 2536 static void nfit_test1_setup(struct nfit_test *t) 2537 { 2538 size_t offset; 2539 void *nfit_buf = t->nfit_buf; 2540 struct acpi_nfit_memory_map *memdev; 2541 struct acpi_nfit_control_region *dcr; 2542 struct acpi_nfit_system_address *spa; 2543 struct acpi_nfit_desc *acpi_desc; 2544 2545 offset = 0; 2546 /* spa0 (flat range with no bdw aliasing) */ 2547 spa = nfit_buf + offset; 2548 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2549 spa->header.length = sizeof(*spa); 2550 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 2551 spa->range_index = 0+1; 2552 spa->address = t->spa_set_dma[0]; 2553 spa->length = SPA2_SIZE; 2554 offset += spa->header.length; 2555 2556 /* virtual cd region */ 2557 spa = nfit_buf + offset; 2558 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2559 spa->header.length = sizeof(*spa); 2560 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16); 2561 spa->range_index = 0; 2562 spa->address = t->spa_set_dma[1]; 2563 spa->length = SPA_VCD_SIZE; 2564 offset += spa->header.length; 2565 2566 /* mem-region0 (spa0, dimm0) */ 2567 memdev = nfit_buf + offset; 2568 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2569 memdev->header.length = sizeof(*memdev); 2570 memdev->device_handle = handle[5]; 2571 memdev->physical_id = 0; 2572 memdev->region_id = 0; 2573 memdev->range_index = 0+1; 2574 memdev->region_index = 0+1; 2575 memdev->region_size = SPA2_SIZE; 2576 memdev->region_offset = 0; 2577 memdev->address = 0; 2578 memdev->interleave_index = 0; 2579 memdev->interleave_ways = 1; 2580 memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED 2581 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED 2582 | ACPI_NFIT_MEM_NOT_ARMED; 2583 offset += memdev->header.length; 2584 2585 /* dcr-descriptor0 */ 2586 dcr = nfit_buf + offset; 2587 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2588 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2589 window_size); 2590 dcr->region_index = 0+1; 2591 dcr_common_init(dcr); 2592 dcr->serial_number = ~handle[5]; 2593 dcr->code = NFIT_FIC_BYTE; 2594 dcr->windows = 0; 2595 offset += dcr->header.length; 2596 2597 memdev = nfit_buf + offset; 2598 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2599 memdev->header.length = sizeof(*memdev); 2600 memdev->device_handle = handle[6]; 2601 memdev->physical_id = 0; 2602 memdev->region_id = 0; 2603 memdev->range_index = 0; 2604 memdev->region_index = 0+2; 2605 memdev->region_size = SPA2_SIZE; 2606 memdev->region_offset = 0; 2607 memdev->address = 0; 2608 memdev->interleave_index = 0; 2609 memdev->interleave_ways = 1; 2610 memdev->flags = ACPI_NFIT_MEM_MAP_FAILED; 2611 offset += memdev->header.length; 2612 2613 /* dcr-descriptor1 */ 2614 dcr = nfit_buf + offset; 2615 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2616 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2617 window_size); 2618 dcr->region_index = 0+2; 2619 dcr_common_init(dcr); 2620 dcr->serial_number = ~handle[6]; 2621 dcr->code = NFIT_FIC_BYTE; 2622 dcr->windows = 0; 2623 offset += dcr->header.length; 2624 2625 /* sanity check to make sure we've filled the buffer */ 2626 WARN_ON(offset != t->nfit_size); 2627 2628 t->nfit_filled = offset; 2629 2630 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0], 2631 SPA2_SIZE); 2632 2633 acpi_desc = &t->acpi_desc; 2634 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en); 2635 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en); 2636 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en); 2637 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en); 2638 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en); 2639 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en); 2640 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2641 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2642 } 2643 2644 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa, 2645 void *iobuf, u64 len, int rw) 2646 { 2647 struct nfit_blk *nfit_blk = ndbr->blk_provider_data; 2648 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW]; 2649 struct nd_region *nd_region = &ndbr->nd_region; 2650 unsigned int lane; 2651 2652 lane = nd_region_acquire_lane(nd_region); 2653 if (rw) 2654 memcpy(mmio->addr.base + dpa, iobuf, len); 2655 else { 2656 memcpy(iobuf, mmio->addr.base + dpa, len); 2657 2658 /* give us some some coverage of the arch_invalidate_pmem() API */ 2659 arch_invalidate_pmem(mmio->addr.base + dpa, len); 2660 } 2661 nd_region_release_lane(nd_region, lane); 2662 2663 return 0; 2664 } 2665 2666 static unsigned long nfit_ctl_handle; 2667 2668 union acpi_object *result; 2669 2670 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle, 2671 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4) 2672 { 2673 if (handle != &nfit_ctl_handle) 2674 return ERR_PTR(-ENXIO); 2675 2676 return result; 2677 } 2678 2679 static int setup_result(void *buf, size_t size) 2680 { 2681 result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL); 2682 if (!result) 2683 return -ENOMEM; 2684 result->package.type = ACPI_TYPE_BUFFER, 2685 result->buffer.pointer = (void *) (result + 1); 2686 result->buffer.length = size; 2687 memcpy(result->buffer.pointer, buf, size); 2688 memset(buf, 0, size); 2689 return 0; 2690 } 2691 2692 static int nfit_ctl_test(struct device *dev) 2693 { 2694 int rc, cmd_rc; 2695 struct nvdimm *nvdimm; 2696 struct acpi_device *adev; 2697 struct nfit_mem *nfit_mem; 2698 struct nd_ars_record *record; 2699 struct acpi_nfit_desc *acpi_desc; 2700 const u64 test_val = 0x0123456789abcdefULL; 2701 unsigned long mask, cmd_size, offset; 2702 union { 2703 struct nd_cmd_get_config_size cfg_size; 2704 struct nd_cmd_clear_error clear_err; 2705 struct nd_cmd_ars_status ars_stat; 2706 struct nd_cmd_ars_cap ars_cap; 2707 char buf[sizeof(struct nd_cmd_ars_status) 2708 + sizeof(struct nd_ars_record)]; 2709 } cmds; 2710 2711 adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL); 2712 if (!adev) 2713 return -ENOMEM; 2714 *adev = (struct acpi_device) { 2715 .handle = &nfit_ctl_handle, 2716 .dev = { 2717 .init_name = "test-adev", 2718 }, 2719 }; 2720 2721 acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL); 2722 if (!acpi_desc) 2723 return -ENOMEM; 2724 *acpi_desc = (struct acpi_nfit_desc) { 2725 .nd_desc = { 2726 .cmd_mask = 1UL << ND_CMD_ARS_CAP 2727 | 1UL << ND_CMD_ARS_START 2728 | 1UL << ND_CMD_ARS_STATUS 2729 | 1UL << ND_CMD_CLEAR_ERROR 2730 | 1UL << ND_CMD_CALL, 2731 .module = THIS_MODULE, 2732 .provider_name = "ACPI.NFIT", 2733 .ndctl = acpi_nfit_ctl, 2734 .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA 2735 | 1UL << NFIT_CMD_ARS_INJECT_SET 2736 | 1UL << NFIT_CMD_ARS_INJECT_CLEAR 2737 | 1UL << NFIT_CMD_ARS_INJECT_GET, 2738 }, 2739 .dev = &adev->dev, 2740 }; 2741 2742 nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL); 2743 if (!nfit_mem) 2744 return -ENOMEM; 2745 2746 mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD 2747 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE 2748 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA 2749 | 1UL << ND_CMD_VENDOR; 2750 *nfit_mem = (struct nfit_mem) { 2751 .adev = adev, 2752 .family = NVDIMM_FAMILY_INTEL, 2753 .dsm_mask = mask, 2754 }; 2755 2756 nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL); 2757 if (!nvdimm) 2758 return -ENOMEM; 2759 *nvdimm = (struct nvdimm) { 2760 .provider_data = nfit_mem, 2761 .cmd_mask = mask, 2762 .dev = { 2763 .init_name = "test-dimm", 2764 }, 2765 }; 2766 2767 2768 /* basic checkout of a typical 'get config size' command */ 2769 cmd_size = sizeof(cmds.cfg_size); 2770 cmds.cfg_size = (struct nd_cmd_get_config_size) { 2771 .status = 0, 2772 .config_size = SZ_128K, 2773 .max_xfer = SZ_4K, 2774 }; 2775 rc = setup_result(cmds.buf, cmd_size); 2776 if (rc) 2777 return rc; 2778 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE, 2779 cmds.buf, cmd_size, &cmd_rc); 2780 2781 if (rc < 0 || cmd_rc || cmds.cfg_size.status != 0 2782 || cmds.cfg_size.config_size != SZ_128K 2783 || cmds.cfg_size.max_xfer != SZ_4K) { 2784 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2785 __func__, __LINE__, rc, cmd_rc); 2786 return -EIO; 2787 } 2788 2789 2790 /* test ars_status with zero output */ 2791 cmd_size = offsetof(struct nd_cmd_ars_status, address); 2792 cmds.ars_stat = (struct nd_cmd_ars_status) { 2793 .out_length = 0, 2794 }; 2795 rc = setup_result(cmds.buf, cmd_size); 2796 if (rc) 2797 return rc; 2798 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2799 cmds.buf, cmd_size, &cmd_rc); 2800 2801 if (rc < 0 || cmd_rc) { 2802 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2803 __func__, __LINE__, rc, cmd_rc); 2804 return -EIO; 2805 } 2806 2807 2808 /* test ars_cap with benign extended status */ 2809 cmd_size = sizeof(cmds.ars_cap); 2810 cmds.ars_cap = (struct nd_cmd_ars_cap) { 2811 .status = ND_ARS_PERSISTENT << 16, 2812 }; 2813 offset = offsetof(struct nd_cmd_ars_cap, status); 2814 rc = setup_result(cmds.buf + offset, cmd_size - offset); 2815 if (rc) 2816 return rc; 2817 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP, 2818 cmds.buf, cmd_size, &cmd_rc); 2819 2820 if (rc < 0 || cmd_rc) { 2821 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2822 __func__, __LINE__, rc, cmd_rc); 2823 return -EIO; 2824 } 2825 2826 2827 /* test ars_status with 'status' trimmed from 'out_length' */ 2828 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record); 2829 cmds.ars_stat = (struct nd_cmd_ars_status) { 2830 .out_length = cmd_size - 4, 2831 }; 2832 record = &cmds.ars_stat.records[0]; 2833 *record = (struct nd_ars_record) { 2834 .length = test_val, 2835 }; 2836 rc = setup_result(cmds.buf, cmd_size); 2837 if (rc) 2838 return rc; 2839 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2840 cmds.buf, cmd_size, &cmd_rc); 2841 2842 if (rc < 0 || cmd_rc || record->length != test_val) { 2843 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2844 __func__, __LINE__, rc, cmd_rc); 2845 return -EIO; 2846 } 2847 2848 2849 /* test ars_status with 'Output (Size)' including 'status' */ 2850 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record); 2851 cmds.ars_stat = (struct nd_cmd_ars_status) { 2852 .out_length = cmd_size, 2853 }; 2854 record = &cmds.ars_stat.records[0]; 2855 *record = (struct nd_ars_record) { 2856 .length = test_val, 2857 }; 2858 rc = setup_result(cmds.buf, cmd_size); 2859 if (rc) 2860 return rc; 2861 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2862 cmds.buf, cmd_size, &cmd_rc); 2863 2864 if (rc < 0 || cmd_rc || record->length != test_val) { 2865 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2866 __func__, __LINE__, rc, cmd_rc); 2867 return -EIO; 2868 } 2869 2870 2871 /* test extended status for get_config_size results in failure */ 2872 cmd_size = sizeof(cmds.cfg_size); 2873 cmds.cfg_size = (struct nd_cmd_get_config_size) { 2874 .status = 1 << 16, 2875 }; 2876 rc = setup_result(cmds.buf, cmd_size); 2877 if (rc) 2878 return rc; 2879 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE, 2880 cmds.buf, cmd_size, &cmd_rc); 2881 2882 if (rc < 0 || cmd_rc >= 0) { 2883 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2884 __func__, __LINE__, rc, cmd_rc); 2885 return -EIO; 2886 } 2887 2888 /* test clear error */ 2889 cmd_size = sizeof(cmds.clear_err); 2890 cmds.clear_err = (struct nd_cmd_clear_error) { 2891 .length = 512, 2892 .cleared = 512, 2893 }; 2894 rc = setup_result(cmds.buf, cmd_size); 2895 if (rc) 2896 return rc; 2897 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR, 2898 cmds.buf, cmd_size, &cmd_rc); 2899 if (rc < 0 || cmd_rc) { 2900 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2901 __func__, __LINE__, rc, cmd_rc); 2902 return -EIO; 2903 } 2904 2905 return 0; 2906 } 2907 2908 static int nfit_test_probe(struct platform_device *pdev) 2909 { 2910 struct nvdimm_bus_descriptor *nd_desc; 2911 struct acpi_nfit_desc *acpi_desc; 2912 struct device *dev = &pdev->dev; 2913 struct nfit_test *nfit_test; 2914 struct nfit_mem *nfit_mem; 2915 union acpi_object *obj; 2916 int rc; 2917 2918 if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) { 2919 rc = nfit_ctl_test(&pdev->dev); 2920 if (rc) 2921 return rc; 2922 } 2923 2924 nfit_test = to_nfit_test(&pdev->dev); 2925 2926 /* common alloc */ 2927 if (nfit_test->num_dcr) { 2928 int num = nfit_test->num_dcr; 2929 2930 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *), 2931 GFP_KERNEL); 2932 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t), 2933 GFP_KERNEL); 2934 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *), 2935 GFP_KERNEL); 2936 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t), 2937 GFP_KERNEL); 2938 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *), 2939 GFP_KERNEL); 2940 nfit_test->label_dma = devm_kcalloc(dev, num, 2941 sizeof(dma_addr_t), GFP_KERNEL); 2942 nfit_test->dcr = devm_kcalloc(dev, num, 2943 sizeof(struct nfit_test_dcr *), GFP_KERNEL); 2944 nfit_test->dcr_dma = devm_kcalloc(dev, num, 2945 sizeof(dma_addr_t), GFP_KERNEL); 2946 nfit_test->smart = devm_kcalloc(dev, num, 2947 sizeof(struct nd_intel_smart), GFP_KERNEL); 2948 nfit_test->smart_threshold = devm_kcalloc(dev, num, 2949 sizeof(struct nd_intel_smart_threshold), 2950 GFP_KERNEL); 2951 nfit_test->fw = devm_kcalloc(dev, num, 2952 sizeof(struct nfit_test_fw), GFP_KERNEL); 2953 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label 2954 && nfit_test->label_dma && nfit_test->dcr 2955 && nfit_test->dcr_dma && nfit_test->flush 2956 && nfit_test->flush_dma 2957 && nfit_test->fw) 2958 /* pass */; 2959 else 2960 return -ENOMEM; 2961 } 2962 2963 if (nfit_test->num_pm) { 2964 int num = nfit_test->num_pm; 2965 2966 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *), 2967 GFP_KERNEL); 2968 nfit_test->spa_set_dma = devm_kcalloc(dev, num, 2969 sizeof(dma_addr_t), GFP_KERNEL); 2970 if (nfit_test->spa_set && nfit_test->spa_set_dma) 2971 /* pass */; 2972 else 2973 return -ENOMEM; 2974 } 2975 2976 /* per-nfit specific alloc */ 2977 if (nfit_test->alloc(nfit_test)) 2978 return -ENOMEM; 2979 2980 nfit_test->setup(nfit_test); 2981 acpi_desc = &nfit_test->acpi_desc; 2982 acpi_nfit_desc_init(acpi_desc, &pdev->dev); 2983 acpi_desc->blk_do_io = nfit_test_blk_do_io; 2984 nd_desc = &acpi_desc->nd_desc; 2985 nd_desc->provider_name = NULL; 2986 nd_desc->module = THIS_MODULE; 2987 nd_desc->ndctl = nfit_test_ctl; 2988 2989 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf, 2990 nfit_test->nfit_filled); 2991 if (rc) 2992 return rc; 2993 2994 rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc); 2995 if (rc) 2996 return rc; 2997 2998 if (nfit_test->setup != nfit_test0_setup) 2999 return 0; 3000 3001 nfit_test->setup_hotplug = 1; 3002 nfit_test->setup(nfit_test); 3003 3004 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 3005 if (!obj) 3006 return -ENOMEM; 3007 obj->type = ACPI_TYPE_BUFFER; 3008 obj->buffer.length = nfit_test->nfit_size; 3009 obj->buffer.pointer = nfit_test->nfit_buf; 3010 *(nfit_test->_fit) = obj; 3011 __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80); 3012 3013 /* associate dimm devices with nfit_mem data for notification testing */ 3014 mutex_lock(&acpi_desc->init_mutex); 3015 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) { 3016 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle; 3017 int i; 3018 3019 for (i = 0; i < ARRAY_SIZE(handle); i++) 3020 if (nfit_handle == handle[i]) 3021 dev_set_drvdata(nfit_test->dimm_dev[i], 3022 nfit_mem); 3023 } 3024 mutex_unlock(&acpi_desc->init_mutex); 3025 3026 return 0; 3027 } 3028 3029 static int nfit_test_remove(struct platform_device *pdev) 3030 { 3031 return 0; 3032 } 3033 3034 static void nfit_test_release(struct device *dev) 3035 { 3036 struct nfit_test *nfit_test = to_nfit_test(dev); 3037 3038 kfree(nfit_test); 3039 } 3040 3041 static const struct platform_device_id nfit_test_id[] = { 3042 { KBUILD_MODNAME }, 3043 { }, 3044 }; 3045 3046 static struct platform_driver nfit_test_driver = { 3047 .probe = nfit_test_probe, 3048 .remove = nfit_test_remove, 3049 .driver = { 3050 .name = KBUILD_MODNAME, 3051 }, 3052 .id_table = nfit_test_id, 3053 }; 3054 3055 static char mcsafe_buf[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE))); 3056 3057 enum INJECT { 3058 INJECT_NONE, 3059 INJECT_SRC, 3060 INJECT_DST, 3061 }; 3062 3063 static void mcsafe_test_init(char *dst, char *src, size_t size) 3064 { 3065 size_t i; 3066 3067 memset(dst, 0xff, size); 3068 for (i = 0; i < size; i++) 3069 src[i] = (char) i; 3070 } 3071 3072 static bool mcsafe_test_validate(unsigned char *dst, unsigned char *src, 3073 size_t size, unsigned long rem) 3074 { 3075 size_t i; 3076 3077 for (i = 0; i < size - rem; i++) 3078 if (dst[i] != (unsigned char) i) { 3079 pr_info_once("%s:%d: offset: %zd got: %#x expect: %#x\n", 3080 __func__, __LINE__, i, dst[i], 3081 (unsigned char) i); 3082 return false; 3083 } 3084 for (i = size - rem; i < size; i++) 3085 if (dst[i] != 0xffU) { 3086 pr_info_once("%s:%d: offset: %zd got: %#x expect: 0xff\n", 3087 __func__, __LINE__, i, dst[i]); 3088 return false; 3089 } 3090 return true; 3091 } 3092 3093 void mcsafe_test(void) 3094 { 3095 char *inject_desc[] = { "none", "source", "destination" }; 3096 enum INJECT inj; 3097 3098 if (IS_ENABLED(CONFIG_MCSAFE_TEST)) { 3099 pr_info("%s: run...\n", __func__); 3100 } else { 3101 pr_info("%s: disabled, skip.\n", __func__); 3102 return; 3103 } 3104 3105 for (inj = INJECT_NONE; inj <= INJECT_DST; inj++) { 3106 int i; 3107 3108 pr_info("%s: inject: %s\n", __func__, inject_desc[inj]); 3109 for (i = 0; i < 512; i++) { 3110 unsigned long expect, rem; 3111 void *src, *dst; 3112 bool valid; 3113 3114 switch (inj) { 3115 case INJECT_NONE: 3116 mcsafe_inject_src(NULL); 3117 mcsafe_inject_dst(NULL); 3118 dst = &mcsafe_buf[2048]; 3119 src = &mcsafe_buf[1024 - i]; 3120 expect = 0; 3121 break; 3122 case INJECT_SRC: 3123 mcsafe_inject_src(&mcsafe_buf[1024]); 3124 mcsafe_inject_dst(NULL); 3125 dst = &mcsafe_buf[2048]; 3126 src = &mcsafe_buf[1024 - i]; 3127 expect = 512 - i; 3128 break; 3129 case INJECT_DST: 3130 mcsafe_inject_src(NULL); 3131 mcsafe_inject_dst(&mcsafe_buf[2048]); 3132 dst = &mcsafe_buf[2048 - i]; 3133 src = &mcsafe_buf[1024]; 3134 expect = 512 - i; 3135 break; 3136 } 3137 3138 mcsafe_test_init(dst, src, 512); 3139 rem = __memcpy_mcsafe(dst, src, 512); 3140 valid = mcsafe_test_validate(dst, src, 512, expect); 3141 if (rem == expect && valid) 3142 continue; 3143 pr_info("%s: copy(%#lx, %#lx, %d) off: %d rem: %ld %s expect: %ld\n", 3144 __func__, 3145 ((unsigned long) dst) & ~PAGE_MASK, 3146 ((unsigned long ) src) & ~PAGE_MASK, 3147 512, i, rem, valid ? "valid" : "bad", 3148 expect); 3149 } 3150 } 3151 3152 mcsafe_inject_src(NULL); 3153 mcsafe_inject_dst(NULL); 3154 } 3155 3156 static __init int nfit_test_init(void) 3157 { 3158 int rc, i; 3159 3160 pmem_test(); 3161 libnvdimm_test(); 3162 acpi_nfit_test(); 3163 device_dax_test(); 3164 mcsafe_test(); 3165 3166 nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm); 3167 3168 nfit_wq = create_singlethread_workqueue("nfit"); 3169 if (!nfit_wq) 3170 return -ENOMEM; 3171 3172 nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm"); 3173 if (IS_ERR(nfit_test_dimm)) { 3174 rc = PTR_ERR(nfit_test_dimm); 3175 goto err_register; 3176 } 3177 3178 nfit_pool = gen_pool_create(ilog2(SZ_4M), NUMA_NO_NODE); 3179 if (!nfit_pool) { 3180 rc = -ENOMEM; 3181 goto err_register; 3182 } 3183 3184 if (gen_pool_add(nfit_pool, SZ_4G, SZ_4G, NUMA_NO_NODE)) { 3185 rc = -ENOMEM; 3186 goto err_register; 3187 } 3188 3189 for (i = 0; i < NUM_NFITS; i++) { 3190 struct nfit_test *nfit_test; 3191 struct platform_device *pdev; 3192 3193 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL); 3194 if (!nfit_test) { 3195 rc = -ENOMEM; 3196 goto err_register; 3197 } 3198 INIT_LIST_HEAD(&nfit_test->resources); 3199 badrange_init(&nfit_test->badrange); 3200 switch (i) { 3201 case 0: 3202 nfit_test->num_pm = NUM_PM; 3203 nfit_test->dcr_idx = 0; 3204 nfit_test->num_dcr = NUM_DCR; 3205 nfit_test->alloc = nfit_test0_alloc; 3206 nfit_test->setup = nfit_test0_setup; 3207 break; 3208 case 1: 3209 nfit_test->num_pm = 2; 3210 nfit_test->dcr_idx = NUM_DCR; 3211 nfit_test->num_dcr = 2; 3212 nfit_test->alloc = nfit_test1_alloc; 3213 nfit_test->setup = nfit_test1_setup; 3214 break; 3215 default: 3216 rc = -EINVAL; 3217 goto err_register; 3218 } 3219 pdev = &nfit_test->pdev; 3220 pdev->name = KBUILD_MODNAME; 3221 pdev->id = i; 3222 pdev->dev.release = nfit_test_release; 3223 rc = platform_device_register(pdev); 3224 if (rc) { 3225 put_device(&pdev->dev); 3226 goto err_register; 3227 } 3228 get_device(&pdev->dev); 3229 3230 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3231 if (rc) 3232 goto err_register; 3233 3234 instances[i] = nfit_test; 3235 INIT_WORK(&nfit_test->work, uc_error_notify); 3236 } 3237 3238 rc = platform_driver_register(&nfit_test_driver); 3239 if (rc) 3240 goto err_register; 3241 return 0; 3242 3243 err_register: 3244 if (nfit_pool) 3245 gen_pool_destroy(nfit_pool); 3246 3247 destroy_workqueue(nfit_wq); 3248 for (i = 0; i < NUM_NFITS; i++) 3249 if (instances[i]) 3250 platform_device_unregister(&instances[i]->pdev); 3251 nfit_test_teardown(); 3252 for (i = 0; i < NUM_NFITS; i++) 3253 if (instances[i]) 3254 put_device(&instances[i]->pdev.dev); 3255 3256 return rc; 3257 } 3258 3259 static __exit void nfit_test_exit(void) 3260 { 3261 int i; 3262 3263 flush_workqueue(nfit_wq); 3264 destroy_workqueue(nfit_wq); 3265 for (i = 0; i < NUM_NFITS; i++) 3266 platform_device_unregister(&instances[i]->pdev); 3267 platform_driver_unregister(&nfit_test_driver); 3268 nfit_test_teardown(); 3269 3270 gen_pool_destroy(nfit_pool); 3271 3272 for (i = 0; i < NUM_NFITS; i++) 3273 put_device(&instances[i]->pdev.dev); 3274 class_destroy(nfit_test_dimm); 3275 } 3276 3277 module_init(nfit_test_init); 3278 module_exit(nfit_test_exit); 3279 MODULE_LICENSE("GPL v2"); 3280 MODULE_AUTHOR("Intel Corporation"); 3281