1 // SPDX-License-Identifier: GPL-2.0 2 #include <errno.h> 3 #include <string.h> 4 #include "perf_regs.h" 5 #include "util/sample.h" 6 7 int __weak arch_sdt_arg_parse_op(char *old_op __maybe_unused, 8 char **new_op __maybe_unused) 9 { 10 return SDT_ARG_SKIP; 11 } 12 13 uint64_t __weak arch__intr_reg_mask(void) 14 { 15 return PERF_REGS_MASK; 16 } 17 18 uint64_t __weak arch__user_reg_mask(void) 19 { 20 return PERF_REGS_MASK; 21 } 22 23 #ifdef HAVE_PERF_REGS_SUPPORT 24 25 #define perf_event_arm_regs perf_event_arm64_regs 26 #include "../../arch/arm64/include/uapi/asm/perf_regs.h" 27 #undef perf_event_arm_regs 28 29 #include "../../arch/arm/include/uapi/asm/perf_regs.h" 30 #include "../../arch/csky/include/uapi/asm/perf_regs.h" 31 #include "../../arch/loongarch/include/uapi/asm/perf_regs.h" 32 #include "../../arch/mips/include/uapi/asm/perf_regs.h" 33 #include "../../arch/powerpc/include/uapi/asm/perf_regs.h" 34 #include "../../arch/riscv/include/uapi/asm/perf_regs.h" 35 #include "../../arch/s390/include/uapi/asm/perf_regs.h" 36 #include "../../arch/x86/include/uapi/asm/perf_regs.h" 37 38 static const char *__perf_reg_name_arm64(int id) 39 { 40 switch (id) { 41 case PERF_REG_ARM64_X0: 42 return "x0"; 43 case PERF_REG_ARM64_X1: 44 return "x1"; 45 case PERF_REG_ARM64_X2: 46 return "x2"; 47 case PERF_REG_ARM64_X3: 48 return "x3"; 49 case PERF_REG_ARM64_X4: 50 return "x4"; 51 case PERF_REG_ARM64_X5: 52 return "x5"; 53 case PERF_REG_ARM64_X6: 54 return "x6"; 55 case PERF_REG_ARM64_X7: 56 return "x7"; 57 case PERF_REG_ARM64_X8: 58 return "x8"; 59 case PERF_REG_ARM64_X9: 60 return "x9"; 61 case PERF_REG_ARM64_X10: 62 return "x10"; 63 case PERF_REG_ARM64_X11: 64 return "x11"; 65 case PERF_REG_ARM64_X12: 66 return "x12"; 67 case PERF_REG_ARM64_X13: 68 return "x13"; 69 case PERF_REG_ARM64_X14: 70 return "x14"; 71 case PERF_REG_ARM64_X15: 72 return "x15"; 73 case PERF_REG_ARM64_X16: 74 return "x16"; 75 case PERF_REG_ARM64_X17: 76 return "x17"; 77 case PERF_REG_ARM64_X18: 78 return "x18"; 79 case PERF_REG_ARM64_X19: 80 return "x19"; 81 case PERF_REG_ARM64_X20: 82 return "x20"; 83 case PERF_REG_ARM64_X21: 84 return "x21"; 85 case PERF_REG_ARM64_X22: 86 return "x22"; 87 case PERF_REG_ARM64_X23: 88 return "x23"; 89 case PERF_REG_ARM64_X24: 90 return "x24"; 91 case PERF_REG_ARM64_X25: 92 return "x25"; 93 case PERF_REG_ARM64_X26: 94 return "x26"; 95 case PERF_REG_ARM64_X27: 96 return "x27"; 97 case PERF_REG_ARM64_X28: 98 return "x28"; 99 case PERF_REG_ARM64_X29: 100 return "x29"; 101 case PERF_REG_ARM64_SP: 102 return "sp"; 103 case PERF_REG_ARM64_LR: 104 return "lr"; 105 case PERF_REG_ARM64_PC: 106 return "pc"; 107 case PERF_REG_ARM64_VG: 108 return "vg"; 109 default: 110 return NULL; 111 } 112 113 return NULL; 114 } 115 116 static const char *__perf_reg_name_arm(int id) 117 { 118 switch (id) { 119 case PERF_REG_ARM_R0: 120 return "r0"; 121 case PERF_REG_ARM_R1: 122 return "r1"; 123 case PERF_REG_ARM_R2: 124 return "r2"; 125 case PERF_REG_ARM_R3: 126 return "r3"; 127 case PERF_REG_ARM_R4: 128 return "r4"; 129 case PERF_REG_ARM_R5: 130 return "r5"; 131 case PERF_REG_ARM_R6: 132 return "r6"; 133 case PERF_REG_ARM_R7: 134 return "r7"; 135 case PERF_REG_ARM_R8: 136 return "r8"; 137 case PERF_REG_ARM_R9: 138 return "r9"; 139 case PERF_REG_ARM_R10: 140 return "r10"; 141 case PERF_REG_ARM_FP: 142 return "fp"; 143 case PERF_REG_ARM_IP: 144 return "ip"; 145 case PERF_REG_ARM_SP: 146 return "sp"; 147 case PERF_REG_ARM_LR: 148 return "lr"; 149 case PERF_REG_ARM_PC: 150 return "pc"; 151 default: 152 return NULL; 153 } 154 155 return NULL; 156 } 157 158 static const char *__perf_reg_name_csky(int id) 159 { 160 switch (id) { 161 case PERF_REG_CSKY_A0: 162 return "a0"; 163 case PERF_REG_CSKY_A1: 164 return "a1"; 165 case PERF_REG_CSKY_A2: 166 return "a2"; 167 case PERF_REG_CSKY_A3: 168 return "a3"; 169 case PERF_REG_CSKY_REGS0: 170 return "regs0"; 171 case PERF_REG_CSKY_REGS1: 172 return "regs1"; 173 case PERF_REG_CSKY_REGS2: 174 return "regs2"; 175 case PERF_REG_CSKY_REGS3: 176 return "regs3"; 177 case PERF_REG_CSKY_REGS4: 178 return "regs4"; 179 case PERF_REG_CSKY_REGS5: 180 return "regs5"; 181 case PERF_REG_CSKY_REGS6: 182 return "regs6"; 183 case PERF_REG_CSKY_REGS7: 184 return "regs7"; 185 case PERF_REG_CSKY_REGS8: 186 return "regs8"; 187 case PERF_REG_CSKY_REGS9: 188 return "regs9"; 189 case PERF_REG_CSKY_SP: 190 return "sp"; 191 case PERF_REG_CSKY_LR: 192 return "lr"; 193 case PERF_REG_CSKY_PC: 194 return "pc"; 195 #if defined(__CSKYABIV2__) 196 case PERF_REG_CSKY_EXREGS0: 197 return "exregs0"; 198 case PERF_REG_CSKY_EXREGS1: 199 return "exregs1"; 200 case PERF_REG_CSKY_EXREGS2: 201 return "exregs2"; 202 case PERF_REG_CSKY_EXREGS3: 203 return "exregs3"; 204 case PERF_REG_CSKY_EXREGS4: 205 return "exregs4"; 206 case PERF_REG_CSKY_EXREGS5: 207 return "exregs5"; 208 case PERF_REG_CSKY_EXREGS6: 209 return "exregs6"; 210 case PERF_REG_CSKY_EXREGS7: 211 return "exregs7"; 212 case PERF_REG_CSKY_EXREGS8: 213 return "exregs8"; 214 case PERF_REG_CSKY_EXREGS9: 215 return "exregs9"; 216 case PERF_REG_CSKY_EXREGS10: 217 return "exregs10"; 218 case PERF_REG_CSKY_EXREGS11: 219 return "exregs11"; 220 case PERF_REG_CSKY_EXREGS12: 221 return "exregs12"; 222 case PERF_REG_CSKY_EXREGS13: 223 return "exregs13"; 224 case PERF_REG_CSKY_EXREGS14: 225 return "exregs14"; 226 case PERF_REG_CSKY_TLS: 227 return "tls"; 228 case PERF_REG_CSKY_HI: 229 return "hi"; 230 case PERF_REG_CSKY_LO: 231 return "lo"; 232 #endif 233 default: 234 return NULL; 235 } 236 237 return NULL; 238 } 239 240 static inline const char *__perf_reg_name_loongarch(int id) 241 { 242 switch (id) { 243 case PERF_REG_LOONGARCH_PC: 244 return "PC"; 245 case PERF_REG_LOONGARCH_R1: 246 return "%r1"; 247 case PERF_REG_LOONGARCH_R2: 248 return "%r2"; 249 case PERF_REG_LOONGARCH_R3: 250 return "%r3"; 251 case PERF_REG_LOONGARCH_R4: 252 return "%r4"; 253 case PERF_REG_LOONGARCH_R5: 254 return "%r5"; 255 case PERF_REG_LOONGARCH_R6: 256 return "%r6"; 257 case PERF_REG_LOONGARCH_R7: 258 return "%r7"; 259 case PERF_REG_LOONGARCH_R8: 260 return "%r8"; 261 case PERF_REG_LOONGARCH_R9: 262 return "%r9"; 263 case PERF_REG_LOONGARCH_R10: 264 return "%r10"; 265 case PERF_REG_LOONGARCH_R11: 266 return "%r11"; 267 case PERF_REG_LOONGARCH_R12: 268 return "%r12"; 269 case PERF_REG_LOONGARCH_R13: 270 return "%r13"; 271 case PERF_REG_LOONGARCH_R14: 272 return "%r14"; 273 case PERF_REG_LOONGARCH_R15: 274 return "%r15"; 275 case PERF_REG_LOONGARCH_R16: 276 return "%r16"; 277 case PERF_REG_LOONGARCH_R17: 278 return "%r17"; 279 case PERF_REG_LOONGARCH_R18: 280 return "%r18"; 281 case PERF_REG_LOONGARCH_R19: 282 return "%r19"; 283 case PERF_REG_LOONGARCH_R20: 284 return "%r20"; 285 case PERF_REG_LOONGARCH_R21: 286 return "%r21"; 287 case PERF_REG_LOONGARCH_R22: 288 return "%r22"; 289 case PERF_REG_LOONGARCH_R23: 290 return "%r23"; 291 case PERF_REG_LOONGARCH_R24: 292 return "%r24"; 293 case PERF_REG_LOONGARCH_R25: 294 return "%r25"; 295 case PERF_REG_LOONGARCH_R26: 296 return "%r26"; 297 case PERF_REG_LOONGARCH_R27: 298 return "%r27"; 299 case PERF_REG_LOONGARCH_R28: 300 return "%r28"; 301 case PERF_REG_LOONGARCH_R29: 302 return "%r29"; 303 case PERF_REG_LOONGARCH_R30: 304 return "%r30"; 305 case PERF_REG_LOONGARCH_R31: 306 return "%r31"; 307 default: 308 break; 309 } 310 return NULL; 311 } 312 313 static const char *__perf_reg_name_mips(int id) 314 { 315 switch (id) { 316 case PERF_REG_MIPS_PC: 317 return "PC"; 318 case PERF_REG_MIPS_R1: 319 return "$1"; 320 case PERF_REG_MIPS_R2: 321 return "$2"; 322 case PERF_REG_MIPS_R3: 323 return "$3"; 324 case PERF_REG_MIPS_R4: 325 return "$4"; 326 case PERF_REG_MIPS_R5: 327 return "$5"; 328 case PERF_REG_MIPS_R6: 329 return "$6"; 330 case PERF_REG_MIPS_R7: 331 return "$7"; 332 case PERF_REG_MIPS_R8: 333 return "$8"; 334 case PERF_REG_MIPS_R9: 335 return "$9"; 336 case PERF_REG_MIPS_R10: 337 return "$10"; 338 case PERF_REG_MIPS_R11: 339 return "$11"; 340 case PERF_REG_MIPS_R12: 341 return "$12"; 342 case PERF_REG_MIPS_R13: 343 return "$13"; 344 case PERF_REG_MIPS_R14: 345 return "$14"; 346 case PERF_REG_MIPS_R15: 347 return "$15"; 348 case PERF_REG_MIPS_R16: 349 return "$16"; 350 case PERF_REG_MIPS_R17: 351 return "$17"; 352 case PERF_REG_MIPS_R18: 353 return "$18"; 354 case PERF_REG_MIPS_R19: 355 return "$19"; 356 case PERF_REG_MIPS_R20: 357 return "$20"; 358 case PERF_REG_MIPS_R21: 359 return "$21"; 360 case PERF_REG_MIPS_R22: 361 return "$22"; 362 case PERF_REG_MIPS_R23: 363 return "$23"; 364 case PERF_REG_MIPS_R24: 365 return "$24"; 366 case PERF_REG_MIPS_R25: 367 return "$25"; 368 case PERF_REG_MIPS_R28: 369 return "$28"; 370 case PERF_REG_MIPS_R29: 371 return "$29"; 372 case PERF_REG_MIPS_R30: 373 return "$30"; 374 case PERF_REG_MIPS_R31: 375 return "$31"; 376 default: 377 break; 378 } 379 return NULL; 380 } 381 382 static const char *__perf_reg_name_powerpc(int id) 383 { 384 switch (id) { 385 case PERF_REG_POWERPC_R0: 386 return "r0"; 387 case PERF_REG_POWERPC_R1: 388 return "r1"; 389 case PERF_REG_POWERPC_R2: 390 return "r2"; 391 case PERF_REG_POWERPC_R3: 392 return "r3"; 393 case PERF_REG_POWERPC_R4: 394 return "r4"; 395 case PERF_REG_POWERPC_R5: 396 return "r5"; 397 case PERF_REG_POWERPC_R6: 398 return "r6"; 399 case PERF_REG_POWERPC_R7: 400 return "r7"; 401 case PERF_REG_POWERPC_R8: 402 return "r8"; 403 case PERF_REG_POWERPC_R9: 404 return "r9"; 405 case PERF_REG_POWERPC_R10: 406 return "r10"; 407 case PERF_REG_POWERPC_R11: 408 return "r11"; 409 case PERF_REG_POWERPC_R12: 410 return "r12"; 411 case PERF_REG_POWERPC_R13: 412 return "r13"; 413 case PERF_REG_POWERPC_R14: 414 return "r14"; 415 case PERF_REG_POWERPC_R15: 416 return "r15"; 417 case PERF_REG_POWERPC_R16: 418 return "r16"; 419 case PERF_REG_POWERPC_R17: 420 return "r17"; 421 case PERF_REG_POWERPC_R18: 422 return "r18"; 423 case PERF_REG_POWERPC_R19: 424 return "r19"; 425 case PERF_REG_POWERPC_R20: 426 return "r20"; 427 case PERF_REG_POWERPC_R21: 428 return "r21"; 429 case PERF_REG_POWERPC_R22: 430 return "r22"; 431 case PERF_REG_POWERPC_R23: 432 return "r23"; 433 case PERF_REG_POWERPC_R24: 434 return "r24"; 435 case PERF_REG_POWERPC_R25: 436 return "r25"; 437 case PERF_REG_POWERPC_R26: 438 return "r26"; 439 case PERF_REG_POWERPC_R27: 440 return "r27"; 441 case PERF_REG_POWERPC_R28: 442 return "r28"; 443 case PERF_REG_POWERPC_R29: 444 return "r29"; 445 case PERF_REG_POWERPC_R30: 446 return "r30"; 447 case PERF_REG_POWERPC_R31: 448 return "r31"; 449 case PERF_REG_POWERPC_NIP: 450 return "nip"; 451 case PERF_REG_POWERPC_MSR: 452 return "msr"; 453 case PERF_REG_POWERPC_ORIG_R3: 454 return "orig_r3"; 455 case PERF_REG_POWERPC_CTR: 456 return "ctr"; 457 case PERF_REG_POWERPC_LINK: 458 return "link"; 459 case PERF_REG_POWERPC_XER: 460 return "xer"; 461 case PERF_REG_POWERPC_CCR: 462 return "ccr"; 463 case PERF_REG_POWERPC_SOFTE: 464 return "softe"; 465 case PERF_REG_POWERPC_TRAP: 466 return "trap"; 467 case PERF_REG_POWERPC_DAR: 468 return "dar"; 469 case PERF_REG_POWERPC_DSISR: 470 return "dsisr"; 471 case PERF_REG_POWERPC_SIER: 472 return "sier"; 473 case PERF_REG_POWERPC_MMCRA: 474 return "mmcra"; 475 case PERF_REG_POWERPC_MMCR0: 476 return "mmcr0"; 477 case PERF_REG_POWERPC_MMCR1: 478 return "mmcr1"; 479 case PERF_REG_POWERPC_MMCR2: 480 return "mmcr2"; 481 case PERF_REG_POWERPC_MMCR3: 482 return "mmcr3"; 483 case PERF_REG_POWERPC_SIER2: 484 return "sier2"; 485 case PERF_REG_POWERPC_SIER3: 486 return "sier3"; 487 case PERF_REG_POWERPC_PMC1: 488 return "pmc1"; 489 case PERF_REG_POWERPC_PMC2: 490 return "pmc2"; 491 case PERF_REG_POWERPC_PMC3: 492 return "pmc3"; 493 case PERF_REG_POWERPC_PMC4: 494 return "pmc4"; 495 case PERF_REG_POWERPC_PMC5: 496 return "pmc5"; 497 case PERF_REG_POWERPC_PMC6: 498 return "pmc6"; 499 case PERF_REG_POWERPC_SDAR: 500 return "sdar"; 501 case PERF_REG_POWERPC_SIAR: 502 return "siar"; 503 default: 504 break; 505 } 506 return NULL; 507 } 508 509 static const char *__perf_reg_name_riscv(int id) 510 { 511 switch (id) { 512 case PERF_REG_RISCV_PC: 513 return "pc"; 514 case PERF_REG_RISCV_RA: 515 return "ra"; 516 case PERF_REG_RISCV_SP: 517 return "sp"; 518 case PERF_REG_RISCV_GP: 519 return "gp"; 520 case PERF_REG_RISCV_TP: 521 return "tp"; 522 case PERF_REG_RISCV_T0: 523 return "t0"; 524 case PERF_REG_RISCV_T1: 525 return "t1"; 526 case PERF_REG_RISCV_T2: 527 return "t2"; 528 case PERF_REG_RISCV_S0: 529 return "s0"; 530 case PERF_REG_RISCV_S1: 531 return "s1"; 532 case PERF_REG_RISCV_A0: 533 return "a0"; 534 case PERF_REG_RISCV_A1: 535 return "a1"; 536 case PERF_REG_RISCV_A2: 537 return "a2"; 538 case PERF_REG_RISCV_A3: 539 return "a3"; 540 case PERF_REG_RISCV_A4: 541 return "a4"; 542 case PERF_REG_RISCV_A5: 543 return "a5"; 544 case PERF_REG_RISCV_A6: 545 return "a6"; 546 case PERF_REG_RISCV_A7: 547 return "a7"; 548 case PERF_REG_RISCV_S2: 549 return "s2"; 550 case PERF_REG_RISCV_S3: 551 return "s3"; 552 case PERF_REG_RISCV_S4: 553 return "s4"; 554 case PERF_REG_RISCV_S5: 555 return "s5"; 556 case PERF_REG_RISCV_S6: 557 return "s6"; 558 case PERF_REG_RISCV_S7: 559 return "s7"; 560 case PERF_REG_RISCV_S8: 561 return "s8"; 562 case PERF_REG_RISCV_S9: 563 return "s9"; 564 case PERF_REG_RISCV_S10: 565 return "s10"; 566 case PERF_REG_RISCV_S11: 567 return "s11"; 568 case PERF_REG_RISCV_T3: 569 return "t3"; 570 case PERF_REG_RISCV_T4: 571 return "t4"; 572 case PERF_REG_RISCV_T5: 573 return "t5"; 574 case PERF_REG_RISCV_T6: 575 return "t6"; 576 default: 577 return NULL; 578 } 579 580 return NULL; 581 } 582 583 static const char *__perf_reg_name_s390(int id) 584 { 585 switch (id) { 586 case PERF_REG_S390_R0: 587 return "R0"; 588 case PERF_REG_S390_R1: 589 return "R1"; 590 case PERF_REG_S390_R2: 591 return "R2"; 592 case PERF_REG_S390_R3: 593 return "R3"; 594 case PERF_REG_S390_R4: 595 return "R4"; 596 case PERF_REG_S390_R5: 597 return "R5"; 598 case PERF_REG_S390_R6: 599 return "R6"; 600 case PERF_REG_S390_R7: 601 return "R7"; 602 case PERF_REG_S390_R8: 603 return "R8"; 604 case PERF_REG_S390_R9: 605 return "R9"; 606 case PERF_REG_S390_R10: 607 return "R10"; 608 case PERF_REG_S390_R11: 609 return "R11"; 610 case PERF_REG_S390_R12: 611 return "R12"; 612 case PERF_REG_S390_R13: 613 return "R13"; 614 case PERF_REG_S390_R14: 615 return "R14"; 616 case PERF_REG_S390_R15: 617 return "R15"; 618 case PERF_REG_S390_FP0: 619 return "FP0"; 620 case PERF_REG_S390_FP1: 621 return "FP1"; 622 case PERF_REG_S390_FP2: 623 return "FP2"; 624 case PERF_REG_S390_FP3: 625 return "FP3"; 626 case PERF_REG_S390_FP4: 627 return "FP4"; 628 case PERF_REG_S390_FP5: 629 return "FP5"; 630 case PERF_REG_S390_FP6: 631 return "FP6"; 632 case PERF_REG_S390_FP7: 633 return "FP7"; 634 case PERF_REG_S390_FP8: 635 return "FP8"; 636 case PERF_REG_S390_FP9: 637 return "FP9"; 638 case PERF_REG_S390_FP10: 639 return "FP10"; 640 case PERF_REG_S390_FP11: 641 return "FP11"; 642 case PERF_REG_S390_FP12: 643 return "FP12"; 644 case PERF_REG_S390_FP13: 645 return "FP13"; 646 case PERF_REG_S390_FP14: 647 return "FP14"; 648 case PERF_REG_S390_FP15: 649 return "FP15"; 650 case PERF_REG_S390_MASK: 651 return "MASK"; 652 case PERF_REG_S390_PC: 653 return "PC"; 654 default: 655 return NULL; 656 } 657 658 return NULL; 659 } 660 661 static const char *__perf_reg_name_x86(int id) 662 { 663 switch (id) { 664 case PERF_REG_X86_AX: 665 return "AX"; 666 case PERF_REG_X86_BX: 667 return "BX"; 668 case PERF_REG_X86_CX: 669 return "CX"; 670 case PERF_REG_X86_DX: 671 return "DX"; 672 case PERF_REG_X86_SI: 673 return "SI"; 674 case PERF_REG_X86_DI: 675 return "DI"; 676 case PERF_REG_X86_BP: 677 return "BP"; 678 case PERF_REG_X86_SP: 679 return "SP"; 680 case PERF_REG_X86_IP: 681 return "IP"; 682 case PERF_REG_X86_FLAGS: 683 return "FLAGS"; 684 case PERF_REG_X86_CS: 685 return "CS"; 686 case PERF_REG_X86_SS: 687 return "SS"; 688 case PERF_REG_X86_DS: 689 return "DS"; 690 case PERF_REG_X86_ES: 691 return "ES"; 692 case PERF_REG_X86_FS: 693 return "FS"; 694 case PERF_REG_X86_GS: 695 return "GS"; 696 case PERF_REG_X86_R8: 697 return "R8"; 698 case PERF_REG_X86_R9: 699 return "R9"; 700 case PERF_REG_X86_R10: 701 return "R10"; 702 case PERF_REG_X86_R11: 703 return "R11"; 704 case PERF_REG_X86_R12: 705 return "R12"; 706 case PERF_REG_X86_R13: 707 return "R13"; 708 case PERF_REG_X86_R14: 709 return "R14"; 710 case PERF_REG_X86_R15: 711 return "R15"; 712 713 #define XMM(x) \ 714 case PERF_REG_X86_XMM ## x: \ 715 case PERF_REG_X86_XMM ## x + 1: \ 716 return "XMM" #x; 717 XMM(0) 718 XMM(1) 719 XMM(2) 720 XMM(3) 721 XMM(4) 722 XMM(5) 723 XMM(6) 724 XMM(7) 725 XMM(8) 726 XMM(9) 727 XMM(10) 728 XMM(11) 729 XMM(12) 730 XMM(13) 731 XMM(14) 732 XMM(15) 733 #undef XMM 734 default: 735 return NULL; 736 } 737 738 return NULL; 739 } 740 741 const char *perf_reg_name(int id, const char *arch) 742 { 743 const char *reg_name = NULL; 744 745 if (!strcmp(arch, "csky")) 746 reg_name = __perf_reg_name_csky(id); 747 else if (!strcmp(arch, "loongarch")) 748 reg_name = __perf_reg_name_loongarch(id); 749 else if (!strcmp(arch, "mips")) 750 reg_name = __perf_reg_name_mips(id); 751 else if (!strcmp(arch, "powerpc")) 752 reg_name = __perf_reg_name_powerpc(id); 753 else if (!strcmp(arch, "riscv")) 754 reg_name = __perf_reg_name_riscv(id); 755 else if (!strcmp(arch, "s390")) 756 reg_name = __perf_reg_name_s390(id); 757 else if (!strcmp(arch, "x86")) 758 reg_name = __perf_reg_name_x86(id); 759 else if (!strcmp(arch, "arm")) 760 reg_name = __perf_reg_name_arm(id); 761 else if (!strcmp(arch, "arm64")) 762 reg_name = __perf_reg_name_arm64(id); 763 764 return reg_name ?: "unknown"; 765 } 766 767 int perf_reg_value(u64 *valp, struct regs_dump *regs, int id) 768 { 769 int i, idx = 0; 770 u64 mask = regs->mask; 771 772 if ((u64)id >= PERF_SAMPLE_REGS_CACHE_SIZE) 773 return -EINVAL; 774 775 if (regs->cache_mask & (1ULL << id)) 776 goto out; 777 778 if (!(mask & (1ULL << id))) 779 return -EINVAL; 780 781 for (i = 0; i < id; i++) { 782 if (mask & (1ULL << i)) 783 idx++; 784 } 785 786 regs->cache_mask |= (1ULL << id); 787 regs->cache_regs[id] = regs->regs[idx]; 788 789 out: 790 *valp = regs->cache_regs[id]; 791 return 0; 792 } 793 #endif 794