1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pt.c: Intel Processor Trace support 4 * Copyright (c) 2013-2015, Intel Corporation. 5 */ 6 7 #include <inttypes.h> 8 #include <stdio.h> 9 #include <stdbool.h> 10 #include <errno.h> 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/types.h> 14 #include <linux/zalloc.h> 15 16 #include "session.h" 17 #include "machine.h" 18 #include "memswap.h" 19 #include "sort.h" 20 #include "tool.h" 21 #include "event.h" 22 #include "evlist.h" 23 #include "evsel.h" 24 #include "map.h" 25 #include "color.h" 26 #include "thread.h" 27 #include "thread-stack.h" 28 #include "symbol.h" 29 #include "callchain.h" 30 #include "dso.h" 31 #include "debug.h" 32 #include "auxtrace.h" 33 #include "tsc.h" 34 #include "intel-pt.h" 35 #include "config.h" 36 #include "util/perf_api_probe.h" 37 #include "util/synthetic-events.h" 38 #include "time-utils.h" 39 40 #include "../arch/x86/include/uapi/asm/perf_regs.h" 41 42 #include "intel-pt-decoder/intel-pt-log.h" 43 #include "intel-pt-decoder/intel-pt-decoder.h" 44 #include "intel-pt-decoder/intel-pt-insn-decoder.h" 45 #include "intel-pt-decoder/intel-pt-pkt-decoder.h" 46 47 #define MAX_TIMESTAMP (~0ULL) 48 49 #define INTEL_PT_CFG_PASS_THRU BIT_ULL(0) 50 #define INTEL_PT_CFG_PWR_EVT_EN BIT_ULL(4) 51 #define INTEL_PT_CFG_BRANCH_EN BIT_ULL(13) 52 #define INTEL_PT_CFG_EVT_EN BIT_ULL(31) 53 #define INTEL_PT_CFG_TNT_DIS BIT_ULL(55) 54 55 struct range { 56 u64 start; 57 u64 end; 58 }; 59 60 struct intel_pt { 61 struct auxtrace auxtrace; 62 struct auxtrace_queues queues; 63 struct auxtrace_heap heap; 64 u32 auxtrace_type; 65 struct perf_session *session; 66 struct machine *machine; 67 struct evsel *switch_evsel; 68 struct thread *unknown_thread; 69 bool timeless_decoding; 70 bool sampling_mode; 71 bool snapshot_mode; 72 bool per_cpu_mmaps; 73 bool have_tsc; 74 bool data_queued; 75 bool est_tsc; 76 bool sync_switch; 77 bool sync_switch_not_supported; 78 bool mispred_all; 79 bool use_thread_stack; 80 bool callstack; 81 bool cap_event_trace; 82 bool have_guest_sideband; 83 unsigned int br_stack_sz; 84 unsigned int br_stack_sz_plus; 85 int have_sched_switch; 86 u32 pmu_type; 87 u64 kernel_start; 88 u64 switch_ip; 89 u64 ptss_ip; 90 u64 first_timestamp; 91 92 struct perf_tsc_conversion tc; 93 bool cap_user_time_zero; 94 95 struct itrace_synth_opts synth_opts; 96 97 bool sample_instructions; 98 u64 instructions_sample_type; 99 u64 instructions_id; 100 101 bool sample_branches; 102 u32 branches_filter; 103 u64 branches_sample_type; 104 u64 branches_id; 105 106 bool sample_transactions; 107 u64 transactions_sample_type; 108 u64 transactions_id; 109 110 bool sample_ptwrites; 111 u64 ptwrites_sample_type; 112 u64 ptwrites_id; 113 114 bool sample_pwr_events; 115 u64 pwr_events_sample_type; 116 u64 mwait_id; 117 u64 pwre_id; 118 u64 exstop_id; 119 u64 pwrx_id; 120 u64 cbr_id; 121 u64 psb_id; 122 123 bool single_pebs; 124 bool sample_pebs; 125 struct evsel *pebs_evsel; 126 127 u64 evt_sample_type; 128 u64 evt_id; 129 130 u64 iflag_chg_sample_type; 131 u64 iflag_chg_id; 132 133 u64 tsc_bit; 134 u64 mtc_bit; 135 u64 mtc_freq_bits; 136 u32 tsc_ctc_ratio_n; 137 u32 tsc_ctc_ratio_d; 138 u64 cyc_bit; 139 u64 noretcomp_bit; 140 unsigned max_non_turbo_ratio; 141 unsigned cbr2khz; 142 int max_loops; 143 144 unsigned long num_events; 145 146 char *filter; 147 struct addr_filters filts; 148 149 struct range *time_ranges; 150 unsigned int range_cnt; 151 152 struct ip_callchain *chain; 153 struct branch_stack *br_stack; 154 155 u64 dflt_tsc_offset; 156 struct rb_root vmcs_info; 157 }; 158 159 enum switch_state { 160 INTEL_PT_SS_NOT_TRACING, 161 INTEL_PT_SS_UNKNOWN, 162 INTEL_PT_SS_TRACING, 163 INTEL_PT_SS_EXPECTING_SWITCH_EVENT, 164 INTEL_PT_SS_EXPECTING_SWITCH_IP, 165 }; 166 167 /* applicable_counters is 64-bits */ 168 #define INTEL_PT_MAX_PEBS 64 169 170 struct intel_pt_pebs_event { 171 struct evsel *evsel; 172 u64 id; 173 }; 174 175 struct intel_pt_queue { 176 struct intel_pt *pt; 177 unsigned int queue_nr; 178 struct auxtrace_buffer *buffer; 179 struct auxtrace_buffer *old_buffer; 180 void *decoder; 181 const struct intel_pt_state *state; 182 struct ip_callchain *chain; 183 struct branch_stack *last_branch; 184 union perf_event *event_buf; 185 bool on_heap; 186 bool stop; 187 bool step_through_buffers; 188 bool use_buffer_pid_tid; 189 bool sync_switch; 190 bool sample_ipc; 191 pid_t pid, tid; 192 int cpu; 193 int switch_state; 194 pid_t next_tid; 195 struct thread *thread; 196 struct machine *guest_machine; 197 struct thread *guest_thread; 198 struct thread *unknown_guest_thread; 199 pid_t guest_machine_pid; 200 pid_t guest_pid; 201 pid_t guest_tid; 202 int vcpu; 203 bool exclude_kernel; 204 bool have_sample; 205 u64 time; 206 u64 timestamp; 207 u64 sel_timestamp; 208 bool sel_start; 209 unsigned int sel_idx; 210 u32 flags; 211 u16 insn_len; 212 u64 last_insn_cnt; 213 u64 ipc_insn_cnt; 214 u64 ipc_cyc_cnt; 215 u64 last_in_insn_cnt; 216 u64 last_in_cyc_cnt; 217 u64 last_br_insn_cnt; 218 u64 last_br_cyc_cnt; 219 unsigned int cbr_seen; 220 char insn[INTEL_PT_INSN_BUF_SZ]; 221 struct intel_pt_pebs_event pebs[INTEL_PT_MAX_PEBS]; 222 }; 223 224 static void intel_pt_dump(struct intel_pt *pt __maybe_unused, 225 unsigned char *buf, size_t len) 226 { 227 struct intel_pt_pkt packet; 228 size_t pos = 0; 229 int ret, pkt_len, i; 230 char desc[INTEL_PT_PKT_DESC_MAX]; 231 const char *color = PERF_COLOR_BLUE; 232 enum intel_pt_pkt_ctx ctx = INTEL_PT_NO_CTX; 233 234 color_fprintf(stdout, color, 235 ". ... Intel Processor Trace data: size %zu bytes\n", 236 len); 237 238 while (len) { 239 ret = intel_pt_get_packet(buf, len, &packet, &ctx); 240 if (ret > 0) 241 pkt_len = ret; 242 else 243 pkt_len = 1; 244 printf("."); 245 color_fprintf(stdout, color, " %08x: ", pos); 246 for (i = 0; i < pkt_len; i++) 247 color_fprintf(stdout, color, " %02x", buf[i]); 248 for (; i < 16; i++) 249 color_fprintf(stdout, color, " "); 250 if (ret > 0) { 251 ret = intel_pt_pkt_desc(&packet, desc, 252 INTEL_PT_PKT_DESC_MAX); 253 if (ret > 0) 254 color_fprintf(stdout, color, " %s\n", desc); 255 } else { 256 color_fprintf(stdout, color, " Bad packet!\n"); 257 } 258 pos += pkt_len; 259 buf += pkt_len; 260 len -= pkt_len; 261 } 262 } 263 264 static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf, 265 size_t len) 266 { 267 printf(".\n"); 268 intel_pt_dump(pt, buf, len); 269 } 270 271 static void intel_pt_log_event(union perf_event *event) 272 { 273 FILE *f = intel_pt_log_fp(); 274 275 if (!intel_pt_enable_logging || !f) 276 return; 277 278 perf_event__fprintf(event, NULL, f); 279 } 280 281 static void intel_pt_dump_sample(struct perf_session *session, 282 struct perf_sample *sample) 283 { 284 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 285 auxtrace); 286 287 printf("\n"); 288 intel_pt_dump(pt, sample->aux_sample.data, sample->aux_sample.size); 289 } 290 291 static bool intel_pt_log_events(struct intel_pt *pt, u64 tm) 292 { 293 struct perf_time_interval *range = pt->synth_opts.ptime_range; 294 int n = pt->synth_opts.range_num; 295 296 if (pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS) 297 return true; 298 299 if (pt->synth_opts.log_minus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS) 300 return false; 301 302 /* perf_time__ranges_skip_sample does not work if time is zero */ 303 if (!tm) 304 tm = 1; 305 306 return !n || !perf_time__ranges_skip_sample(range, n, tm); 307 } 308 309 static struct intel_pt_vmcs_info *intel_pt_findnew_vmcs(struct rb_root *rb_root, 310 u64 vmcs, 311 u64 dflt_tsc_offset) 312 { 313 struct rb_node **p = &rb_root->rb_node; 314 struct rb_node *parent = NULL; 315 struct intel_pt_vmcs_info *v; 316 317 while (*p) { 318 parent = *p; 319 v = rb_entry(parent, struct intel_pt_vmcs_info, rb_node); 320 321 if (v->vmcs == vmcs) 322 return v; 323 324 if (vmcs < v->vmcs) 325 p = &(*p)->rb_left; 326 else 327 p = &(*p)->rb_right; 328 } 329 330 v = zalloc(sizeof(*v)); 331 if (v) { 332 v->vmcs = vmcs; 333 v->tsc_offset = dflt_tsc_offset; 334 v->reliable = dflt_tsc_offset; 335 336 rb_link_node(&v->rb_node, parent, p); 337 rb_insert_color(&v->rb_node, rb_root); 338 } 339 340 return v; 341 } 342 343 static struct intel_pt_vmcs_info *intel_pt_findnew_vmcs_info(void *data, uint64_t vmcs) 344 { 345 struct intel_pt_queue *ptq = data; 346 struct intel_pt *pt = ptq->pt; 347 348 if (!vmcs && !pt->dflt_tsc_offset) 349 return NULL; 350 351 return intel_pt_findnew_vmcs(&pt->vmcs_info, vmcs, pt->dflt_tsc_offset); 352 } 353 354 static void intel_pt_free_vmcs_info(struct intel_pt *pt) 355 { 356 struct intel_pt_vmcs_info *v; 357 struct rb_node *n; 358 359 n = rb_first(&pt->vmcs_info); 360 while (n) { 361 v = rb_entry(n, struct intel_pt_vmcs_info, rb_node); 362 n = rb_next(n); 363 rb_erase(&v->rb_node, &pt->vmcs_info); 364 free(v); 365 } 366 } 367 368 static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a, 369 struct auxtrace_buffer *b) 370 { 371 bool consecutive = false; 372 void *start; 373 374 start = intel_pt_find_overlap(a->data, a->size, b->data, b->size, 375 pt->have_tsc, &consecutive, 376 pt->synth_opts.vm_time_correlation); 377 if (!start) 378 return -EINVAL; 379 /* 380 * In the case of vm_time_correlation, the overlap might contain TSC 381 * packets that will not be fixed, and that will then no longer work for 382 * overlap detection. Avoid that by zeroing out the overlap. 383 */ 384 if (pt->synth_opts.vm_time_correlation) 385 memset(b->data, 0, start - b->data); 386 b->use_size = b->data + b->size - start; 387 b->use_data = start; 388 if (b->use_size && consecutive) 389 b->consecutive = true; 390 return 0; 391 } 392 393 static int intel_pt_get_buffer(struct intel_pt_queue *ptq, 394 struct auxtrace_buffer *buffer, 395 struct auxtrace_buffer *old_buffer, 396 struct intel_pt_buffer *b) 397 { 398 bool might_overlap; 399 400 if (!buffer->data) { 401 int fd = perf_data__fd(ptq->pt->session->data); 402 403 buffer->data = auxtrace_buffer__get_data(buffer, fd); 404 if (!buffer->data) 405 return -ENOMEM; 406 } 407 408 might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode; 409 if (might_overlap && !buffer->consecutive && old_buffer && 410 intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer)) 411 return -ENOMEM; 412 413 if (buffer->use_data) { 414 b->len = buffer->use_size; 415 b->buf = buffer->use_data; 416 } else { 417 b->len = buffer->size; 418 b->buf = buffer->data; 419 } 420 b->ref_timestamp = buffer->reference; 421 422 if (!old_buffer || (might_overlap && !buffer->consecutive)) { 423 b->consecutive = false; 424 b->trace_nr = buffer->buffer_nr + 1; 425 } else { 426 b->consecutive = true; 427 } 428 429 return 0; 430 } 431 432 /* Do not drop buffers with references - refer intel_pt_get_trace() */ 433 static void intel_pt_lookahead_drop_buffer(struct intel_pt_queue *ptq, 434 struct auxtrace_buffer *buffer) 435 { 436 if (!buffer || buffer == ptq->buffer || buffer == ptq->old_buffer) 437 return; 438 439 auxtrace_buffer__drop_data(buffer); 440 } 441 442 /* Must be serialized with respect to intel_pt_get_trace() */ 443 static int intel_pt_lookahead(void *data, intel_pt_lookahead_cb_t cb, 444 void *cb_data) 445 { 446 struct intel_pt_queue *ptq = data; 447 struct auxtrace_buffer *buffer = ptq->buffer; 448 struct auxtrace_buffer *old_buffer = ptq->old_buffer; 449 struct auxtrace_queue *queue; 450 int err = 0; 451 452 queue = &ptq->pt->queues.queue_array[ptq->queue_nr]; 453 454 while (1) { 455 struct intel_pt_buffer b = { .len = 0 }; 456 457 buffer = auxtrace_buffer__next(queue, buffer); 458 if (!buffer) 459 break; 460 461 err = intel_pt_get_buffer(ptq, buffer, old_buffer, &b); 462 if (err) 463 break; 464 465 if (b.len) { 466 intel_pt_lookahead_drop_buffer(ptq, old_buffer); 467 old_buffer = buffer; 468 } else { 469 intel_pt_lookahead_drop_buffer(ptq, buffer); 470 continue; 471 } 472 473 err = cb(&b, cb_data); 474 if (err) 475 break; 476 } 477 478 if (buffer != old_buffer) 479 intel_pt_lookahead_drop_buffer(ptq, buffer); 480 intel_pt_lookahead_drop_buffer(ptq, old_buffer); 481 482 return err; 483 } 484 485 /* 486 * This function assumes data is processed sequentially only. 487 * Must be serialized with respect to intel_pt_lookahead() 488 */ 489 static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data) 490 { 491 struct intel_pt_queue *ptq = data; 492 struct auxtrace_buffer *buffer = ptq->buffer; 493 struct auxtrace_buffer *old_buffer = ptq->old_buffer; 494 struct auxtrace_queue *queue; 495 int err; 496 497 if (ptq->stop) { 498 b->len = 0; 499 return 0; 500 } 501 502 queue = &ptq->pt->queues.queue_array[ptq->queue_nr]; 503 504 buffer = auxtrace_buffer__next(queue, buffer); 505 if (!buffer) { 506 if (old_buffer) 507 auxtrace_buffer__drop_data(old_buffer); 508 b->len = 0; 509 return 0; 510 } 511 512 ptq->buffer = buffer; 513 514 err = intel_pt_get_buffer(ptq, buffer, old_buffer, b); 515 if (err) 516 return err; 517 518 if (ptq->step_through_buffers) 519 ptq->stop = true; 520 521 if (b->len) { 522 if (old_buffer) 523 auxtrace_buffer__drop_data(old_buffer); 524 ptq->old_buffer = buffer; 525 } else { 526 auxtrace_buffer__drop_data(buffer); 527 return intel_pt_get_trace(b, data); 528 } 529 530 return 0; 531 } 532 533 struct intel_pt_cache_entry { 534 struct auxtrace_cache_entry entry; 535 u64 insn_cnt; 536 u64 byte_cnt; 537 enum intel_pt_insn_op op; 538 enum intel_pt_insn_branch branch; 539 bool emulated_ptwrite; 540 int length; 541 int32_t rel; 542 char insn[INTEL_PT_INSN_BUF_SZ]; 543 }; 544 545 static int intel_pt_config_div(const char *var, const char *value, void *data) 546 { 547 int *d = data; 548 long val; 549 550 if (!strcmp(var, "intel-pt.cache-divisor")) { 551 val = strtol(value, NULL, 0); 552 if (val > 0 && val <= INT_MAX) 553 *d = val; 554 } 555 556 return 0; 557 } 558 559 static int intel_pt_cache_divisor(void) 560 { 561 static int d; 562 563 if (d) 564 return d; 565 566 perf_config(intel_pt_config_div, &d); 567 568 if (!d) 569 d = 64; 570 571 return d; 572 } 573 574 static unsigned int intel_pt_cache_size(struct dso *dso, 575 struct machine *machine) 576 { 577 off_t size; 578 579 size = dso__data_size(dso, machine); 580 size /= intel_pt_cache_divisor(); 581 if (size < 1000) 582 return 10; 583 if (size > (1 << 21)) 584 return 21; 585 return 32 - __builtin_clz(size); 586 } 587 588 static struct auxtrace_cache *intel_pt_cache(struct dso *dso, 589 struct machine *machine) 590 { 591 struct auxtrace_cache *c; 592 unsigned int bits; 593 594 if (dso->auxtrace_cache) 595 return dso->auxtrace_cache; 596 597 bits = intel_pt_cache_size(dso, machine); 598 599 /* Ignoring cache creation failure */ 600 c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200); 601 602 dso->auxtrace_cache = c; 603 604 return c; 605 } 606 607 static int intel_pt_cache_add(struct dso *dso, struct machine *machine, 608 u64 offset, u64 insn_cnt, u64 byte_cnt, 609 struct intel_pt_insn *intel_pt_insn) 610 { 611 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 612 struct intel_pt_cache_entry *e; 613 int err; 614 615 if (!c) 616 return -ENOMEM; 617 618 e = auxtrace_cache__alloc_entry(c); 619 if (!e) 620 return -ENOMEM; 621 622 e->insn_cnt = insn_cnt; 623 e->byte_cnt = byte_cnt; 624 e->op = intel_pt_insn->op; 625 e->branch = intel_pt_insn->branch; 626 e->emulated_ptwrite = intel_pt_insn->emulated_ptwrite; 627 e->length = intel_pt_insn->length; 628 e->rel = intel_pt_insn->rel; 629 memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ); 630 631 err = auxtrace_cache__add(c, offset, &e->entry); 632 if (err) 633 auxtrace_cache__free_entry(c, e); 634 635 return err; 636 } 637 638 static struct intel_pt_cache_entry * 639 intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset) 640 { 641 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 642 643 if (!c) 644 return NULL; 645 646 return auxtrace_cache__lookup(dso->auxtrace_cache, offset); 647 } 648 649 static void intel_pt_cache_invalidate(struct dso *dso, struct machine *machine, 650 u64 offset) 651 { 652 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 653 654 if (!c) 655 return; 656 657 auxtrace_cache__remove(dso->auxtrace_cache, offset); 658 } 659 660 static inline bool intel_pt_guest_kernel_ip(uint64_t ip) 661 { 662 /* Assumes 64-bit kernel */ 663 return ip & (1ULL << 63); 664 } 665 666 static inline u8 intel_pt_nr_cpumode(struct intel_pt_queue *ptq, uint64_t ip, bool nr) 667 { 668 if (nr) { 669 return intel_pt_guest_kernel_ip(ip) ? 670 PERF_RECORD_MISC_GUEST_KERNEL : 671 PERF_RECORD_MISC_GUEST_USER; 672 } 673 674 return ip >= ptq->pt->kernel_start ? 675 PERF_RECORD_MISC_KERNEL : 676 PERF_RECORD_MISC_USER; 677 } 678 679 static inline u8 intel_pt_cpumode(struct intel_pt_queue *ptq, uint64_t from_ip, uint64_t to_ip) 680 { 681 /* No support for non-zero CS base */ 682 if (from_ip) 683 return intel_pt_nr_cpumode(ptq, from_ip, ptq->state->from_nr); 684 return intel_pt_nr_cpumode(ptq, to_ip, ptq->state->to_nr); 685 } 686 687 static int intel_pt_get_guest(struct intel_pt_queue *ptq) 688 { 689 struct machines *machines = &ptq->pt->session->machines; 690 struct machine *machine; 691 pid_t pid = ptq->pid <= 0 ? DEFAULT_GUEST_KERNEL_ID : ptq->pid; 692 693 if (ptq->guest_machine && pid == ptq->guest_machine->pid) 694 return 0; 695 696 ptq->guest_machine = NULL; 697 thread__zput(ptq->unknown_guest_thread); 698 699 if (symbol_conf.guest_code) { 700 thread__zput(ptq->guest_thread); 701 ptq->guest_thread = machines__findnew_guest_code(machines, pid); 702 } 703 704 machine = machines__find_guest(machines, pid); 705 if (!machine) 706 return -1; 707 708 ptq->unknown_guest_thread = machine__idle_thread(machine); 709 if (!ptq->unknown_guest_thread) 710 return -1; 711 712 ptq->guest_machine = machine; 713 714 return 0; 715 } 716 717 static inline bool intel_pt_jmp_16(struct intel_pt_insn *intel_pt_insn) 718 { 719 return intel_pt_insn->rel == 16 && intel_pt_insn->branch == INTEL_PT_BR_UNCONDITIONAL; 720 } 721 722 #define PTWRITE_MAGIC "\x0f\x0bperf,ptwrite " 723 #define PTWRITE_MAGIC_LEN 16 724 725 static bool intel_pt_emulated_ptwrite(struct dso *dso, struct machine *machine, u64 offset) 726 { 727 unsigned char buf[PTWRITE_MAGIC_LEN]; 728 ssize_t len; 729 730 len = dso__data_read_offset(dso, machine, offset, buf, PTWRITE_MAGIC_LEN); 731 if (len == PTWRITE_MAGIC_LEN && !memcmp(buf, PTWRITE_MAGIC, PTWRITE_MAGIC_LEN)) { 732 intel_pt_log("Emulated ptwrite signature found\n"); 733 return true; 734 } 735 intel_pt_log("Emulated ptwrite signature not found\n"); 736 return false; 737 } 738 739 static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, 740 uint64_t *insn_cnt_ptr, uint64_t *ip, 741 uint64_t to_ip, uint64_t max_insn_cnt, 742 void *data) 743 { 744 struct intel_pt_queue *ptq = data; 745 struct machine *machine = ptq->pt->machine; 746 struct thread *thread; 747 struct addr_location al; 748 unsigned char buf[INTEL_PT_INSN_BUF_SZ]; 749 ssize_t len; 750 int x86_64; 751 u8 cpumode; 752 u64 offset, start_offset, start_ip; 753 u64 insn_cnt = 0; 754 bool one_map = true; 755 bool nr; 756 757 intel_pt_insn->length = 0; 758 759 if (to_ip && *ip == to_ip) 760 goto out_no_cache; 761 762 nr = ptq->state->to_nr; 763 cpumode = intel_pt_nr_cpumode(ptq, *ip, nr); 764 765 if (nr) { 766 if (ptq->pt->have_guest_sideband) { 767 if (!ptq->guest_machine || ptq->guest_machine_pid != ptq->pid) { 768 intel_pt_log("ERROR: guest sideband but no guest machine\n"); 769 return -EINVAL; 770 } 771 } else if ((!symbol_conf.guest_code && cpumode != PERF_RECORD_MISC_GUEST_KERNEL) || 772 intel_pt_get_guest(ptq)) { 773 intel_pt_log("ERROR: no guest machine\n"); 774 return -EINVAL; 775 } 776 machine = ptq->guest_machine; 777 thread = ptq->guest_thread; 778 if (!thread) { 779 if (cpumode != PERF_RECORD_MISC_GUEST_KERNEL) { 780 intel_pt_log("ERROR: no guest thread\n"); 781 return -EINVAL; 782 } 783 thread = ptq->unknown_guest_thread; 784 } 785 } else { 786 thread = ptq->thread; 787 if (!thread) { 788 if (cpumode != PERF_RECORD_MISC_KERNEL) { 789 intel_pt_log("ERROR: no thread\n"); 790 return -EINVAL; 791 } 792 thread = ptq->pt->unknown_thread; 793 } 794 } 795 796 while (1) { 797 if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso) { 798 if (al.map) 799 intel_pt_log("ERROR: thread has no dso for %#" PRIx64 "\n", *ip); 800 else 801 intel_pt_log("ERROR: thread has no map for %#" PRIx64 "\n", *ip); 802 return -EINVAL; 803 } 804 805 if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR && 806 dso__data_status_seen(al.map->dso, 807 DSO_DATA_STATUS_SEEN_ITRACE)) 808 return -ENOENT; 809 810 offset = al.map->map_ip(al.map, *ip); 811 812 if (!to_ip && one_map) { 813 struct intel_pt_cache_entry *e; 814 815 e = intel_pt_cache_lookup(al.map->dso, machine, offset); 816 if (e && 817 (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) { 818 *insn_cnt_ptr = e->insn_cnt; 819 *ip += e->byte_cnt; 820 intel_pt_insn->op = e->op; 821 intel_pt_insn->branch = e->branch; 822 intel_pt_insn->emulated_ptwrite = e->emulated_ptwrite; 823 intel_pt_insn->length = e->length; 824 intel_pt_insn->rel = e->rel; 825 memcpy(intel_pt_insn->buf, e->insn, 826 INTEL_PT_INSN_BUF_SZ); 827 intel_pt_log_insn_no_data(intel_pt_insn, *ip); 828 return 0; 829 } 830 } 831 832 start_offset = offset; 833 start_ip = *ip; 834 835 /* Load maps to ensure dso->is_64_bit has been updated */ 836 map__load(al.map); 837 838 x86_64 = al.map->dso->is_64_bit; 839 840 while (1) { 841 len = dso__data_read_offset(al.map->dso, machine, 842 offset, buf, 843 INTEL_PT_INSN_BUF_SZ); 844 if (len <= 0) { 845 intel_pt_log("ERROR: failed to read at offset %#" PRIx64 " ", 846 offset); 847 if (intel_pt_enable_logging) 848 dso__fprintf(al.map->dso, intel_pt_log_fp()); 849 return -EINVAL; 850 } 851 852 if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn)) 853 return -EINVAL; 854 855 intel_pt_log_insn(intel_pt_insn, *ip); 856 857 insn_cnt += 1; 858 859 if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH) { 860 bool eptw; 861 u64 offs; 862 863 if (!intel_pt_jmp_16(intel_pt_insn)) 864 goto out; 865 /* Check for emulated ptwrite */ 866 offs = offset + intel_pt_insn->length; 867 eptw = intel_pt_emulated_ptwrite(al.map->dso, machine, offs); 868 intel_pt_insn->emulated_ptwrite = eptw; 869 goto out; 870 } 871 872 if (max_insn_cnt && insn_cnt >= max_insn_cnt) 873 goto out_no_cache; 874 875 *ip += intel_pt_insn->length; 876 877 if (to_ip && *ip == to_ip) { 878 intel_pt_insn->length = 0; 879 goto out_no_cache; 880 } 881 882 if (*ip >= al.map->end) 883 break; 884 885 offset += intel_pt_insn->length; 886 } 887 one_map = false; 888 } 889 out: 890 *insn_cnt_ptr = insn_cnt; 891 892 if (!one_map) 893 goto out_no_cache; 894 895 /* 896 * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate 897 * entries. 898 */ 899 if (to_ip) { 900 struct intel_pt_cache_entry *e; 901 902 e = intel_pt_cache_lookup(al.map->dso, machine, start_offset); 903 if (e) 904 return 0; 905 } 906 907 /* Ignore cache errors */ 908 intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt, 909 *ip - start_ip, intel_pt_insn); 910 911 return 0; 912 913 out_no_cache: 914 *insn_cnt_ptr = insn_cnt; 915 return 0; 916 } 917 918 static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip, 919 uint64_t offset, const char *filename) 920 { 921 struct addr_filter *filt; 922 bool have_filter = false; 923 bool hit_tracestop = false; 924 bool hit_filter = false; 925 926 list_for_each_entry(filt, &pt->filts.head, list) { 927 if (filt->start) 928 have_filter = true; 929 930 if ((filename && !filt->filename) || 931 (!filename && filt->filename) || 932 (filename && strcmp(filename, filt->filename))) 933 continue; 934 935 if (!(offset >= filt->addr && offset < filt->addr + filt->size)) 936 continue; 937 938 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n", 939 ip, offset, filename ? filename : "[kernel]", 940 filt->start ? "filter" : "stop", 941 filt->addr, filt->size); 942 943 if (filt->start) 944 hit_filter = true; 945 else 946 hit_tracestop = true; 947 } 948 949 if (!hit_tracestop && !hit_filter) 950 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n", 951 ip, offset, filename ? filename : "[kernel]"); 952 953 return hit_tracestop || (have_filter && !hit_filter); 954 } 955 956 static int __intel_pt_pgd_ip(uint64_t ip, void *data) 957 { 958 struct intel_pt_queue *ptq = data; 959 struct thread *thread; 960 struct addr_location al; 961 u8 cpumode; 962 u64 offset; 963 964 if (ptq->state->to_nr) { 965 if (intel_pt_guest_kernel_ip(ip)) 966 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL); 967 /* No support for decoding guest user space */ 968 return -EINVAL; 969 } else if (ip >= ptq->pt->kernel_start) { 970 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL); 971 } 972 973 cpumode = PERF_RECORD_MISC_USER; 974 975 thread = ptq->thread; 976 if (!thread) 977 return -EINVAL; 978 979 if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso) 980 return -EINVAL; 981 982 offset = al.map->map_ip(al.map, ip); 983 984 return intel_pt_match_pgd_ip(ptq->pt, ip, offset, 985 al.map->dso->long_name); 986 } 987 988 static bool intel_pt_pgd_ip(uint64_t ip, void *data) 989 { 990 return __intel_pt_pgd_ip(ip, data) > 0; 991 } 992 993 static bool intel_pt_get_config(struct intel_pt *pt, 994 struct perf_event_attr *attr, u64 *config) 995 { 996 if (attr->type == pt->pmu_type) { 997 if (config) 998 *config = attr->config; 999 return true; 1000 } 1001 1002 return false; 1003 } 1004 1005 static bool intel_pt_exclude_kernel(struct intel_pt *pt) 1006 { 1007 struct evsel *evsel; 1008 1009 evlist__for_each_entry(pt->session->evlist, evsel) { 1010 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) && 1011 !evsel->core.attr.exclude_kernel) 1012 return false; 1013 } 1014 return true; 1015 } 1016 1017 static bool intel_pt_return_compression(struct intel_pt *pt) 1018 { 1019 struct evsel *evsel; 1020 u64 config; 1021 1022 if (!pt->noretcomp_bit) 1023 return true; 1024 1025 evlist__for_each_entry(pt->session->evlist, evsel) { 1026 if (intel_pt_get_config(pt, &evsel->core.attr, &config) && 1027 (config & pt->noretcomp_bit)) 1028 return false; 1029 } 1030 return true; 1031 } 1032 1033 static bool intel_pt_branch_enable(struct intel_pt *pt) 1034 { 1035 struct evsel *evsel; 1036 u64 config; 1037 1038 evlist__for_each_entry(pt->session->evlist, evsel) { 1039 if (intel_pt_get_config(pt, &evsel->core.attr, &config) && 1040 (config & INTEL_PT_CFG_PASS_THRU) && 1041 !(config & INTEL_PT_CFG_BRANCH_EN)) 1042 return false; 1043 } 1044 return true; 1045 } 1046 1047 static bool intel_pt_disabled_tnt(struct intel_pt *pt) 1048 { 1049 struct evsel *evsel; 1050 u64 config; 1051 1052 evlist__for_each_entry(pt->session->evlist, evsel) { 1053 if (intel_pt_get_config(pt, &evsel->core.attr, &config) && 1054 config & INTEL_PT_CFG_TNT_DIS) 1055 return true; 1056 } 1057 return false; 1058 } 1059 1060 static unsigned int intel_pt_mtc_period(struct intel_pt *pt) 1061 { 1062 struct evsel *evsel; 1063 unsigned int shift; 1064 u64 config; 1065 1066 if (!pt->mtc_freq_bits) 1067 return 0; 1068 1069 for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++) 1070 config >>= 1; 1071 1072 evlist__for_each_entry(pt->session->evlist, evsel) { 1073 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) 1074 return (config & pt->mtc_freq_bits) >> shift; 1075 } 1076 return 0; 1077 } 1078 1079 static bool intel_pt_timeless_decoding(struct intel_pt *pt) 1080 { 1081 struct evsel *evsel; 1082 bool timeless_decoding = true; 1083 u64 config; 1084 1085 if (!pt->tsc_bit || !pt->cap_user_time_zero || pt->synth_opts.timeless_decoding) 1086 return true; 1087 1088 evlist__for_each_entry(pt->session->evlist, evsel) { 1089 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_TIME)) 1090 return true; 1091 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) { 1092 if (config & pt->tsc_bit) 1093 timeless_decoding = false; 1094 else 1095 return true; 1096 } 1097 } 1098 return timeless_decoding; 1099 } 1100 1101 static bool intel_pt_tracing_kernel(struct intel_pt *pt) 1102 { 1103 struct evsel *evsel; 1104 1105 evlist__for_each_entry(pt->session->evlist, evsel) { 1106 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) && 1107 !evsel->core.attr.exclude_kernel) 1108 return true; 1109 } 1110 return false; 1111 } 1112 1113 static bool intel_pt_have_tsc(struct intel_pt *pt) 1114 { 1115 struct evsel *evsel; 1116 bool have_tsc = false; 1117 u64 config; 1118 1119 if (!pt->tsc_bit) 1120 return false; 1121 1122 evlist__for_each_entry(pt->session->evlist, evsel) { 1123 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) { 1124 if (config & pt->tsc_bit) 1125 have_tsc = true; 1126 else 1127 return false; 1128 } 1129 } 1130 return have_tsc; 1131 } 1132 1133 static bool intel_pt_have_mtc(struct intel_pt *pt) 1134 { 1135 struct evsel *evsel; 1136 u64 config; 1137 1138 evlist__for_each_entry(pt->session->evlist, evsel) { 1139 if (intel_pt_get_config(pt, &evsel->core.attr, &config) && 1140 (config & pt->mtc_bit)) 1141 return true; 1142 } 1143 return false; 1144 } 1145 1146 static bool intel_pt_sampling_mode(struct intel_pt *pt) 1147 { 1148 struct evsel *evsel; 1149 1150 evlist__for_each_entry(pt->session->evlist, evsel) { 1151 if ((evsel->core.attr.sample_type & PERF_SAMPLE_AUX) && 1152 evsel->core.attr.aux_sample_size) 1153 return true; 1154 } 1155 return false; 1156 } 1157 1158 static u64 intel_pt_ctl(struct intel_pt *pt) 1159 { 1160 struct evsel *evsel; 1161 u64 config; 1162 1163 evlist__for_each_entry(pt->session->evlist, evsel) { 1164 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) 1165 return config; 1166 } 1167 return 0; 1168 } 1169 1170 static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns) 1171 { 1172 u64 quot, rem; 1173 1174 quot = ns / pt->tc.time_mult; 1175 rem = ns % pt->tc.time_mult; 1176 return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) / 1177 pt->tc.time_mult; 1178 } 1179 1180 static struct ip_callchain *intel_pt_alloc_chain(struct intel_pt *pt) 1181 { 1182 size_t sz = sizeof(struct ip_callchain); 1183 1184 /* Add 1 to callchain_sz for callchain context */ 1185 sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64); 1186 return zalloc(sz); 1187 } 1188 1189 static int intel_pt_callchain_init(struct intel_pt *pt) 1190 { 1191 struct evsel *evsel; 1192 1193 evlist__for_each_entry(pt->session->evlist, evsel) { 1194 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_CALLCHAIN)) 1195 evsel->synth_sample_type |= PERF_SAMPLE_CALLCHAIN; 1196 } 1197 1198 pt->chain = intel_pt_alloc_chain(pt); 1199 if (!pt->chain) 1200 return -ENOMEM; 1201 1202 return 0; 1203 } 1204 1205 static void intel_pt_add_callchain(struct intel_pt *pt, 1206 struct perf_sample *sample) 1207 { 1208 struct thread *thread = machine__findnew_thread(pt->machine, 1209 sample->pid, 1210 sample->tid); 1211 1212 thread_stack__sample_late(thread, sample->cpu, pt->chain, 1213 pt->synth_opts.callchain_sz + 1, sample->ip, 1214 pt->kernel_start); 1215 1216 sample->callchain = pt->chain; 1217 } 1218 1219 static struct branch_stack *intel_pt_alloc_br_stack(unsigned int entry_cnt) 1220 { 1221 size_t sz = sizeof(struct branch_stack); 1222 1223 sz += entry_cnt * sizeof(struct branch_entry); 1224 return zalloc(sz); 1225 } 1226 1227 static int intel_pt_br_stack_init(struct intel_pt *pt) 1228 { 1229 struct evsel *evsel; 1230 1231 evlist__for_each_entry(pt->session->evlist, evsel) { 1232 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_BRANCH_STACK)) 1233 evsel->synth_sample_type |= PERF_SAMPLE_BRANCH_STACK; 1234 } 1235 1236 pt->br_stack = intel_pt_alloc_br_stack(pt->br_stack_sz); 1237 if (!pt->br_stack) 1238 return -ENOMEM; 1239 1240 return 0; 1241 } 1242 1243 static void intel_pt_add_br_stack(struct intel_pt *pt, 1244 struct perf_sample *sample) 1245 { 1246 struct thread *thread = machine__findnew_thread(pt->machine, 1247 sample->pid, 1248 sample->tid); 1249 1250 thread_stack__br_sample_late(thread, sample->cpu, pt->br_stack, 1251 pt->br_stack_sz, sample->ip, 1252 pt->kernel_start); 1253 1254 sample->branch_stack = pt->br_stack; 1255 } 1256 1257 /* INTEL_PT_LBR_0, INTEL_PT_LBR_1 and INTEL_PT_LBR_2 */ 1258 #define LBRS_MAX (INTEL_PT_BLK_ITEM_ID_CNT * 3U) 1259 1260 static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt, 1261 unsigned int queue_nr) 1262 { 1263 struct intel_pt_params params = { .get_trace = 0, }; 1264 struct perf_env *env = pt->machine->env; 1265 struct intel_pt_queue *ptq; 1266 1267 ptq = zalloc(sizeof(struct intel_pt_queue)); 1268 if (!ptq) 1269 return NULL; 1270 1271 if (pt->synth_opts.callchain) { 1272 ptq->chain = intel_pt_alloc_chain(pt); 1273 if (!ptq->chain) 1274 goto out_free; 1275 } 1276 1277 if (pt->synth_opts.last_branch || pt->synth_opts.other_events) { 1278 unsigned int entry_cnt = max(LBRS_MAX, pt->br_stack_sz); 1279 1280 ptq->last_branch = intel_pt_alloc_br_stack(entry_cnt); 1281 if (!ptq->last_branch) 1282 goto out_free; 1283 } 1284 1285 ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE); 1286 if (!ptq->event_buf) 1287 goto out_free; 1288 1289 ptq->pt = pt; 1290 ptq->queue_nr = queue_nr; 1291 ptq->exclude_kernel = intel_pt_exclude_kernel(pt); 1292 ptq->pid = -1; 1293 ptq->tid = -1; 1294 ptq->cpu = -1; 1295 ptq->next_tid = -1; 1296 1297 params.get_trace = intel_pt_get_trace; 1298 params.walk_insn = intel_pt_walk_next_insn; 1299 params.lookahead = intel_pt_lookahead; 1300 params.findnew_vmcs_info = intel_pt_findnew_vmcs_info; 1301 params.data = ptq; 1302 params.return_compression = intel_pt_return_compression(pt); 1303 params.branch_enable = intel_pt_branch_enable(pt); 1304 params.ctl = intel_pt_ctl(pt); 1305 params.max_non_turbo_ratio = pt->max_non_turbo_ratio; 1306 params.mtc_period = intel_pt_mtc_period(pt); 1307 params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n; 1308 params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d; 1309 params.quick = pt->synth_opts.quick; 1310 params.vm_time_correlation = pt->synth_opts.vm_time_correlation; 1311 params.vm_tm_corr_dry_run = pt->synth_opts.vm_tm_corr_dry_run; 1312 params.first_timestamp = pt->first_timestamp; 1313 params.max_loops = pt->max_loops; 1314 1315 /* Cannot walk code without TNT, so force 'quick' mode */ 1316 if (params.branch_enable && intel_pt_disabled_tnt(pt) && !params.quick) 1317 params.quick = 1; 1318 1319 if (pt->filts.cnt > 0) 1320 params.pgd_ip = intel_pt_pgd_ip; 1321 1322 if (pt->synth_opts.instructions) { 1323 if (pt->synth_opts.period) { 1324 switch (pt->synth_opts.period_type) { 1325 case PERF_ITRACE_PERIOD_INSTRUCTIONS: 1326 params.period_type = 1327 INTEL_PT_PERIOD_INSTRUCTIONS; 1328 params.period = pt->synth_opts.period; 1329 break; 1330 case PERF_ITRACE_PERIOD_TICKS: 1331 params.period_type = INTEL_PT_PERIOD_TICKS; 1332 params.period = pt->synth_opts.period; 1333 break; 1334 case PERF_ITRACE_PERIOD_NANOSECS: 1335 params.period_type = INTEL_PT_PERIOD_TICKS; 1336 params.period = intel_pt_ns_to_ticks(pt, 1337 pt->synth_opts.period); 1338 break; 1339 default: 1340 break; 1341 } 1342 } 1343 1344 if (!params.period) { 1345 params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS; 1346 params.period = 1; 1347 } 1348 } 1349 1350 if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18)) 1351 params.flags |= INTEL_PT_FUP_WITH_NLIP; 1352 1353 ptq->decoder = intel_pt_decoder_new(¶ms); 1354 if (!ptq->decoder) 1355 goto out_free; 1356 1357 return ptq; 1358 1359 out_free: 1360 zfree(&ptq->event_buf); 1361 zfree(&ptq->last_branch); 1362 zfree(&ptq->chain); 1363 free(ptq); 1364 return NULL; 1365 } 1366 1367 static void intel_pt_free_queue(void *priv) 1368 { 1369 struct intel_pt_queue *ptq = priv; 1370 1371 if (!ptq) 1372 return; 1373 thread__zput(ptq->thread); 1374 thread__zput(ptq->guest_thread); 1375 thread__zput(ptq->unknown_guest_thread); 1376 intel_pt_decoder_free(ptq->decoder); 1377 zfree(&ptq->event_buf); 1378 zfree(&ptq->last_branch); 1379 zfree(&ptq->chain); 1380 free(ptq); 1381 } 1382 1383 static void intel_pt_first_timestamp(struct intel_pt *pt, u64 timestamp) 1384 { 1385 unsigned int i; 1386 1387 pt->first_timestamp = timestamp; 1388 1389 for (i = 0; i < pt->queues.nr_queues; i++) { 1390 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 1391 struct intel_pt_queue *ptq = queue->priv; 1392 1393 if (ptq && ptq->decoder) 1394 intel_pt_set_first_timestamp(ptq->decoder, timestamp); 1395 } 1396 } 1397 1398 static int intel_pt_get_guest_from_sideband(struct intel_pt_queue *ptq) 1399 { 1400 struct machines *machines = &ptq->pt->session->machines; 1401 struct machine *machine; 1402 pid_t machine_pid = ptq->pid; 1403 pid_t tid; 1404 int vcpu; 1405 1406 if (machine_pid <= 0) 1407 return 0; /* Not a guest machine */ 1408 1409 machine = machines__find(machines, machine_pid); 1410 if (!machine) 1411 return 0; /* Not a guest machine */ 1412 1413 if (ptq->guest_machine != machine) { 1414 ptq->guest_machine = NULL; 1415 thread__zput(ptq->guest_thread); 1416 thread__zput(ptq->unknown_guest_thread); 1417 1418 ptq->unknown_guest_thread = machine__find_thread(machine, 0, 0); 1419 if (!ptq->unknown_guest_thread) 1420 return -1; 1421 ptq->guest_machine = machine; 1422 } 1423 1424 vcpu = ptq->thread ? ptq->thread->guest_cpu : -1; 1425 if (vcpu < 0) 1426 return -1; 1427 1428 tid = machine__get_current_tid(machine, vcpu); 1429 1430 if (ptq->guest_thread && ptq->guest_thread->tid != tid) 1431 thread__zput(ptq->guest_thread); 1432 1433 if (!ptq->guest_thread) { 1434 ptq->guest_thread = machine__find_thread(machine, -1, tid); 1435 if (!ptq->guest_thread) 1436 return -1; 1437 } 1438 1439 ptq->guest_machine_pid = machine_pid; 1440 ptq->guest_pid = ptq->guest_thread->pid_; 1441 ptq->guest_tid = tid; 1442 ptq->vcpu = vcpu; 1443 1444 return 0; 1445 } 1446 1447 static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt, 1448 struct auxtrace_queue *queue) 1449 { 1450 struct intel_pt_queue *ptq = queue->priv; 1451 1452 if (queue->tid == -1 || pt->have_sched_switch) { 1453 ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu); 1454 if (ptq->tid == -1) 1455 ptq->pid = -1; 1456 thread__zput(ptq->thread); 1457 } 1458 1459 if (!ptq->thread && ptq->tid != -1) 1460 ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid); 1461 1462 if (ptq->thread) { 1463 ptq->pid = ptq->thread->pid_; 1464 if (queue->cpu == -1) 1465 ptq->cpu = ptq->thread->cpu; 1466 } 1467 1468 if (pt->have_guest_sideband && intel_pt_get_guest_from_sideband(ptq)) { 1469 ptq->guest_machine_pid = 0; 1470 ptq->guest_pid = -1; 1471 ptq->guest_tid = -1; 1472 ptq->vcpu = -1; 1473 } 1474 } 1475 1476 static void intel_pt_sample_flags(struct intel_pt_queue *ptq) 1477 { 1478 struct intel_pt *pt = ptq->pt; 1479 1480 ptq->insn_len = 0; 1481 if (ptq->state->flags & INTEL_PT_ABORT_TX) { 1482 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT; 1483 } else if (ptq->state->flags & INTEL_PT_ASYNC) { 1484 if (!ptq->state->to_ip) 1485 ptq->flags = PERF_IP_FLAG_BRANCH | 1486 PERF_IP_FLAG_TRACE_END; 1487 else if (ptq->state->from_nr && !ptq->state->to_nr) 1488 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | 1489 PERF_IP_FLAG_VMEXIT; 1490 else 1491 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | 1492 PERF_IP_FLAG_ASYNC | 1493 PERF_IP_FLAG_INTERRUPT; 1494 } else { 1495 if (ptq->state->from_ip) 1496 ptq->flags = intel_pt_insn_type(ptq->state->insn_op); 1497 else 1498 ptq->flags = PERF_IP_FLAG_BRANCH | 1499 PERF_IP_FLAG_TRACE_BEGIN; 1500 if (ptq->state->flags & INTEL_PT_IN_TX) 1501 ptq->flags |= PERF_IP_FLAG_IN_TX; 1502 ptq->insn_len = ptq->state->insn_len; 1503 memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ); 1504 } 1505 1506 if (ptq->state->type & INTEL_PT_TRACE_BEGIN) 1507 ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN; 1508 if (ptq->state->type & INTEL_PT_TRACE_END) 1509 ptq->flags |= PERF_IP_FLAG_TRACE_END; 1510 1511 if (pt->cap_event_trace) { 1512 if (ptq->state->type & INTEL_PT_IFLAG_CHG) { 1513 if (!ptq->state->from_iflag) 1514 ptq->flags |= PERF_IP_FLAG_INTR_DISABLE; 1515 if (ptq->state->from_iflag != ptq->state->to_iflag) 1516 ptq->flags |= PERF_IP_FLAG_INTR_TOGGLE; 1517 } else if (!ptq->state->to_iflag) { 1518 ptq->flags |= PERF_IP_FLAG_INTR_DISABLE; 1519 } 1520 } 1521 } 1522 1523 static void intel_pt_setup_time_range(struct intel_pt *pt, 1524 struct intel_pt_queue *ptq) 1525 { 1526 if (!pt->range_cnt) 1527 return; 1528 1529 ptq->sel_timestamp = pt->time_ranges[0].start; 1530 ptq->sel_idx = 0; 1531 1532 if (ptq->sel_timestamp) { 1533 ptq->sel_start = true; 1534 } else { 1535 ptq->sel_timestamp = pt->time_ranges[0].end; 1536 ptq->sel_start = false; 1537 } 1538 } 1539 1540 static int intel_pt_setup_queue(struct intel_pt *pt, 1541 struct auxtrace_queue *queue, 1542 unsigned int queue_nr) 1543 { 1544 struct intel_pt_queue *ptq = queue->priv; 1545 1546 if (list_empty(&queue->head)) 1547 return 0; 1548 1549 if (!ptq) { 1550 ptq = intel_pt_alloc_queue(pt, queue_nr); 1551 if (!ptq) 1552 return -ENOMEM; 1553 queue->priv = ptq; 1554 1555 if (queue->cpu != -1) 1556 ptq->cpu = queue->cpu; 1557 ptq->tid = queue->tid; 1558 1559 ptq->cbr_seen = UINT_MAX; 1560 1561 if (pt->sampling_mode && !pt->snapshot_mode && 1562 pt->timeless_decoding) 1563 ptq->step_through_buffers = true; 1564 1565 ptq->sync_switch = pt->sync_switch; 1566 1567 intel_pt_setup_time_range(pt, ptq); 1568 } 1569 1570 if (!ptq->on_heap && 1571 (!ptq->sync_switch || 1572 ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) { 1573 const struct intel_pt_state *state; 1574 int ret; 1575 1576 if (pt->timeless_decoding) 1577 return 0; 1578 1579 intel_pt_log("queue %u getting timestamp\n", queue_nr); 1580 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n", 1581 queue_nr, ptq->cpu, ptq->pid, ptq->tid); 1582 1583 if (ptq->sel_start && ptq->sel_timestamp) { 1584 ret = intel_pt_fast_forward(ptq->decoder, 1585 ptq->sel_timestamp); 1586 if (ret) 1587 return ret; 1588 } 1589 1590 while (1) { 1591 state = intel_pt_decode(ptq->decoder); 1592 if (state->err) { 1593 if (state->err == INTEL_PT_ERR_NODATA) { 1594 intel_pt_log("queue %u has no timestamp\n", 1595 queue_nr); 1596 return 0; 1597 } 1598 continue; 1599 } 1600 if (state->timestamp) 1601 break; 1602 } 1603 1604 ptq->timestamp = state->timestamp; 1605 intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n", 1606 queue_nr, ptq->timestamp); 1607 ptq->state = state; 1608 ptq->have_sample = true; 1609 if (ptq->sel_start && ptq->sel_timestamp && 1610 ptq->timestamp < ptq->sel_timestamp) 1611 ptq->have_sample = false; 1612 intel_pt_sample_flags(ptq); 1613 ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp); 1614 if (ret) 1615 return ret; 1616 ptq->on_heap = true; 1617 } 1618 1619 return 0; 1620 } 1621 1622 static int intel_pt_setup_queues(struct intel_pt *pt) 1623 { 1624 unsigned int i; 1625 int ret; 1626 1627 for (i = 0; i < pt->queues.nr_queues; i++) { 1628 ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i); 1629 if (ret) 1630 return ret; 1631 } 1632 return 0; 1633 } 1634 1635 static inline bool intel_pt_skip_event(struct intel_pt *pt) 1636 { 1637 return pt->synth_opts.initial_skip && 1638 pt->num_events++ < pt->synth_opts.initial_skip; 1639 } 1640 1641 /* 1642 * Cannot count CBR as skipped because it won't go away until cbr == cbr_seen. 1643 * Also ensure CBR is first non-skipped event by allowing for 4 more samples 1644 * from this decoder state. 1645 */ 1646 static inline bool intel_pt_skip_cbr_event(struct intel_pt *pt) 1647 { 1648 return pt->synth_opts.initial_skip && 1649 pt->num_events + 4 < pt->synth_opts.initial_skip; 1650 } 1651 1652 static void intel_pt_prep_a_sample(struct intel_pt_queue *ptq, 1653 union perf_event *event, 1654 struct perf_sample *sample) 1655 { 1656 event->sample.header.type = PERF_RECORD_SAMPLE; 1657 event->sample.header.size = sizeof(struct perf_event_header); 1658 1659 sample->pid = ptq->pid; 1660 sample->tid = ptq->tid; 1661 1662 if (ptq->pt->have_guest_sideband) { 1663 if ((ptq->state->from_ip && ptq->state->from_nr) || 1664 (ptq->state->to_ip && ptq->state->to_nr)) { 1665 sample->pid = ptq->guest_pid; 1666 sample->tid = ptq->guest_tid; 1667 sample->machine_pid = ptq->guest_machine_pid; 1668 sample->vcpu = ptq->vcpu; 1669 } 1670 } 1671 1672 sample->cpu = ptq->cpu; 1673 sample->insn_len = ptq->insn_len; 1674 memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ); 1675 } 1676 1677 static void intel_pt_prep_b_sample(struct intel_pt *pt, 1678 struct intel_pt_queue *ptq, 1679 union perf_event *event, 1680 struct perf_sample *sample) 1681 { 1682 intel_pt_prep_a_sample(ptq, event, sample); 1683 1684 if (!pt->timeless_decoding) 1685 sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc); 1686 1687 sample->ip = ptq->state->from_ip; 1688 sample->addr = ptq->state->to_ip; 1689 sample->cpumode = intel_pt_cpumode(ptq, sample->ip, sample->addr); 1690 sample->period = 1; 1691 sample->flags = ptq->flags; 1692 1693 event->sample.header.misc = sample->cpumode; 1694 } 1695 1696 static int intel_pt_inject_event(union perf_event *event, 1697 struct perf_sample *sample, u64 type) 1698 { 1699 event->header.size = perf_event__sample_event_size(sample, type, 0); 1700 return perf_event__synthesize_sample(event, type, 0, sample); 1701 } 1702 1703 static inline int intel_pt_opt_inject(struct intel_pt *pt, 1704 union perf_event *event, 1705 struct perf_sample *sample, u64 type) 1706 { 1707 if (!pt->synth_opts.inject) 1708 return 0; 1709 1710 return intel_pt_inject_event(event, sample, type); 1711 } 1712 1713 static int intel_pt_deliver_synth_event(struct intel_pt *pt, 1714 union perf_event *event, 1715 struct perf_sample *sample, u64 type) 1716 { 1717 int ret; 1718 1719 ret = intel_pt_opt_inject(pt, event, sample, type); 1720 if (ret) 1721 return ret; 1722 1723 ret = perf_session__deliver_synth_event(pt->session, event, sample); 1724 if (ret) 1725 pr_err("Intel PT: failed to deliver event, error %d\n", ret); 1726 1727 return ret; 1728 } 1729 1730 static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq) 1731 { 1732 struct intel_pt *pt = ptq->pt; 1733 union perf_event *event = ptq->event_buf; 1734 struct perf_sample sample = { .ip = 0, }; 1735 struct dummy_branch_stack { 1736 u64 nr; 1737 u64 hw_idx; 1738 struct branch_entry entries; 1739 } dummy_bs; 1740 1741 if (pt->branches_filter && !(pt->branches_filter & ptq->flags)) 1742 return 0; 1743 1744 if (intel_pt_skip_event(pt)) 1745 return 0; 1746 1747 intel_pt_prep_b_sample(pt, ptq, event, &sample); 1748 1749 sample.id = ptq->pt->branches_id; 1750 sample.stream_id = ptq->pt->branches_id; 1751 1752 /* 1753 * perf report cannot handle events without a branch stack when using 1754 * SORT_MODE__BRANCH so make a dummy one. 1755 */ 1756 if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) { 1757 dummy_bs = (struct dummy_branch_stack){ 1758 .nr = 1, 1759 .hw_idx = -1ULL, 1760 .entries = { 1761 .from = sample.ip, 1762 .to = sample.addr, 1763 }, 1764 }; 1765 sample.branch_stack = (struct branch_stack *)&dummy_bs; 1766 } 1767 1768 if (ptq->sample_ipc) 1769 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_br_cyc_cnt; 1770 if (sample.cyc_cnt) { 1771 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_br_insn_cnt; 1772 ptq->last_br_insn_cnt = ptq->ipc_insn_cnt; 1773 ptq->last_br_cyc_cnt = ptq->ipc_cyc_cnt; 1774 } 1775 1776 return intel_pt_deliver_synth_event(pt, event, &sample, 1777 pt->branches_sample_type); 1778 } 1779 1780 static void intel_pt_prep_sample(struct intel_pt *pt, 1781 struct intel_pt_queue *ptq, 1782 union perf_event *event, 1783 struct perf_sample *sample) 1784 { 1785 intel_pt_prep_b_sample(pt, ptq, event, sample); 1786 1787 if (pt->synth_opts.callchain) { 1788 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain, 1789 pt->synth_opts.callchain_sz + 1, 1790 sample->ip, pt->kernel_start); 1791 sample->callchain = ptq->chain; 1792 } 1793 1794 if (pt->synth_opts.last_branch) { 1795 thread_stack__br_sample(ptq->thread, ptq->cpu, ptq->last_branch, 1796 pt->br_stack_sz); 1797 sample->branch_stack = ptq->last_branch; 1798 } 1799 } 1800 1801 static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq) 1802 { 1803 struct intel_pt *pt = ptq->pt; 1804 union perf_event *event = ptq->event_buf; 1805 struct perf_sample sample = { .ip = 0, }; 1806 1807 if (intel_pt_skip_event(pt)) 1808 return 0; 1809 1810 intel_pt_prep_sample(pt, ptq, event, &sample); 1811 1812 sample.id = ptq->pt->instructions_id; 1813 sample.stream_id = ptq->pt->instructions_id; 1814 if (pt->synth_opts.quick) 1815 sample.period = 1; 1816 else 1817 sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt; 1818 1819 if (ptq->sample_ipc) 1820 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_in_cyc_cnt; 1821 if (sample.cyc_cnt) { 1822 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_in_insn_cnt; 1823 ptq->last_in_insn_cnt = ptq->ipc_insn_cnt; 1824 ptq->last_in_cyc_cnt = ptq->ipc_cyc_cnt; 1825 } 1826 1827 ptq->last_insn_cnt = ptq->state->tot_insn_cnt; 1828 1829 return intel_pt_deliver_synth_event(pt, event, &sample, 1830 pt->instructions_sample_type); 1831 } 1832 1833 static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq) 1834 { 1835 struct intel_pt *pt = ptq->pt; 1836 union perf_event *event = ptq->event_buf; 1837 struct perf_sample sample = { .ip = 0, }; 1838 1839 if (intel_pt_skip_event(pt)) 1840 return 0; 1841 1842 intel_pt_prep_sample(pt, ptq, event, &sample); 1843 1844 sample.id = ptq->pt->transactions_id; 1845 sample.stream_id = ptq->pt->transactions_id; 1846 1847 return intel_pt_deliver_synth_event(pt, event, &sample, 1848 pt->transactions_sample_type); 1849 } 1850 1851 static void intel_pt_prep_p_sample(struct intel_pt *pt, 1852 struct intel_pt_queue *ptq, 1853 union perf_event *event, 1854 struct perf_sample *sample) 1855 { 1856 intel_pt_prep_sample(pt, ptq, event, sample); 1857 1858 /* 1859 * Zero IP is used to mean "trace start" but that is not the case for 1860 * power or PTWRITE events with no IP, so clear the flags. 1861 */ 1862 if (!sample->ip) 1863 sample->flags = 0; 1864 } 1865 1866 static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq) 1867 { 1868 struct intel_pt *pt = ptq->pt; 1869 union perf_event *event = ptq->event_buf; 1870 struct perf_sample sample = { .ip = 0, }; 1871 struct perf_synth_intel_ptwrite raw; 1872 1873 if (intel_pt_skip_event(pt)) 1874 return 0; 1875 1876 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1877 1878 sample.id = ptq->pt->ptwrites_id; 1879 sample.stream_id = ptq->pt->ptwrites_id; 1880 1881 raw.flags = 0; 1882 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); 1883 raw.payload = cpu_to_le64(ptq->state->ptw_payload); 1884 1885 sample.raw_size = perf_synth__raw_size(raw); 1886 sample.raw_data = perf_synth__raw_data(&raw); 1887 1888 return intel_pt_deliver_synth_event(pt, event, &sample, 1889 pt->ptwrites_sample_type); 1890 } 1891 1892 static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq) 1893 { 1894 struct intel_pt *pt = ptq->pt; 1895 union perf_event *event = ptq->event_buf; 1896 struct perf_sample sample = { .ip = 0, }; 1897 struct perf_synth_intel_cbr raw; 1898 u32 flags; 1899 1900 if (intel_pt_skip_cbr_event(pt)) 1901 return 0; 1902 1903 ptq->cbr_seen = ptq->state->cbr; 1904 1905 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1906 1907 sample.id = ptq->pt->cbr_id; 1908 sample.stream_id = ptq->pt->cbr_id; 1909 1910 flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16); 1911 raw.flags = cpu_to_le32(flags); 1912 raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz); 1913 raw.reserved3 = 0; 1914 1915 sample.raw_size = perf_synth__raw_size(raw); 1916 sample.raw_data = perf_synth__raw_data(&raw); 1917 1918 return intel_pt_deliver_synth_event(pt, event, &sample, 1919 pt->pwr_events_sample_type); 1920 } 1921 1922 static int intel_pt_synth_psb_sample(struct intel_pt_queue *ptq) 1923 { 1924 struct intel_pt *pt = ptq->pt; 1925 union perf_event *event = ptq->event_buf; 1926 struct perf_sample sample = { .ip = 0, }; 1927 struct perf_synth_intel_psb raw; 1928 1929 if (intel_pt_skip_event(pt)) 1930 return 0; 1931 1932 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1933 1934 sample.id = ptq->pt->psb_id; 1935 sample.stream_id = ptq->pt->psb_id; 1936 sample.flags = 0; 1937 1938 raw.reserved = 0; 1939 raw.offset = ptq->state->psb_offset; 1940 1941 sample.raw_size = perf_synth__raw_size(raw); 1942 sample.raw_data = perf_synth__raw_data(&raw); 1943 1944 return intel_pt_deliver_synth_event(pt, event, &sample, 1945 pt->pwr_events_sample_type); 1946 } 1947 1948 static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq) 1949 { 1950 struct intel_pt *pt = ptq->pt; 1951 union perf_event *event = ptq->event_buf; 1952 struct perf_sample sample = { .ip = 0, }; 1953 struct perf_synth_intel_mwait raw; 1954 1955 if (intel_pt_skip_event(pt)) 1956 return 0; 1957 1958 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1959 1960 sample.id = ptq->pt->mwait_id; 1961 sample.stream_id = ptq->pt->mwait_id; 1962 1963 raw.reserved = 0; 1964 raw.payload = cpu_to_le64(ptq->state->mwait_payload); 1965 1966 sample.raw_size = perf_synth__raw_size(raw); 1967 sample.raw_data = perf_synth__raw_data(&raw); 1968 1969 return intel_pt_deliver_synth_event(pt, event, &sample, 1970 pt->pwr_events_sample_type); 1971 } 1972 1973 static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq) 1974 { 1975 struct intel_pt *pt = ptq->pt; 1976 union perf_event *event = ptq->event_buf; 1977 struct perf_sample sample = { .ip = 0, }; 1978 struct perf_synth_intel_pwre raw; 1979 1980 if (intel_pt_skip_event(pt)) 1981 return 0; 1982 1983 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1984 1985 sample.id = ptq->pt->pwre_id; 1986 sample.stream_id = ptq->pt->pwre_id; 1987 1988 raw.reserved = 0; 1989 raw.payload = cpu_to_le64(ptq->state->pwre_payload); 1990 1991 sample.raw_size = perf_synth__raw_size(raw); 1992 sample.raw_data = perf_synth__raw_data(&raw); 1993 1994 return intel_pt_deliver_synth_event(pt, event, &sample, 1995 pt->pwr_events_sample_type); 1996 } 1997 1998 static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq) 1999 { 2000 struct intel_pt *pt = ptq->pt; 2001 union perf_event *event = ptq->event_buf; 2002 struct perf_sample sample = { .ip = 0, }; 2003 struct perf_synth_intel_exstop raw; 2004 2005 if (intel_pt_skip_event(pt)) 2006 return 0; 2007 2008 intel_pt_prep_p_sample(pt, ptq, event, &sample); 2009 2010 sample.id = ptq->pt->exstop_id; 2011 sample.stream_id = ptq->pt->exstop_id; 2012 2013 raw.flags = 0; 2014 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); 2015 2016 sample.raw_size = perf_synth__raw_size(raw); 2017 sample.raw_data = perf_synth__raw_data(&raw); 2018 2019 return intel_pt_deliver_synth_event(pt, event, &sample, 2020 pt->pwr_events_sample_type); 2021 } 2022 2023 static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq) 2024 { 2025 struct intel_pt *pt = ptq->pt; 2026 union perf_event *event = ptq->event_buf; 2027 struct perf_sample sample = { .ip = 0, }; 2028 struct perf_synth_intel_pwrx raw; 2029 2030 if (intel_pt_skip_event(pt)) 2031 return 0; 2032 2033 intel_pt_prep_p_sample(pt, ptq, event, &sample); 2034 2035 sample.id = ptq->pt->pwrx_id; 2036 sample.stream_id = ptq->pt->pwrx_id; 2037 2038 raw.reserved = 0; 2039 raw.payload = cpu_to_le64(ptq->state->pwrx_payload); 2040 2041 sample.raw_size = perf_synth__raw_size(raw); 2042 sample.raw_data = perf_synth__raw_data(&raw); 2043 2044 return intel_pt_deliver_synth_event(pt, event, &sample, 2045 pt->pwr_events_sample_type); 2046 } 2047 2048 /* 2049 * PEBS gp_regs array indexes plus 1 so that 0 means not present. Refer 2050 * intel_pt_add_gp_regs(). 2051 */ 2052 static const int pebs_gp_regs[] = { 2053 [PERF_REG_X86_FLAGS] = 1, 2054 [PERF_REG_X86_IP] = 2, 2055 [PERF_REG_X86_AX] = 3, 2056 [PERF_REG_X86_CX] = 4, 2057 [PERF_REG_X86_DX] = 5, 2058 [PERF_REG_X86_BX] = 6, 2059 [PERF_REG_X86_SP] = 7, 2060 [PERF_REG_X86_BP] = 8, 2061 [PERF_REG_X86_SI] = 9, 2062 [PERF_REG_X86_DI] = 10, 2063 [PERF_REG_X86_R8] = 11, 2064 [PERF_REG_X86_R9] = 12, 2065 [PERF_REG_X86_R10] = 13, 2066 [PERF_REG_X86_R11] = 14, 2067 [PERF_REG_X86_R12] = 15, 2068 [PERF_REG_X86_R13] = 16, 2069 [PERF_REG_X86_R14] = 17, 2070 [PERF_REG_X86_R15] = 18, 2071 }; 2072 2073 static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos, 2074 const struct intel_pt_blk_items *items, 2075 u64 regs_mask) 2076 { 2077 const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS]; 2078 u32 mask = items->mask[INTEL_PT_GP_REGS_POS]; 2079 u32 bit; 2080 int i; 2081 2082 for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) { 2083 /* Get the PEBS gp_regs array index */ 2084 int n = pebs_gp_regs[i] - 1; 2085 2086 if (n < 0) 2087 continue; 2088 /* 2089 * Add only registers that were requested (i.e. 'regs_mask') and 2090 * that were provided (i.e. 'mask'), and update the resulting 2091 * mask (i.e. 'intr_regs->mask') accordingly. 2092 */ 2093 if (mask & 1 << n && regs_mask & bit) { 2094 intr_regs->mask |= bit; 2095 *pos++ = gp_regs[n]; 2096 } 2097 } 2098 2099 return pos; 2100 } 2101 2102 #ifndef PERF_REG_X86_XMM0 2103 #define PERF_REG_X86_XMM0 32 2104 #endif 2105 2106 static void intel_pt_add_xmm(struct regs_dump *intr_regs, u64 *pos, 2107 const struct intel_pt_blk_items *items, 2108 u64 regs_mask) 2109 { 2110 u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0); 2111 const u64 *xmm = items->xmm; 2112 2113 /* 2114 * If there are any XMM registers, then there should be all of them. 2115 * Nevertheless, follow the logic to add only registers that were 2116 * requested (i.e. 'regs_mask') and that were provided (i.e. 'mask'), 2117 * and update the resulting mask (i.e. 'intr_regs->mask') accordingly. 2118 */ 2119 intr_regs->mask |= (u64)mask << PERF_REG_X86_XMM0; 2120 2121 for (; mask; mask >>= 1, xmm++) { 2122 if (mask & 1) 2123 *pos++ = *xmm; 2124 } 2125 } 2126 2127 #define LBR_INFO_MISPRED (1ULL << 63) 2128 #define LBR_INFO_IN_TX (1ULL << 62) 2129 #define LBR_INFO_ABORT (1ULL << 61) 2130 #define LBR_INFO_CYCLES 0xffff 2131 2132 /* Refer kernel's intel_pmu_store_pebs_lbrs() */ 2133 static u64 intel_pt_lbr_flags(u64 info) 2134 { 2135 union { 2136 struct branch_flags flags; 2137 u64 result; 2138 } u; 2139 2140 u.result = 0; 2141 u.flags.mispred = !!(info & LBR_INFO_MISPRED); 2142 u.flags.predicted = !(info & LBR_INFO_MISPRED); 2143 u.flags.in_tx = !!(info & LBR_INFO_IN_TX); 2144 u.flags.abort = !!(info & LBR_INFO_ABORT); 2145 u.flags.cycles = info & LBR_INFO_CYCLES; 2146 2147 return u.result; 2148 } 2149 2150 static void intel_pt_add_lbrs(struct branch_stack *br_stack, 2151 const struct intel_pt_blk_items *items) 2152 { 2153 u64 *to; 2154 int i; 2155 2156 br_stack->nr = 0; 2157 2158 to = &br_stack->entries[0].from; 2159 2160 for (i = INTEL_PT_LBR_0_POS; i <= INTEL_PT_LBR_2_POS; i++) { 2161 u32 mask = items->mask[i]; 2162 const u64 *from = items->val[i]; 2163 2164 for (; mask; mask >>= 3, from += 3) { 2165 if ((mask & 7) == 7) { 2166 *to++ = from[0]; 2167 *to++ = from[1]; 2168 *to++ = intel_pt_lbr_flags(from[2]); 2169 br_stack->nr += 1; 2170 } 2171 } 2172 } 2173 } 2174 2175 static int intel_pt_do_synth_pebs_sample(struct intel_pt_queue *ptq, struct evsel *evsel, u64 id) 2176 { 2177 const struct intel_pt_blk_items *items = &ptq->state->items; 2178 struct perf_sample sample = { .ip = 0, }; 2179 union perf_event *event = ptq->event_buf; 2180 struct intel_pt *pt = ptq->pt; 2181 u64 sample_type = evsel->core.attr.sample_type; 2182 u8 cpumode; 2183 u64 regs[8 * sizeof(sample.intr_regs.mask)]; 2184 2185 if (intel_pt_skip_event(pt)) 2186 return 0; 2187 2188 intel_pt_prep_a_sample(ptq, event, &sample); 2189 2190 sample.id = id; 2191 sample.stream_id = id; 2192 2193 if (!evsel->core.attr.freq) 2194 sample.period = evsel->core.attr.sample_period; 2195 2196 /* No support for non-zero CS base */ 2197 if (items->has_ip) 2198 sample.ip = items->ip; 2199 else if (items->has_rip) 2200 sample.ip = items->rip; 2201 else 2202 sample.ip = ptq->state->from_ip; 2203 2204 cpumode = intel_pt_cpumode(ptq, sample.ip, 0); 2205 2206 event->sample.header.misc = cpumode | PERF_RECORD_MISC_EXACT_IP; 2207 2208 sample.cpumode = cpumode; 2209 2210 if (sample_type & PERF_SAMPLE_TIME) { 2211 u64 timestamp = 0; 2212 2213 if (items->has_timestamp) 2214 timestamp = items->timestamp; 2215 else if (!pt->timeless_decoding) 2216 timestamp = ptq->timestamp; 2217 if (timestamp) 2218 sample.time = tsc_to_perf_time(timestamp, &pt->tc); 2219 } 2220 2221 if (sample_type & PERF_SAMPLE_CALLCHAIN && 2222 pt->synth_opts.callchain) { 2223 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain, 2224 pt->synth_opts.callchain_sz, sample.ip, 2225 pt->kernel_start); 2226 sample.callchain = ptq->chain; 2227 } 2228 2229 if (sample_type & PERF_SAMPLE_REGS_INTR && 2230 (items->mask[INTEL_PT_GP_REGS_POS] || 2231 items->mask[INTEL_PT_XMM_POS])) { 2232 u64 regs_mask = evsel->core.attr.sample_regs_intr; 2233 u64 *pos; 2234 2235 sample.intr_regs.abi = items->is_32_bit ? 2236 PERF_SAMPLE_REGS_ABI_32 : 2237 PERF_SAMPLE_REGS_ABI_64; 2238 sample.intr_regs.regs = regs; 2239 2240 pos = intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask); 2241 2242 intel_pt_add_xmm(&sample.intr_regs, pos, items, regs_mask); 2243 } 2244 2245 if (sample_type & PERF_SAMPLE_BRANCH_STACK) { 2246 if (items->mask[INTEL_PT_LBR_0_POS] || 2247 items->mask[INTEL_PT_LBR_1_POS] || 2248 items->mask[INTEL_PT_LBR_2_POS]) { 2249 intel_pt_add_lbrs(ptq->last_branch, items); 2250 } else if (pt->synth_opts.last_branch) { 2251 thread_stack__br_sample(ptq->thread, ptq->cpu, 2252 ptq->last_branch, 2253 pt->br_stack_sz); 2254 } else { 2255 ptq->last_branch->nr = 0; 2256 } 2257 sample.branch_stack = ptq->last_branch; 2258 } 2259 2260 if (sample_type & PERF_SAMPLE_ADDR && items->has_mem_access_address) 2261 sample.addr = items->mem_access_address; 2262 2263 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) { 2264 /* 2265 * Refer kernel's setup_pebs_adaptive_sample_data() and 2266 * intel_hsw_weight(). 2267 */ 2268 if (items->has_mem_access_latency) { 2269 u64 weight = items->mem_access_latency >> 32; 2270 2271 /* 2272 * Starts from SPR, the mem access latency field 2273 * contains both cache latency [47:32] and instruction 2274 * latency [15:0]. The cache latency is the same as the 2275 * mem access latency on previous platforms. 2276 * 2277 * In practice, no memory access could last than 4G 2278 * cycles. Use latency >> 32 to distinguish the 2279 * different format of the mem access latency field. 2280 */ 2281 if (weight > 0) { 2282 sample.weight = weight & 0xffff; 2283 sample.ins_lat = items->mem_access_latency & 0xffff; 2284 } else 2285 sample.weight = items->mem_access_latency; 2286 } 2287 if (!sample.weight && items->has_tsx_aux_info) { 2288 /* Cycles last block */ 2289 sample.weight = (u32)items->tsx_aux_info; 2290 } 2291 } 2292 2293 if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) { 2294 u64 ax = items->has_rax ? items->rax : 0; 2295 /* Refer kernel's intel_hsw_transaction() */ 2296 u64 txn = (u8)(items->tsx_aux_info >> 32); 2297 2298 /* For RTM XABORTs also log the abort code from AX */ 2299 if (txn & PERF_TXN_TRANSACTION && ax & 1) 2300 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; 2301 sample.transaction = txn; 2302 } 2303 2304 return intel_pt_deliver_synth_event(pt, event, &sample, sample_type); 2305 } 2306 2307 static int intel_pt_synth_single_pebs_sample(struct intel_pt_queue *ptq) 2308 { 2309 struct intel_pt *pt = ptq->pt; 2310 struct evsel *evsel = pt->pebs_evsel; 2311 u64 id = evsel->core.id[0]; 2312 2313 return intel_pt_do_synth_pebs_sample(ptq, evsel, id); 2314 } 2315 2316 static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq) 2317 { 2318 const struct intel_pt_blk_items *items = &ptq->state->items; 2319 struct intel_pt_pebs_event *pe; 2320 struct intel_pt *pt = ptq->pt; 2321 int err = -EINVAL; 2322 int hw_id; 2323 2324 if (!items->has_applicable_counters || !items->applicable_counters) { 2325 if (!pt->single_pebs) 2326 pr_err("PEBS-via-PT record with no applicable_counters\n"); 2327 return intel_pt_synth_single_pebs_sample(ptq); 2328 } 2329 2330 for_each_set_bit(hw_id, (unsigned long *)&items->applicable_counters, INTEL_PT_MAX_PEBS) { 2331 pe = &ptq->pebs[hw_id]; 2332 if (!pe->evsel) { 2333 if (!pt->single_pebs) 2334 pr_err("PEBS-via-PT record with no matching event, hw_id %d\n", 2335 hw_id); 2336 return intel_pt_synth_single_pebs_sample(ptq); 2337 } 2338 err = intel_pt_do_synth_pebs_sample(ptq, pe->evsel, pe->id); 2339 if (err) 2340 return err; 2341 } 2342 2343 return err; 2344 } 2345 2346 static int intel_pt_synth_events_sample(struct intel_pt_queue *ptq) 2347 { 2348 struct intel_pt *pt = ptq->pt; 2349 union perf_event *event = ptq->event_buf; 2350 struct perf_sample sample = { .ip = 0, }; 2351 struct { 2352 struct perf_synth_intel_evt cfe; 2353 struct perf_synth_intel_evd evd[INTEL_PT_MAX_EVDS]; 2354 } raw; 2355 int i; 2356 2357 if (intel_pt_skip_event(pt)) 2358 return 0; 2359 2360 intel_pt_prep_p_sample(pt, ptq, event, &sample); 2361 2362 sample.id = ptq->pt->evt_id; 2363 sample.stream_id = ptq->pt->evt_id; 2364 2365 raw.cfe.type = ptq->state->cfe_type; 2366 raw.cfe.reserved = 0; 2367 raw.cfe.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); 2368 raw.cfe.vector = ptq->state->cfe_vector; 2369 raw.cfe.evd_cnt = ptq->state->evd_cnt; 2370 2371 for (i = 0; i < ptq->state->evd_cnt; i++) { 2372 raw.evd[i].et = 0; 2373 raw.evd[i].evd_type = ptq->state->evd[i].type; 2374 raw.evd[i].payload = ptq->state->evd[i].payload; 2375 } 2376 2377 sample.raw_size = perf_synth__raw_size(raw) + 2378 ptq->state->evd_cnt * sizeof(struct perf_synth_intel_evd); 2379 sample.raw_data = perf_synth__raw_data(&raw); 2380 2381 return intel_pt_deliver_synth_event(pt, event, &sample, 2382 pt->evt_sample_type); 2383 } 2384 2385 static int intel_pt_synth_iflag_chg_sample(struct intel_pt_queue *ptq) 2386 { 2387 struct intel_pt *pt = ptq->pt; 2388 union perf_event *event = ptq->event_buf; 2389 struct perf_sample sample = { .ip = 0, }; 2390 struct perf_synth_intel_iflag_chg raw; 2391 2392 if (intel_pt_skip_event(pt)) 2393 return 0; 2394 2395 intel_pt_prep_p_sample(pt, ptq, event, &sample); 2396 2397 sample.id = ptq->pt->iflag_chg_id; 2398 sample.stream_id = ptq->pt->iflag_chg_id; 2399 2400 raw.flags = 0; 2401 raw.iflag = ptq->state->to_iflag; 2402 2403 if (ptq->state->type & INTEL_PT_BRANCH) { 2404 raw.via_branch = 1; 2405 raw.branch_ip = ptq->state->to_ip; 2406 } else { 2407 sample.addr = 0; 2408 } 2409 sample.flags = ptq->flags; 2410 2411 sample.raw_size = perf_synth__raw_size(raw); 2412 sample.raw_data = perf_synth__raw_data(&raw); 2413 2414 return intel_pt_deliver_synth_event(pt, event, &sample, 2415 pt->iflag_chg_sample_type); 2416 } 2417 2418 static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu, 2419 pid_t pid, pid_t tid, u64 ip, u64 timestamp, 2420 pid_t machine_pid, int vcpu) 2421 { 2422 bool dump_log_on_error = pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ON_ERROR; 2423 bool log_on_stdout = pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_USE_STDOUT; 2424 union perf_event event; 2425 char msg[MAX_AUXTRACE_ERROR_MSG]; 2426 int err; 2427 2428 if (pt->synth_opts.error_minus_flags) { 2429 if (code == INTEL_PT_ERR_OVR && 2430 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_OVERFLOW) 2431 return 0; 2432 if (code == INTEL_PT_ERR_LOST && 2433 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_DATA_LOST) 2434 return 0; 2435 } 2436 2437 intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG); 2438 2439 auxtrace_synth_guest_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE, 2440 code, cpu, pid, tid, ip, msg, timestamp, 2441 machine_pid, vcpu); 2442 2443 if (intel_pt_enable_logging && !log_on_stdout) { 2444 FILE *fp = intel_pt_log_fp(); 2445 2446 if (fp) 2447 perf_event__fprintf_auxtrace_error(&event, fp); 2448 } 2449 2450 if (code != INTEL_PT_ERR_LOST && dump_log_on_error) 2451 intel_pt_log_dump_buf(); 2452 2453 err = perf_session__deliver_synth_event(pt->session, &event, NULL); 2454 if (err) 2455 pr_err("Intel Processor Trace: failed to deliver error event, error %d\n", 2456 err); 2457 2458 return err; 2459 } 2460 2461 static int intel_ptq_synth_error(struct intel_pt_queue *ptq, 2462 const struct intel_pt_state *state) 2463 { 2464 struct intel_pt *pt = ptq->pt; 2465 u64 tm = ptq->timestamp; 2466 pid_t machine_pid = 0; 2467 pid_t pid = ptq->pid; 2468 pid_t tid = ptq->tid; 2469 int vcpu = -1; 2470 2471 tm = pt->timeless_decoding ? 0 : tsc_to_perf_time(tm, &pt->tc); 2472 2473 if (pt->have_guest_sideband && state->from_nr) { 2474 machine_pid = ptq->guest_machine_pid; 2475 vcpu = ptq->vcpu; 2476 pid = ptq->guest_pid; 2477 tid = ptq->guest_tid; 2478 } 2479 2480 return intel_pt_synth_error(pt, state->err, ptq->cpu, pid, tid, 2481 state->from_ip, tm, machine_pid, vcpu); 2482 } 2483 2484 static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq) 2485 { 2486 struct auxtrace_queue *queue; 2487 pid_t tid = ptq->next_tid; 2488 int err; 2489 2490 if (tid == -1) 2491 return 0; 2492 2493 intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid); 2494 2495 err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid); 2496 2497 queue = &pt->queues.queue_array[ptq->queue_nr]; 2498 intel_pt_set_pid_tid_cpu(pt, queue); 2499 2500 ptq->next_tid = -1; 2501 2502 return err; 2503 } 2504 2505 static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip) 2506 { 2507 struct intel_pt *pt = ptq->pt; 2508 2509 return ip == pt->switch_ip && 2510 (ptq->flags & PERF_IP_FLAG_BRANCH) && 2511 !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC | 2512 PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT)); 2513 } 2514 2515 #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \ 2516 INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT) 2517 2518 static int intel_pt_sample(struct intel_pt_queue *ptq) 2519 { 2520 const struct intel_pt_state *state = ptq->state; 2521 struct intel_pt *pt = ptq->pt; 2522 int err; 2523 2524 if (!ptq->have_sample) 2525 return 0; 2526 2527 ptq->have_sample = false; 2528 2529 if (pt->synth_opts.approx_ipc) { 2530 ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt; 2531 ptq->ipc_cyc_cnt = ptq->state->cycles; 2532 ptq->sample_ipc = true; 2533 } else { 2534 ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt; 2535 ptq->ipc_cyc_cnt = ptq->state->tot_cyc_cnt; 2536 ptq->sample_ipc = ptq->state->flags & INTEL_PT_SAMPLE_IPC; 2537 } 2538 2539 /* Ensure guest code maps are set up */ 2540 if (symbol_conf.guest_code && (state->from_nr || state->to_nr)) 2541 intel_pt_get_guest(ptq); 2542 2543 /* 2544 * Do PEBS first to allow for the possibility that the PEBS timestamp 2545 * precedes the current timestamp. 2546 */ 2547 if (pt->sample_pebs && state->type & INTEL_PT_BLK_ITEMS) { 2548 err = intel_pt_synth_pebs_sample(ptq); 2549 if (err) 2550 return err; 2551 } 2552 2553 if (pt->synth_opts.intr_events) { 2554 if (state->type & INTEL_PT_EVT) { 2555 err = intel_pt_synth_events_sample(ptq); 2556 if (err) 2557 return err; 2558 } 2559 if (state->type & INTEL_PT_IFLAG_CHG) { 2560 err = intel_pt_synth_iflag_chg_sample(ptq); 2561 if (err) 2562 return err; 2563 } 2564 } 2565 2566 if (pt->sample_pwr_events) { 2567 if (state->type & INTEL_PT_PSB_EVT) { 2568 err = intel_pt_synth_psb_sample(ptq); 2569 if (err) 2570 return err; 2571 } 2572 if (ptq->state->cbr != ptq->cbr_seen) { 2573 err = intel_pt_synth_cbr_sample(ptq); 2574 if (err) 2575 return err; 2576 } 2577 if (state->type & INTEL_PT_PWR_EVT) { 2578 if (state->type & INTEL_PT_MWAIT_OP) { 2579 err = intel_pt_synth_mwait_sample(ptq); 2580 if (err) 2581 return err; 2582 } 2583 if (state->type & INTEL_PT_PWR_ENTRY) { 2584 err = intel_pt_synth_pwre_sample(ptq); 2585 if (err) 2586 return err; 2587 } 2588 if (state->type & INTEL_PT_EX_STOP) { 2589 err = intel_pt_synth_exstop_sample(ptq); 2590 if (err) 2591 return err; 2592 } 2593 if (state->type & INTEL_PT_PWR_EXIT) { 2594 err = intel_pt_synth_pwrx_sample(ptq); 2595 if (err) 2596 return err; 2597 } 2598 } 2599 } 2600 2601 if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) { 2602 err = intel_pt_synth_instruction_sample(ptq); 2603 if (err) 2604 return err; 2605 } 2606 2607 if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) { 2608 err = intel_pt_synth_transaction_sample(ptq); 2609 if (err) 2610 return err; 2611 } 2612 2613 if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) { 2614 err = intel_pt_synth_ptwrite_sample(ptq); 2615 if (err) 2616 return err; 2617 } 2618 2619 if (!(state->type & INTEL_PT_BRANCH)) 2620 return 0; 2621 2622 if (pt->use_thread_stack) { 2623 thread_stack__event(ptq->thread, ptq->cpu, ptq->flags, 2624 state->from_ip, state->to_ip, ptq->insn_len, 2625 state->trace_nr, pt->callstack, 2626 pt->br_stack_sz_plus, 2627 pt->mispred_all); 2628 } else { 2629 thread_stack__set_trace_nr(ptq->thread, ptq->cpu, state->trace_nr); 2630 } 2631 2632 if (pt->sample_branches) { 2633 if (state->from_nr != state->to_nr && 2634 state->from_ip && state->to_ip) { 2635 struct intel_pt_state *st = (struct intel_pt_state *)state; 2636 u64 to_ip = st->to_ip; 2637 u64 from_ip = st->from_ip; 2638 2639 /* 2640 * perf cannot handle having different machines for ip 2641 * and addr, so create 2 branches. 2642 */ 2643 st->to_ip = 0; 2644 err = intel_pt_synth_branch_sample(ptq); 2645 if (err) 2646 return err; 2647 st->from_ip = 0; 2648 st->to_ip = to_ip; 2649 err = intel_pt_synth_branch_sample(ptq); 2650 st->from_ip = from_ip; 2651 } else { 2652 err = intel_pt_synth_branch_sample(ptq); 2653 } 2654 if (err) 2655 return err; 2656 } 2657 2658 if (!ptq->sync_switch) 2659 return 0; 2660 2661 if (intel_pt_is_switch_ip(ptq, state->to_ip)) { 2662 switch (ptq->switch_state) { 2663 case INTEL_PT_SS_NOT_TRACING: 2664 case INTEL_PT_SS_UNKNOWN: 2665 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 2666 err = intel_pt_next_tid(pt, ptq); 2667 if (err) 2668 return err; 2669 ptq->switch_state = INTEL_PT_SS_TRACING; 2670 break; 2671 default: 2672 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT; 2673 return 1; 2674 } 2675 } else if (!state->to_ip) { 2676 ptq->switch_state = INTEL_PT_SS_NOT_TRACING; 2677 } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) { 2678 ptq->switch_state = INTEL_PT_SS_UNKNOWN; 2679 } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN && 2680 state->to_ip == pt->ptss_ip && 2681 (ptq->flags & PERF_IP_FLAG_CALL)) { 2682 ptq->switch_state = INTEL_PT_SS_TRACING; 2683 } 2684 2685 return 0; 2686 } 2687 2688 static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip) 2689 { 2690 struct machine *machine = pt->machine; 2691 struct map *map; 2692 struct symbol *sym, *start; 2693 u64 ip, switch_ip = 0; 2694 const char *ptss; 2695 2696 if (ptss_ip) 2697 *ptss_ip = 0; 2698 2699 map = machine__kernel_map(machine); 2700 if (!map) 2701 return 0; 2702 2703 if (map__load(map)) 2704 return 0; 2705 2706 start = dso__first_symbol(map->dso); 2707 2708 for (sym = start; sym; sym = dso__next_symbol(sym)) { 2709 if (sym->binding == STB_GLOBAL && 2710 !strcmp(sym->name, "__switch_to")) { 2711 ip = map->unmap_ip(map, sym->start); 2712 if (ip >= map->start && ip < map->end) { 2713 switch_ip = ip; 2714 break; 2715 } 2716 } 2717 } 2718 2719 if (!switch_ip || !ptss_ip) 2720 return 0; 2721 2722 if (pt->have_sched_switch == 1) 2723 ptss = "perf_trace_sched_switch"; 2724 else 2725 ptss = "__perf_event_task_sched_out"; 2726 2727 for (sym = start; sym; sym = dso__next_symbol(sym)) { 2728 if (!strcmp(sym->name, ptss)) { 2729 ip = map->unmap_ip(map, sym->start); 2730 if (ip >= map->start && ip < map->end) { 2731 *ptss_ip = ip; 2732 break; 2733 } 2734 } 2735 } 2736 2737 return switch_ip; 2738 } 2739 2740 static void intel_pt_enable_sync_switch(struct intel_pt *pt) 2741 { 2742 unsigned int i; 2743 2744 if (pt->sync_switch_not_supported) 2745 return; 2746 2747 pt->sync_switch = true; 2748 2749 for (i = 0; i < pt->queues.nr_queues; i++) { 2750 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 2751 struct intel_pt_queue *ptq = queue->priv; 2752 2753 if (ptq) 2754 ptq->sync_switch = true; 2755 } 2756 } 2757 2758 static void intel_pt_disable_sync_switch(struct intel_pt *pt) 2759 { 2760 unsigned int i; 2761 2762 pt->sync_switch = false; 2763 2764 for (i = 0; i < pt->queues.nr_queues; i++) { 2765 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 2766 struct intel_pt_queue *ptq = queue->priv; 2767 2768 if (ptq) { 2769 ptq->sync_switch = false; 2770 intel_pt_next_tid(pt, ptq); 2771 } 2772 } 2773 } 2774 2775 /* 2776 * To filter against time ranges, it is only necessary to look at the next start 2777 * or end time. 2778 */ 2779 static bool intel_pt_next_time(struct intel_pt_queue *ptq) 2780 { 2781 struct intel_pt *pt = ptq->pt; 2782 2783 if (ptq->sel_start) { 2784 /* Next time is an end time */ 2785 ptq->sel_start = false; 2786 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].end; 2787 return true; 2788 } else if (ptq->sel_idx + 1 < pt->range_cnt) { 2789 /* Next time is a start time */ 2790 ptq->sel_start = true; 2791 ptq->sel_idx += 1; 2792 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].start; 2793 return true; 2794 } 2795 2796 /* No next time */ 2797 return false; 2798 } 2799 2800 static int intel_pt_time_filter(struct intel_pt_queue *ptq, u64 *ff_timestamp) 2801 { 2802 int err; 2803 2804 while (1) { 2805 if (ptq->sel_start) { 2806 if (ptq->timestamp >= ptq->sel_timestamp) { 2807 /* After start time, so consider next time */ 2808 intel_pt_next_time(ptq); 2809 if (!ptq->sel_timestamp) { 2810 /* No end time */ 2811 return 0; 2812 } 2813 /* Check against end time */ 2814 continue; 2815 } 2816 /* Before start time, so fast forward */ 2817 ptq->have_sample = false; 2818 if (ptq->sel_timestamp > *ff_timestamp) { 2819 if (ptq->sync_switch) { 2820 intel_pt_next_tid(ptq->pt, ptq); 2821 ptq->switch_state = INTEL_PT_SS_UNKNOWN; 2822 } 2823 *ff_timestamp = ptq->sel_timestamp; 2824 err = intel_pt_fast_forward(ptq->decoder, 2825 ptq->sel_timestamp); 2826 if (err) 2827 return err; 2828 } 2829 return 0; 2830 } else if (ptq->timestamp > ptq->sel_timestamp) { 2831 /* After end time, so consider next time */ 2832 if (!intel_pt_next_time(ptq)) { 2833 /* No next time range, so stop decoding */ 2834 ptq->have_sample = false; 2835 ptq->switch_state = INTEL_PT_SS_NOT_TRACING; 2836 return 1; 2837 } 2838 /* Check against next start time */ 2839 continue; 2840 } else { 2841 /* Before end time */ 2842 return 0; 2843 } 2844 } 2845 } 2846 2847 static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp) 2848 { 2849 const struct intel_pt_state *state = ptq->state; 2850 struct intel_pt *pt = ptq->pt; 2851 u64 ff_timestamp = 0; 2852 int err; 2853 2854 if (!pt->kernel_start) { 2855 pt->kernel_start = machine__kernel_start(pt->machine); 2856 if (pt->per_cpu_mmaps && 2857 (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) && 2858 !pt->timeless_decoding && intel_pt_tracing_kernel(pt) && 2859 !pt->sampling_mode && !pt->synth_opts.vm_time_correlation) { 2860 pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip); 2861 if (pt->switch_ip) { 2862 intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n", 2863 pt->switch_ip, pt->ptss_ip); 2864 intel_pt_enable_sync_switch(pt); 2865 } 2866 } 2867 } 2868 2869 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n", 2870 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid); 2871 while (1) { 2872 err = intel_pt_sample(ptq); 2873 if (err) 2874 return err; 2875 2876 state = intel_pt_decode(ptq->decoder); 2877 if (state->err) { 2878 if (state->err == INTEL_PT_ERR_NODATA) 2879 return 1; 2880 if (ptq->sync_switch && 2881 state->from_ip >= pt->kernel_start) { 2882 ptq->sync_switch = false; 2883 intel_pt_next_tid(pt, ptq); 2884 } 2885 ptq->timestamp = state->est_timestamp; 2886 if (pt->synth_opts.errors) { 2887 err = intel_ptq_synth_error(ptq, state); 2888 if (err) 2889 return err; 2890 } 2891 continue; 2892 } 2893 2894 ptq->state = state; 2895 ptq->have_sample = true; 2896 intel_pt_sample_flags(ptq); 2897 2898 /* Use estimated TSC upon return to user space */ 2899 if (pt->est_tsc && 2900 (state->from_ip >= pt->kernel_start || !state->from_ip) && 2901 state->to_ip && state->to_ip < pt->kernel_start) { 2902 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", 2903 state->timestamp, state->est_timestamp); 2904 ptq->timestamp = state->est_timestamp; 2905 /* Use estimated TSC in unknown switch state */ 2906 } else if (ptq->sync_switch && 2907 ptq->switch_state == INTEL_PT_SS_UNKNOWN && 2908 intel_pt_is_switch_ip(ptq, state->to_ip) && 2909 ptq->next_tid == -1) { 2910 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", 2911 state->timestamp, state->est_timestamp); 2912 ptq->timestamp = state->est_timestamp; 2913 } else if (state->timestamp > ptq->timestamp) { 2914 ptq->timestamp = state->timestamp; 2915 } 2916 2917 if (ptq->sel_timestamp) { 2918 err = intel_pt_time_filter(ptq, &ff_timestamp); 2919 if (err) 2920 return err; 2921 } 2922 2923 if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) { 2924 *timestamp = ptq->timestamp; 2925 return 0; 2926 } 2927 } 2928 return 0; 2929 } 2930 2931 static inline int intel_pt_update_queues(struct intel_pt *pt) 2932 { 2933 if (pt->queues.new_data) { 2934 pt->queues.new_data = false; 2935 return intel_pt_setup_queues(pt); 2936 } 2937 return 0; 2938 } 2939 2940 static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp) 2941 { 2942 unsigned int queue_nr; 2943 u64 ts; 2944 int ret; 2945 2946 while (1) { 2947 struct auxtrace_queue *queue; 2948 struct intel_pt_queue *ptq; 2949 2950 if (!pt->heap.heap_cnt) 2951 return 0; 2952 2953 if (pt->heap.heap_array[0].ordinal >= timestamp) 2954 return 0; 2955 2956 queue_nr = pt->heap.heap_array[0].queue_nr; 2957 queue = &pt->queues.queue_array[queue_nr]; 2958 ptq = queue->priv; 2959 2960 intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n", 2961 queue_nr, pt->heap.heap_array[0].ordinal, 2962 timestamp); 2963 2964 auxtrace_heap__pop(&pt->heap); 2965 2966 if (pt->heap.heap_cnt) { 2967 ts = pt->heap.heap_array[0].ordinal + 1; 2968 if (ts > timestamp) 2969 ts = timestamp; 2970 } else { 2971 ts = timestamp; 2972 } 2973 2974 intel_pt_set_pid_tid_cpu(pt, queue); 2975 2976 ret = intel_pt_run_decoder(ptq, &ts); 2977 2978 if (ret < 0) { 2979 auxtrace_heap__add(&pt->heap, queue_nr, ts); 2980 return ret; 2981 } 2982 2983 if (!ret) { 2984 ret = auxtrace_heap__add(&pt->heap, queue_nr, ts); 2985 if (ret < 0) 2986 return ret; 2987 } else { 2988 ptq->on_heap = false; 2989 } 2990 } 2991 2992 return 0; 2993 } 2994 2995 static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid, 2996 u64 time_) 2997 { 2998 struct auxtrace_queues *queues = &pt->queues; 2999 unsigned int i; 3000 u64 ts = 0; 3001 3002 for (i = 0; i < queues->nr_queues; i++) { 3003 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 3004 struct intel_pt_queue *ptq = queue->priv; 3005 3006 if (ptq && (tid == -1 || ptq->tid == tid)) { 3007 ptq->time = time_; 3008 intel_pt_set_pid_tid_cpu(pt, queue); 3009 intel_pt_run_decoder(ptq, &ts); 3010 } 3011 } 3012 return 0; 3013 } 3014 3015 static void intel_pt_sample_set_pid_tid_cpu(struct intel_pt_queue *ptq, 3016 struct auxtrace_queue *queue, 3017 struct perf_sample *sample) 3018 { 3019 struct machine *m = ptq->pt->machine; 3020 3021 ptq->pid = sample->pid; 3022 ptq->tid = sample->tid; 3023 ptq->cpu = queue->cpu; 3024 3025 intel_pt_log("queue %u cpu %d pid %d tid %d\n", 3026 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid); 3027 3028 thread__zput(ptq->thread); 3029 3030 if (ptq->tid == -1) 3031 return; 3032 3033 if (ptq->pid == -1) { 3034 ptq->thread = machine__find_thread(m, -1, ptq->tid); 3035 if (ptq->thread) 3036 ptq->pid = ptq->thread->pid_; 3037 return; 3038 } 3039 3040 ptq->thread = machine__findnew_thread(m, ptq->pid, ptq->tid); 3041 } 3042 3043 static int intel_pt_process_timeless_sample(struct intel_pt *pt, 3044 struct perf_sample *sample) 3045 { 3046 struct auxtrace_queue *queue; 3047 struct intel_pt_queue *ptq; 3048 u64 ts = 0; 3049 3050 queue = auxtrace_queues__sample_queue(&pt->queues, sample, pt->session); 3051 if (!queue) 3052 return -EINVAL; 3053 3054 ptq = queue->priv; 3055 if (!ptq) 3056 return 0; 3057 3058 ptq->stop = false; 3059 ptq->time = sample->time; 3060 intel_pt_sample_set_pid_tid_cpu(ptq, queue, sample); 3061 intel_pt_run_decoder(ptq, &ts); 3062 return 0; 3063 } 3064 3065 static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample) 3066 { 3067 return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu, 3068 sample->pid, sample->tid, 0, sample->time, 3069 sample->machine_pid, sample->vcpu); 3070 } 3071 3072 static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu) 3073 { 3074 unsigned i, j; 3075 3076 if (cpu < 0 || !pt->queues.nr_queues) 3077 return NULL; 3078 3079 if ((unsigned)cpu >= pt->queues.nr_queues) 3080 i = pt->queues.nr_queues - 1; 3081 else 3082 i = cpu; 3083 3084 if (pt->queues.queue_array[i].cpu == cpu) 3085 return pt->queues.queue_array[i].priv; 3086 3087 for (j = 0; i > 0; j++) { 3088 if (pt->queues.queue_array[--i].cpu == cpu) 3089 return pt->queues.queue_array[i].priv; 3090 } 3091 3092 for (; j < pt->queues.nr_queues; j++) { 3093 if (pt->queues.queue_array[j].cpu == cpu) 3094 return pt->queues.queue_array[j].priv; 3095 } 3096 3097 return NULL; 3098 } 3099 3100 static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid, 3101 u64 timestamp) 3102 { 3103 struct intel_pt_queue *ptq; 3104 int err; 3105 3106 if (!pt->sync_switch) 3107 return 1; 3108 3109 ptq = intel_pt_cpu_to_ptq(pt, cpu); 3110 if (!ptq || !ptq->sync_switch) 3111 return 1; 3112 3113 switch (ptq->switch_state) { 3114 case INTEL_PT_SS_NOT_TRACING: 3115 break; 3116 case INTEL_PT_SS_UNKNOWN: 3117 case INTEL_PT_SS_TRACING: 3118 ptq->next_tid = tid; 3119 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP; 3120 return 0; 3121 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT: 3122 if (!ptq->on_heap) { 3123 ptq->timestamp = perf_time_to_tsc(timestamp, 3124 &pt->tc); 3125 err = auxtrace_heap__add(&pt->heap, ptq->queue_nr, 3126 ptq->timestamp); 3127 if (err) 3128 return err; 3129 ptq->on_heap = true; 3130 } 3131 ptq->switch_state = INTEL_PT_SS_TRACING; 3132 break; 3133 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 3134 intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu); 3135 break; 3136 default: 3137 break; 3138 } 3139 3140 ptq->next_tid = -1; 3141 3142 return 1; 3143 } 3144 3145 static int intel_pt_process_switch(struct intel_pt *pt, 3146 struct perf_sample *sample) 3147 { 3148 pid_t tid; 3149 int cpu, ret; 3150 struct evsel *evsel = evlist__id2evsel(pt->session->evlist, sample->id); 3151 3152 if (evsel != pt->switch_evsel) 3153 return 0; 3154 3155 tid = evsel__intval(evsel, sample, "next_pid"); 3156 cpu = sample->cpu; 3157 3158 intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", 3159 cpu, tid, sample->time, perf_time_to_tsc(sample->time, 3160 &pt->tc)); 3161 3162 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time); 3163 if (ret <= 0) 3164 return ret; 3165 3166 return machine__set_current_tid(pt->machine, cpu, -1, tid); 3167 } 3168 3169 static int intel_pt_context_switch_in(struct intel_pt *pt, 3170 struct perf_sample *sample) 3171 { 3172 pid_t pid = sample->pid; 3173 pid_t tid = sample->tid; 3174 int cpu = sample->cpu; 3175 3176 if (pt->sync_switch) { 3177 struct intel_pt_queue *ptq; 3178 3179 ptq = intel_pt_cpu_to_ptq(pt, cpu); 3180 if (ptq && ptq->sync_switch) { 3181 ptq->next_tid = -1; 3182 switch (ptq->switch_state) { 3183 case INTEL_PT_SS_NOT_TRACING: 3184 case INTEL_PT_SS_UNKNOWN: 3185 case INTEL_PT_SS_TRACING: 3186 break; 3187 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT: 3188 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 3189 ptq->switch_state = INTEL_PT_SS_TRACING; 3190 break; 3191 default: 3192 break; 3193 } 3194 } 3195 } 3196 3197 /* 3198 * If the current tid has not been updated yet, ensure it is now that 3199 * a "switch in" event has occurred. 3200 */ 3201 if (machine__get_current_tid(pt->machine, cpu) == tid) 3202 return 0; 3203 3204 return machine__set_current_tid(pt->machine, cpu, pid, tid); 3205 } 3206 3207 static int intel_pt_guest_context_switch(struct intel_pt *pt, 3208 union perf_event *event, 3209 struct perf_sample *sample) 3210 { 3211 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT; 3212 struct machines *machines = &pt->session->machines; 3213 struct machine *machine = machines__find(machines, sample->machine_pid); 3214 3215 pt->have_guest_sideband = true; 3216 3217 /* 3218 * sync_switch cannot handle guest machines at present, so just disable 3219 * it. 3220 */ 3221 pt->sync_switch_not_supported = true; 3222 if (pt->sync_switch) 3223 intel_pt_disable_sync_switch(pt); 3224 3225 if (out) 3226 return 0; 3227 3228 if (!machine) 3229 return -EINVAL; 3230 3231 return machine__set_current_tid(machine, sample->vcpu, sample->pid, sample->tid); 3232 } 3233 3234 static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event, 3235 struct perf_sample *sample) 3236 { 3237 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT; 3238 pid_t pid, tid; 3239 int cpu, ret; 3240 3241 if (perf_event__is_guest(event)) 3242 return intel_pt_guest_context_switch(pt, event, sample); 3243 3244 cpu = sample->cpu; 3245 3246 if (pt->have_sched_switch == 3) { 3247 if (!out) 3248 return intel_pt_context_switch_in(pt, sample); 3249 if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) { 3250 pr_err("Expecting CPU-wide context switch event\n"); 3251 return -EINVAL; 3252 } 3253 pid = event->context_switch.next_prev_pid; 3254 tid = event->context_switch.next_prev_tid; 3255 } else { 3256 if (out) 3257 return 0; 3258 pid = sample->pid; 3259 tid = sample->tid; 3260 } 3261 3262 if (tid == -1) 3263 intel_pt_log("context_switch event has no tid\n"); 3264 3265 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time); 3266 if (ret <= 0) 3267 return ret; 3268 3269 return machine__set_current_tid(pt->machine, cpu, pid, tid); 3270 } 3271 3272 static int intel_pt_process_itrace_start(struct intel_pt *pt, 3273 union perf_event *event, 3274 struct perf_sample *sample) 3275 { 3276 if (!pt->per_cpu_mmaps) 3277 return 0; 3278 3279 intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", 3280 sample->cpu, event->itrace_start.pid, 3281 event->itrace_start.tid, sample->time, 3282 perf_time_to_tsc(sample->time, &pt->tc)); 3283 3284 return machine__set_current_tid(pt->machine, sample->cpu, 3285 event->itrace_start.pid, 3286 event->itrace_start.tid); 3287 } 3288 3289 static int intel_pt_process_aux_output_hw_id(struct intel_pt *pt, 3290 union perf_event *event, 3291 struct perf_sample *sample) 3292 { 3293 u64 hw_id = event->aux_output_hw_id.hw_id; 3294 struct auxtrace_queue *queue; 3295 struct intel_pt_queue *ptq; 3296 struct evsel *evsel; 3297 3298 queue = auxtrace_queues__sample_queue(&pt->queues, sample, pt->session); 3299 evsel = evlist__id2evsel_strict(pt->session->evlist, sample->id); 3300 if (!queue || !queue->priv || !evsel || hw_id > INTEL_PT_MAX_PEBS) { 3301 pr_err("Bad AUX output hardware ID\n"); 3302 return -EINVAL; 3303 } 3304 3305 ptq = queue->priv; 3306 3307 ptq->pebs[hw_id].evsel = evsel; 3308 ptq->pebs[hw_id].id = sample->id; 3309 3310 return 0; 3311 } 3312 3313 static int intel_pt_find_map(struct thread *thread, u8 cpumode, u64 addr, 3314 struct addr_location *al) 3315 { 3316 if (!al->map || addr < al->map->start || addr >= al->map->end) { 3317 if (!thread__find_map(thread, cpumode, addr, al)) 3318 return -1; 3319 } 3320 3321 return 0; 3322 } 3323 3324 /* Invalidate all instruction cache entries that overlap the text poke */ 3325 static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event) 3326 { 3327 u8 cpumode = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK; 3328 u64 addr = event->text_poke.addr + event->text_poke.new_len - 1; 3329 /* Assume text poke begins in a basic block no more than 4096 bytes */ 3330 int cnt = 4096 + event->text_poke.new_len; 3331 struct thread *thread = pt->unknown_thread; 3332 struct addr_location al = { .map = NULL }; 3333 struct machine *machine = pt->machine; 3334 struct intel_pt_cache_entry *e; 3335 u64 offset; 3336 3337 if (!event->text_poke.new_len) 3338 return 0; 3339 3340 for (; cnt; cnt--, addr--) { 3341 if (intel_pt_find_map(thread, cpumode, addr, &al)) { 3342 if (addr < event->text_poke.addr) 3343 return 0; 3344 continue; 3345 } 3346 3347 if (!al.map->dso || !al.map->dso->auxtrace_cache) 3348 continue; 3349 3350 offset = al.map->map_ip(al.map, addr); 3351 3352 e = intel_pt_cache_lookup(al.map->dso, machine, offset); 3353 if (!e) 3354 continue; 3355 3356 if (addr + e->byte_cnt + e->length <= event->text_poke.addr) { 3357 /* 3358 * No overlap. Working backwards there cannot be another 3359 * basic block that overlaps the text poke if there is a 3360 * branch instruction before the text poke address. 3361 */ 3362 if (e->branch != INTEL_PT_BR_NO_BRANCH) 3363 return 0; 3364 } else { 3365 intel_pt_cache_invalidate(al.map->dso, machine, offset); 3366 intel_pt_log("Invalidated instruction cache for %s at %#"PRIx64"\n", 3367 al.map->dso->long_name, addr); 3368 } 3369 } 3370 3371 return 0; 3372 } 3373 3374 static int intel_pt_process_event(struct perf_session *session, 3375 union perf_event *event, 3376 struct perf_sample *sample, 3377 struct perf_tool *tool) 3378 { 3379 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 3380 auxtrace); 3381 u64 timestamp; 3382 int err = 0; 3383 3384 if (dump_trace) 3385 return 0; 3386 3387 if (!tool->ordered_events) { 3388 pr_err("Intel Processor Trace requires ordered events\n"); 3389 return -EINVAL; 3390 } 3391 3392 if (sample->time && sample->time != (u64)-1) 3393 timestamp = perf_time_to_tsc(sample->time, &pt->tc); 3394 else 3395 timestamp = 0; 3396 3397 if (timestamp || pt->timeless_decoding) { 3398 err = intel_pt_update_queues(pt); 3399 if (err) 3400 return err; 3401 } 3402 3403 if (pt->timeless_decoding) { 3404 if (pt->sampling_mode) { 3405 if (sample->aux_sample.size) 3406 err = intel_pt_process_timeless_sample(pt, 3407 sample); 3408 } else if (event->header.type == PERF_RECORD_EXIT) { 3409 err = intel_pt_process_timeless_queues(pt, 3410 event->fork.tid, 3411 sample->time); 3412 } 3413 } else if (timestamp) { 3414 if (!pt->first_timestamp) 3415 intel_pt_first_timestamp(pt, timestamp); 3416 err = intel_pt_process_queues(pt, timestamp); 3417 } 3418 if (err) 3419 return err; 3420 3421 if (event->header.type == PERF_RECORD_SAMPLE) { 3422 if (pt->synth_opts.add_callchain && !sample->callchain) 3423 intel_pt_add_callchain(pt, sample); 3424 if (pt->synth_opts.add_last_branch && !sample->branch_stack) 3425 intel_pt_add_br_stack(pt, sample); 3426 } 3427 3428 if (event->header.type == PERF_RECORD_AUX && 3429 (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) && 3430 pt->synth_opts.errors) { 3431 err = intel_pt_lost(pt, sample); 3432 if (err) 3433 return err; 3434 } 3435 3436 if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE) 3437 err = intel_pt_process_switch(pt, sample); 3438 else if (event->header.type == PERF_RECORD_ITRACE_START) 3439 err = intel_pt_process_itrace_start(pt, event, sample); 3440 else if (event->header.type == PERF_RECORD_AUX_OUTPUT_HW_ID) 3441 err = intel_pt_process_aux_output_hw_id(pt, event, sample); 3442 else if (event->header.type == PERF_RECORD_SWITCH || 3443 event->header.type == PERF_RECORD_SWITCH_CPU_WIDE) 3444 err = intel_pt_context_switch(pt, event, sample); 3445 3446 if (!err && event->header.type == PERF_RECORD_TEXT_POKE) 3447 err = intel_pt_text_poke(pt, event); 3448 3449 if (intel_pt_enable_logging && intel_pt_log_events(pt, sample->time)) { 3450 intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ", 3451 event->header.type, sample->cpu, sample->time, timestamp); 3452 intel_pt_log_event(event); 3453 } 3454 3455 return err; 3456 } 3457 3458 static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool) 3459 { 3460 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 3461 auxtrace); 3462 int ret; 3463 3464 if (dump_trace) 3465 return 0; 3466 3467 if (!tool->ordered_events) 3468 return -EINVAL; 3469 3470 ret = intel_pt_update_queues(pt); 3471 if (ret < 0) 3472 return ret; 3473 3474 if (pt->timeless_decoding) 3475 return intel_pt_process_timeless_queues(pt, -1, 3476 MAX_TIMESTAMP - 1); 3477 3478 return intel_pt_process_queues(pt, MAX_TIMESTAMP); 3479 } 3480 3481 static void intel_pt_free_events(struct perf_session *session) 3482 { 3483 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 3484 auxtrace); 3485 struct auxtrace_queues *queues = &pt->queues; 3486 unsigned int i; 3487 3488 for (i = 0; i < queues->nr_queues; i++) { 3489 intel_pt_free_queue(queues->queue_array[i].priv); 3490 queues->queue_array[i].priv = NULL; 3491 } 3492 intel_pt_log_disable(); 3493 auxtrace_queues__free(queues); 3494 } 3495 3496 static void intel_pt_free(struct perf_session *session) 3497 { 3498 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 3499 auxtrace); 3500 3501 auxtrace_heap__free(&pt->heap); 3502 intel_pt_free_events(session); 3503 session->auxtrace = NULL; 3504 intel_pt_free_vmcs_info(pt); 3505 thread__put(pt->unknown_thread); 3506 addr_filters__exit(&pt->filts); 3507 zfree(&pt->chain); 3508 zfree(&pt->filter); 3509 zfree(&pt->time_ranges); 3510 free(pt); 3511 } 3512 3513 static bool intel_pt_evsel_is_auxtrace(struct perf_session *session, 3514 struct evsel *evsel) 3515 { 3516 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 3517 auxtrace); 3518 3519 return evsel->core.attr.type == pt->pmu_type; 3520 } 3521 3522 static int intel_pt_process_auxtrace_event(struct perf_session *session, 3523 union perf_event *event, 3524 struct perf_tool *tool __maybe_unused) 3525 { 3526 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 3527 auxtrace); 3528 3529 if (!pt->data_queued) { 3530 struct auxtrace_buffer *buffer; 3531 off_t data_offset; 3532 int fd = perf_data__fd(session->data); 3533 int err; 3534 3535 if (perf_data__is_pipe(session->data)) { 3536 data_offset = 0; 3537 } else { 3538 data_offset = lseek(fd, 0, SEEK_CUR); 3539 if (data_offset == -1) 3540 return -errno; 3541 } 3542 3543 err = auxtrace_queues__add_event(&pt->queues, session, event, 3544 data_offset, &buffer); 3545 if (err) 3546 return err; 3547 3548 /* Dump here now we have copied a piped trace out of the pipe */ 3549 if (dump_trace) { 3550 if (auxtrace_buffer__get_data(buffer, fd)) { 3551 intel_pt_dump_event(pt, buffer->data, 3552 buffer->size); 3553 auxtrace_buffer__put_data(buffer); 3554 } 3555 } 3556 } 3557 3558 return 0; 3559 } 3560 3561 static int intel_pt_queue_data(struct perf_session *session, 3562 struct perf_sample *sample, 3563 union perf_event *event, u64 data_offset) 3564 { 3565 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 3566 auxtrace); 3567 u64 timestamp; 3568 3569 if (event) { 3570 return auxtrace_queues__add_event(&pt->queues, session, event, 3571 data_offset, NULL); 3572 } 3573 3574 if (sample->time && sample->time != (u64)-1) 3575 timestamp = perf_time_to_tsc(sample->time, &pt->tc); 3576 else 3577 timestamp = 0; 3578 3579 return auxtrace_queues__add_sample(&pt->queues, session, sample, 3580 data_offset, timestamp); 3581 } 3582 3583 struct intel_pt_synth { 3584 struct perf_tool dummy_tool; 3585 struct perf_session *session; 3586 }; 3587 3588 static int intel_pt_event_synth(struct perf_tool *tool, 3589 union perf_event *event, 3590 struct perf_sample *sample __maybe_unused, 3591 struct machine *machine __maybe_unused) 3592 { 3593 struct intel_pt_synth *intel_pt_synth = 3594 container_of(tool, struct intel_pt_synth, dummy_tool); 3595 3596 return perf_session__deliver_synth_event(intel_pt_synth->session, event, 3597 NULL); 3598 } 3599 3600 static int intel_pt_synth_event(struct perf_session *session, const char *name, 3601 struct perf_event_attr *attr, u64 id) 3602 { 3603 struct intel_pt_synth intel_pt_synth; 3604 int err; 3605 3606 pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n", 3607 name, id, (u64)attr->sample_type); 3608 3609 memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth)); 3610 intel_pt_synth.session = session; 3611 3612 err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1, 3613 &id, intel_pt_event_synth); 3614 if (err) 3615 pr_err("%s: failed to synthesize '%s' event type\n", 3616 __func__, name); 3617 3618 return err; 3619 } 3620 3621 static void intel_pt_set_event_name(struct evlist *evlist, u64 id, 3622 const char *name) 3623 { 3624 struct evsel *evsel; 3625 3626 evlist__for_each_entry(evlist, evsel) { 3627 if (evsel->core.id && evsel->core.id[0] == id) { 3628 if (evsel->name) 3629 zfree(&evsel->name); 3630 evsel->name = strdup(name); 3631 break; 3632 } 3633 } 3634 } 3635 3636 static struct evsel *intel_pt_evsel(struct intel_pt *pt, 3637 struct evlist *evlist) 3638 { 3639 struct evsel *evsel; 3640 3641 evlist__for_each_entry(evlist, evsel) { 3642 if (evsel->core.attr.type == pt->pmu_type && evsel->core.ids) 3643 return evsel; 3644 } 3645 3646 return NULL; 3647 } 3648 3649 static int intel_pt_synth_events(struct intel_pt *pt, 3650 struct perf_session *session) 3651 { 3652 struct evlist *evlist = session->evlist; 3653 struct evsel *evsel = intel_pt_evsel(pt, evlist); 3654 struct perf_event_attr attr; 3655 u64 id; 3656 int err; 3657 3658 if (!evsel) { 3659 pr_debug("There are no selected events with Intel Processor Trace data\n"); 3660 return 0; 3661 } 3662 3663 memset(&attr, 0, sizeof(struct perf_event_attr)); 3664 attr.size = sizeof(struct perf_event_attr); 3665 attr.type = PERF_TYPE_HARDWARE; 3666 attr.sample_type = evsel->core.attr.sample_type & PERF_SAMPLE_MASK; 3667 attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID | 3668 PERF_SAMPLE_PERIOD; 3669 if (pt->timeless_decoding) 3670 attr.sample_type &= ~(u64)PERF_SAMPLE_TIME; 3671 else 3672 attr.sample_type |= PERF_SAMPLE_TIME; 3673 if (!pt->per_cpu_mmaps) 3674 attr.sample_type &= ~(u64)PERF_SAMPLE_CPU; 3675 attr.exclude_user = evsel->core.attr.exclude_user; 3676 attr.exclude_kernel = evsel->core.attr.exclude_kernel; 3677 attr.exclude_hv = evsel->core.attr.exclude_hv; 3678 attr.exclude_host = evsel->core.attr.exclude_host; 3679 attr.exclude_guest = evsel->core.attr.exclude_guest; 3680 attr.sample_id_all = evsel->core.attr.sample_id_all; 3681 attr.read_format = evsel->core.attr.read_format; 3682 3683 id = evsel->core.id[0] + 1000000000; 3684 if (!id) 3685 id = 1; 3686 3687 if (pt->synth_opts.branches) { 3688 attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS; 3689 attr.sample_period = 1; 3690 attr.sample_type |= PERF_SAMPLE_ADDR; 3691 err = intel_pt_synth_event(session, "branches", &attr, id); 3692 if (err) 3693 return err; 3694 pt->sample_branches = true; 3695 pt->branches_sample_type = attr.sample_type; 3696 pt->branches_id = id; 3697 id += 1; 3698 attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR; 3699 } 3700 3701 if (pt->synth_opts.callchain) 3702 attr.sample_type |= PERF_SAMPLE_CALLCHAIN; 3703 if (pt->synth_opts.last_branch) { 3704 attr.sample_type |= PERF_SAMPLE_BRANCH_STACK; 3705 /* 3706 * We don't use the hardware index, but the sample generation 3707 * code uses the new format branch_stack with this field, 3708 * so the event attributes must indicate that it's present. 3709 */ 3710 attr.branch_sample_type |= PERF_SAMPLE_BRANCH_HW_INDEX; 3711 } 3712 3713 if (pt->synth_opts.instructions) { 3714 attr.config = PERF_COUNT_HW_INSTRUCTIONS; 3715 if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS) 3716 attr.sample_period = 3717 intel_pt_ns_to_ticks(pt, pt->synth_opts.period); 3718 else 3719 attr.sample_period = pt->synth_opts.period; 3720 err = intel_pt_synth_event(session, "instructions", &attr, id); 3721 if (err) 3722 return err; 3723 pt->sample_instructions = true; 3724 pt->instructions_sample_type = attr.sample_type; 3725 pt->instructions_id = id; 3726 id += 1; 3727 } 3728 3729 attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD; 3730 attr.sample_period = 1; 3731 3732 if (pt->synth_opts.transactions) { 3733 attr.config = PERF_COUNT_HW_INSTRUCTIONS; 3734 err = intel_pt_synth_event(session, "transactions", &attr, id); 3735 if (err) 3736 return err; 3737 pt->sample_transactions = true; 3738 pt->transactions_sample_type = attr.sample_type; 3739 pt->transactions_id = id; 3740 intel_pt_set_event_name(evlist, id, "transactions"); 3741 id += 1; 3742 } 3743 3744 attr.type = PERF_TYPE_SYNTH; 3745 attr.sample_type |= PERF_SAMPLE_RAW; 3746 3747 if (pt->synth_opts.ptwrites) { 3748 attr.config = PERF_SYNTH_INTEL_PTWRITE; 3749 err = intel_pt_synth_event(session, "ptwrite", &attr, id); 3750 if (err) 3751 return err; 3752 pt->sample_ptwrites = true; 3753 pt->ptwrites_sample_type = attr.sample_type; 3754 pt->ptwrites_id = id; 3755 intel_pt_set_event_name(evlist, id, "ptwrite"); 3756 id += 1; 3757 } 3758 3759 if (pt->synth_opts.pwr_events) { 3760 pt->sample_pwr_events = true; 3761 pt->pwr_events_sample_type = attr.sample_type; 3762 3763 attr.config = PERF_SYNTH_INTEL_CBR; 3764 err = intel_pt_synth_event(session, "cbr", &attr, id); 3765 if (err) 3766 return err; 3767 pt->cbr_id = id; 3768 intel_pt_set_event_name(evlist, id, "cbr"); 3769 id += 1; 3770 3771 attr.config = PERF_SYNTH_INTEL_PSB; 3772 err = intel_pt_synth_event(session, "psb", &attr, id); 3773 if (err) 3774 return err; 3775 pt->psb_id = id; 3776 intel_pt_set_event_name(evlist, id, "psb"); 3777 id += 1; 3778 } 3779 3780 if (pt->synth_opts.pwr_events && (evsel->core.attr.config & INTEL_PT_CFG_PWR_EVT_EN)) { 3781 attr.config = PERF_SYNTH_INTEL_MWAIT; 3782 err = intel_pt_synth_event(session, "mwait", &attr, id); 3783 if (err) 3784 return err; 3785 pt->mwait_id = id; 3786 intel_pt_set_event_name(evlist, id, "mwait"); 3787 id += 1; 3788 3789 attr.config = PERF_SYNTH_INTEL_PWRE; 3790 err = intel_pt_synth_event(session, "pwre", &attr, id); 3791 if (err) 3792 return err; 3793 pt->pwre_id = id; 3794 intel_pt_set_event_name(evlist, id, "pwre"); 3795 id += 1; 3796 3797 attr.config = PERF_SYNTH_INTEL_EXSTOP; 3798 err = intel_pt_synth_event(session, "exstop", &attr, id); 3799 if (err) 3800 return err; 3801 pt->exstop_id = id; 3802 intel_pt_set_event_name(evlist, id, "exstop"); 3803 id += 1; 3804 3805 attr.config = PERF_SYNTH_INTEL_PWRX; 3806 err = intel_pt_synth_event(session, "pwrx", &attr, id); 3807 if (err) 3808 return err; 3809 pt->pwrx_id = id; 3810 intel_pt_set_event_name(evlist, id, "pwrx"); 3811 id += 1; 3812 } 3813 3814 if (pt->synth_opts.intr_events && (evsel->core.attr.config & INTEL_PT_CFG_EVT_EN)) { 3815 attr.config = PERF_SYNTH_INTEL_EVT; 3816 err = intel_pt_synth_event(session, "evt", &attr, id); 3817 if (err) 3818 return err; 3819 pt->evt_sample_type = attr.sample_type; 3820 pt->evt_id = id; 3821 intel_pt_set_event_name(evlist, id, "evt"); 3822 id += 1; 3823 } 3824 3825 if (pt->synth_opts.intr_events && pt->cap_event_trace) { 3826 attr.config = PERF_SYNTH_INTEL_IFLAG_CHG; 3827 err = intel_pt_synth_event(session, "iflag", &attr, id); 3828 if (err) 3829 return err; 3830 pt->iflag_chg_sample_type = attr.sample_type; 3831 pt->iflag_chg_id = id; 3832 intel_pt_set_event_name(evlist, id, "iflag"); 3833 id += 1; 3834 } 3835 3836 return 0; 3837 } 3838 3839 static void intel_pt_setup_pebs_events(struct intel_pt *pt) 3840 { 3841 struct evsel *evsel; 3842 3843 if (!pt->synth_opts.other_events) 3844 return; 3845 3846 evlist__for_each_entry(pt->session->evlist, evsel) { 3847 if (evsel->core.attr.aux_output && evsel->core.id) { 3848 if (pt->single_pebs) { 3849 pt->single_pebs = false; 3850 return; 3851 } 3852 pt->single_pebs = true; 3853 pt->sample_pebs = true; 3854 pt->pebs_evsel = evsel; 3855 } 3856 } 3857 } 3858 3859 static struct evsel *intel_pt_find_sched_switch(struct evlist *evlist) 3860 { 3861 struct evsel *evsel; 3862 3863 evlist__for_each_entry_reverse(evlist, evsel) { 3864 const char *name = evsel__name(evsel); 3865 3866 if (!strcmp(name, "sched:sched_switch")) 3867 return evsel; 3868 } 3869 3870 return NULL; 3871 } 3872 3873 static bool intel_pt_find_switch(struct evlist *evlist) 3874 { 3875 struct evsel *evsel; 3876 3877 evlist__for_each_entry(evlist, evsel) { 3878 if (evsel->core.attr.context_switch) 3879 return true; 3880 } 3881 3882 return false; 3883 } 3884 3885 static int intel_pt_perf_config(const char *var, const char *value, void *data) 3886 { 3887 struct intel_pt *pt = data; 3888 3889 if (!strcmp(var, "intel-pt.mispred-all")) 3890 pt->mispred_all = perf_config_bool(var, value); 3891 3892 if (!strcmp(var, "intel-pt.max-loops")) 3893 perf_config_int(&pt->max_loops, var, value); 3894 3895 return 0; 3896 } 3897 3898 /* Find least TSC which converts to ns or later */ 3899 static u64 intel_pt_tsc_start(u64 ns, struct intel_pt *pt) 3900 { 3901 u64 tsc, tm; 3902 3903 tsc = perf_time_to_tsc(ns, &pt->tc); 3904 3905 while (1) { 3906 tm = tsc_to_perf_time(tsc, &pt->tc); 3907 if (tm < ns) 3908 break; 3909 tsc -= 1; 3910 } 3911 3912 while (tm < ns) 3913 tm = tsc_to_perf_time(++tsc, &pt->tc); 3914 3915 return tsc; 3916 } 3917 3918 /* Find greatest TSC which converts to ns or earlier */ 3919 static u64 intel_pt_tsc_end(u64 ns, struct intel_pt *pt) 3920 { 3921 u64 tsc, tm; 3922 3923 tsc = perf_time_to_tsc(ns, &pt->tc); 3924 3925 while (1) { 3926 tm = tsc_to_perf_time(tsc, &pt->tc); 3927 if (tm > ns) 3928 break; 3929 tsc += 1; 3930 } 3931 3932 while (tm > ns) 3933 tm = tsc_to_perf_time(--tsc, &pt->tc); 3934 3935 return tsc; 3936 } 3937 3938 static int intel_pt_setup_time_ranges(struct intel_pt *pt, 3939 struct itrace_synth_opts *opts) 3940 { 3941 struct perf_time_interval *p = opts->ptime_range; 3942 int n = opts->range_num; 3943 int i; 3944 3945 if (!n || !p || pt->timeless_decoding) 3946 return 0; 3947 3948 pt->time_ranges = calloc(n, sizeof(struct range)); 3949 if (!pt->time_ranges) 3950 return -ENOMEM; 3951 3952 pt->range_cnt = n; 3953 3954 intel_pt_log("%s: %u range(s)\n", __func__, n); 3955 3956 for (i = 0; i < n; i++) { 3957 struct range *r = &pt->time_ranges[i]; 3958 u64 ts = p[i].start; 3959 u64 te = p[i].end; 3960 3961 /* 3962 * Take care to ensure the TSC range matches the perf-time range 3963 * when converted back to perf-time. 3964 */ 3965 r->start = ts ? intel_pt_tsc_start(ts, pt) : 0; 3966 r->end = te ? intel_pt_tsc_end(te, pt) : 0; 3967 3968 intel_pt_log("range %d: perf time interval: %"PRIu64" to %"PRIu64"\n", 3969 i, ts, te); 3970 intel_pt_log("range %d: TSC time interval: %#"PRIx64" to %#"PRIx64"\n", 3971 i, r->start, r->end); 3972 } 3973 3974 return 0; 3975 } 3976 3977 static int intel_pt_parse_vm_tm_corr_arg(struct intel_pt *pt, char **args) 3978 { 3979 struct intel_pt_vmcs_info *vmcs_info; 3980 u64 tsc_offset, vmcs; 3981 char *p = *args; 3982 3983 errno = 0; 3984 3985 p = skip_spaces(p); 3986 if (!*p) 3987 return 1; 3988 3989 tsc_offset = strtoull(p, &p, 0); 3990 if (errno) 3991 return -errno; 3992 p = skip_spaces(p); 3993 if (*p != ':') { 3994 pt->dflt_tsc_offset = tsc_offset; 3995 *args = p; 3996 return 0; 3997 } 3998 p += 1; 3999 while (1) { 4000 vmcs = strtoull(p, &p, 0); 4001 if (errno) 4002 return -errno; 4003 if (!vmcs) 4004 return -EINVAL; 4005 vmcs_info = intel_pt_findnew_vmcs(&pt->vmcs_info, vmcs, tsc_offset); 4006 if (!vmcs_info) 4007 return -ENOMEM; 4008 p = skip_spaces(p); 4009 if (*p != ',') 4010 break; 4011 p += 1; 4012 } 4013 *args = p; 4014 return 0; 4015 } 4016 4017 static int intel_pt_parse_vm_tm_corr_args(struct intel_pt *pt) 4018 { 4019 char *args = pt->synth_opts.vm_tm_corr_args; 4020 int ret; 4021 4022 if (!args) 4023 return 0; 4024 4025 do { 4026 ret = intel_pt_parse_vm_tm_corr_arg(pt, &args); 4027 } while (!ret); 4028 4029 if (ret < 0) { 4030 pr_err("Failed to parse VM Time Correlation options\n"); 4031 return ret; 4032 } 4033 4034 return 0; 4035 } 4036 4037 static const char * const intel_pt_info_fmts[] = { 4038 [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n", 4039 [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n", 4040 [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n", 4041 [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n", 4042 [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n", 4043 [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n", 4044 [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n", 4045 [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n", 4046 [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n", 4047 [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n", 4048 [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n", 4049 [INTEL_PT_MTC_FREQ_BITS] = " MTC freq bits %#"PRIx64"\n", 4050 [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n", 4051 [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n", 4052 [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n", 4053 [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n", 4054 [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n", 4055 }; 4056 4057 static void intel_pt_print_info(__u64 *arr, int start, int finish) 4058 { 4059 int i; 4060 4061 if (!dump_trace) 4062 return; 4063 4064 for (i = start; i <= finish; i++) { 4065 const char *fmt = intel_pt_info_fmts[i]; 4066 4067 if (fmt) 4068 fprintf(stdout, fmt, arr[i]); 4069 } 4070 } 4071 4072 static void intel_pt_print_info_str(const char *name, const char *str) 4073 { 4074 if (!dump_trace) 4075 return; 4076 4077 fprintf(stdout, " %-20s%s\n", name, str ? str : ""); 4078 } 4079 4080 static bool intel_pt_has(struct perf_record_auxtrace_info *auxtrace_info, int pos) 4081 { 4082 return auxtrace_info->header.size >= 4083 sizeof(struct perf_record_auxtrace_info) + (sizeof(u64) * (pos + 1)); 4084 } 4085 4086 int intel_pt_process_auxtrace_info(union perf_event *event, 4087 struct perf_session *session) 4088 { 4089 struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; 4090 size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS; 4091 struct intel_pt *pt; 4092 void *info_end; 4093 __u64 *info; 4094 int err; 4095 4096 if (auxtrace_info->header.size < sizeof(struct perf_record_auxtrace_info) + 4097 min_sz) 4098 return -EINVAL; 4099 4100 pt = zalloc(sizeof(struct intel_pt)); 4101 if (!pt) 4102 return -ENOMEM; 4103 4104 pt->vmcs_info = RB_ROOT; 4105 4106 addr_filters__init(&pt->filts); 4107 4108 err = perf_config(intel_pt_perf_config, pt); 4109 if (err) 4110 goto err_free; 4111 4112 err = auxtrace_queues__init(&pt->queues); 4113 if (err) 4114 goto err_free; 4115 4116 if (session->itrace_synth_opts->set) { 4117 pt->synth_opts = *session->itrace_synth_opts; 4118 } else { 4119 struct itrace_synth_opts *opts = session->itrace_synth_opts; 4120 4121 itrace_synth_opts__set_default(&pt->synth_opts, opts->default_no_sample); 4122 if (!opts->default_no_sample && !opts->inject) { 4123 pt->synth_opts.branches = false; 4124 pt->synth_opts.callchain = true; 4125 pt->synth_opts.add_callchain = true; 4126 } 4127 pt->synth_opts.thread_stack = opts->thread_stack; 4128 } 4129 4130 if (!(pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_USE_STDOUT)) 4131 intel_pt_log_set_name(INTEL_PT_PMU_NAME); 4132 4133 pt->session = session; 4134 pt->machine = &session->machines.host; /* No kvm support */ 4135 pt->auxtrace_type = auxtrace_info->type; 4136 pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE]; 4137 pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT]; 4138 pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT]; 4139 pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO]; 4140 pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO]; 4141 pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT]; 4142 pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT]; 4143 pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH]; 4144 pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE]; 4145 pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS]; 4146 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE, 4147 INTEL_PT_PER_CPU_MMAPS); 4148 4149 if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) { 4150 pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT]; 4151 pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS]; 4152 pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N]; 4153 pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D]; 4154 pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT]; 4155 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT, 4156 INTEL_PT_CYC_BIT); 4157 } 4158 4159 if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) { 4160 pt->max_non_turbo_ratio = 4161 auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO]; 4162 intel_pt_print_info(&auxtrace_info->priv[0], 4163 INTEL_PT_MAX_NONTURBO_RATIO, 4164 INTEL_PT_MAX_NONTURBO_RATIO); 4165 } 4166 4167 info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1; 4168 info_end = (void *)auxtrace_info + auxtrace_info->header.size; 4169 4170 if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) { 4171 size_t len; 4172 4173 len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN]; 4174 intel_pt_print_info(&auxtrace_info->priv[0], 4175 INTEL_PT_FILTER_STR_LEN, 4176 INTEL_PT_FILTER_STR_LEN); 4177 if (len) { 4178 const char *filter = (const char *)info; 4179 4180 len = roundup(len + 1, 8); 4181 info += len >> 3; 4182 if ((void *)info > info_end) { 4183 pr_err("%s: bad filter string length\n", __func__); 4184 err = -EINVAL; 4185 goto err_free_queues; 4186 } 4187 pt->filter = memdup(filter, len); 4188 if (!pt->filter) { 4189 err = -ENOMEM; 4190 goto err_free_queues; 4191 } 4192 if (session->header.needs_swap) 4193 mem_bswap_64(pt->filter, len); 4194 if (pt->filter[len - 1]) { 4195 pr_err("%s: filter string not null terminated\n", __func__); 4196 err = -EINVAL; 4197 goto err_free_queues; 4198 } 4199 err = addr_filters__parse_bare_filter(&pt->filts, 4200 filter); 4201 if (err) 4202 goto err_free_queues; 4203 } 4204 intel_pt_print_info_str("Filter string", pt->filter); 4205 } 4206 4207 if ((void *)info < info_end) { 4208 pt->cap_event_trace = *info++; 4209 if (dump_trace) 4210 fprintf(stdout, " Cap Event Trace %d\n", 4211 pt->cap_event_trace); 4212 } 4213 4214 pt->timeless_decoding = intel_pt_timeless_decoding(pt); 4215 if (pt->timeless_decoding && !pt->tc.time_mult) 4216 pt->tc.time_mult = 1; 4217 pt->have_tsc = intel_pt_have_tsc(pt); 4218 pt->sampling_mode = intel_pt_sampling_mode(pt); 4219 pt->est_tsc = !pt->timeless_decoding; 4220 4221 if (pt->synth_opts.vm_time_correlation) { 4222 if (pt->timeless_decoding) { 4223 pr_err("Intel PT has no time information for VM Time Correlation\n"); 4224 err = -EINVAL; 4225 goto err_free_queues; 4226 } 4227 if (session->itrace_synth_opts->ptime_range) { 4228 pr_err("Time ranges cannot be specified with VM Time Correlation\n"); 4229 err = -EINVAL; 4230 goto err_free_queues; 4231 } 4232 /* Currently TSC Offset is calculated using MTC packets */ 4233 if (!intel_pt_have_mtc(pt)) { 4234 pr_err("MTC packets must have been enabled for VM Time Correlation\n"); 4235 err = -EINVAL; 4236 goto err_free_queues; 4237 } 4238 err = intel_pt_parse_vm_tm_corr_args(pt); 4239 if (err) 4240 goto err_free_queues; 4241 } 4242 4243 pt->unknown_thread = thread__new(999999999, 999999999); 4244 if (!pt->unknown_thread) { 4245 err = -ENOMEM; 4246 goto err_free_queues; 4247 } 4248 4249 /* 4250 * Since this thread will not be kept in any rbtree not in a 4251 * list, initialize its list node so that at thread__put() the 4252 * current thread lifetime assumption is kept and we don't segfault 4253 * at list_del_init(). 4254 */ 4255 INIT_LIST_HEAD(&pt->unknown_thread->node); 4256 4257 err = thread__set_comm(pt->unknown_thread, "unknown", 0); 4258 if (err) 4259 goto err_delete_thread; 4260 if (thread__init_maps(pt->unknown_thread, pt->machine)) { 4261 err = -ENOMEM; 4262 goto err_delete_thread; 4263 } 4264 4265 pt->auxtrace.process_event = intel_pt_process_event; 4266 pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event; 4267 pt->auxtrace.queue_data = intel_pt_queue_data; 4268 pt->auxtrace.dump_auxtrace_sample = intel_pt_dump_sample; 4269 pt->auxtrace.flush_events = intel_pt_flush; 4270 pt->auxtrace.free_events = intel_pt_free_events; 4271 pt->auxtrace.free = intel_pt_free; 4272 pt->auxtrace.evsel_is_auxtrace = intel_pt_evsel_is_auxtrace; 4273 session->auxtrace = &pt->auxtrace; 4274 4275 if (dump_trace) 4276 return 0; 4277 4278 if (pt->have_sched_switch == 1) { 4279 pt->switch_evsel = intel_pt_find_sched_switch(session->evlist); 4280 if (!pt->switch_evsel) { 4281 pr_err("%s: missing sched_switch event\n", __func__); 4282 err = -EINVAL; 4283 goto err_delete_thread; 4284 } 4285 } else if (pt->have_sched_switch == 2 && 4286 !intel_pt_find_switch(session->evlist)) { 4287 pr_err("%s: missing context_switch attribute flag\n", __func__); 4288 err = -EINVAL; 4289 goto err_delete_thread; 4290 } 4291 4292 if (pt->synth_opts.log) { 4293 bool log_on_error = pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ON_ERROR; 4294 unsigned int log_on_error_size = pt->synth_opts.log_on_error_size; 4295 4296 intel_pt_log_enable(log_on_error, log_on_error_size); 4297 } 4298 4299 /* Maximum non-turbo ratio is TSC freq / 100 MHz */ 4300 if (pt->tc.time_mult) { 4301 u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000); 4302 4303 if (!pt->max_non_turbo_ratio) 4304 pt->max_non_turbo_ratio = 4305 (tsc_freq + 50000000) / 100000000; 4306 intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq); 4307 intel_pt_log("Maximum non-turbo ratio %u\n", 4308 pt->max_non_turbo_ratio); 4309 pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000; 4310 } 4311 4312 err = intel_pt_setup_time_ranges(pt, session->itrace_synth_opts); 4313 if (err) 4314 goto err_delete_thread; 4315 4316 if (pt->synth_opts.calls) 4317 pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC | 4318 PERF_IP_FLAG_TRACE_END; 4319 if (pt->synth_opts.returns) 4320 pt->branches_filter |= PERF_IP_FLAG_RETURN | 4321 PERF_IP_FLAG_TRACE_BEGIN; 4322 4323 if ((pt->synth_opts.callchain || pt->synth_opts.add_callchain) && 4324 !symbol_conf.use_callchain) { 4325 symbol_conf.use_callchain = true; 4326 if (callchain_register_param(&callchain_param) < 0) { 4327 symbol_conf.use_callchain = false; 4328 pt->synth_opts.callchain = false; 4329 pt->synth_opts.add_callchain = false; 4330 } 4331 } 4332 4333 if (pt->synth_opts.add_callchain) { 4334 err = intel_pt_callchain_init(pt); 4335 if (err) 4336 goto err_delete_thread; 4337 } 4338 4339 if (pt->synth_opts.last_branch || pt->synth_opts.add_last_branch) { 4340 pt->br_stack_sz = pt->synth_opts.last_branch_sz; 4341 pt->br_stack_sz_plus = pt->br_stack_sz; 4342 } 4343 4344 if (pt->synth_opts.add_last_branch) { 4345 err = intel_pt_br_stack_init(pt); 4346 if (err) 4347 goto err_delete_thread; 4348 /* 4349 * Additional branch stack size to cater for tracing from the 4350 * actual sample ip to where the sample time is recorded. 4351 * Measured at about 200 branches, but generously set to 1024. 4352 * If kernel space is not being traced, then add just 1 for the 4353 * branch to kernel space. 4354 */ 4355 if (intel_pt_tracing_kernel(pt)) 4356 pt->br_stack_sz_plus += 1024; 4357 else 4358 pt->br_stack_sz_plus += 1; 4359 } 4360 4361 pt->use_thread_stack = pt->synth_opts.callchain || 4362 pt->synth_opts.add_callchain || 4363 pt->synth_opts.thread_stack || 4364 pt->synth_opts.last_branch || 4365 pt->synth_opts.add_last_branch; 4366 4367 pt->callstack = pt->synth_opts.callchain || 4368 pt->synth_opts.add_callchain || 4369 pt->synth_opts.thread_stack; 4370 4371 err = intel_pt_synth_events(pt, session); 4372 if (err) 4373 goto err_delete_thread; 4374 4375 intel_pt_setup_pebs_events(pt); 4376 4377 if (pt->sampling_mode || list_empty(&session->auxtrace_index)) 4378 err = auxtrace_queue_data(session, true, true); 4379 else 4380 err = auxtrace_queues__process_index(&pt->queues, session); 4381 if (err) 4382 goto err_delete_thread; 4383 4384 if (pt->queues.populated) 4385 pt->data_queued = true; 4386 4387 if (pt->timeless_decoding) 4388 pr_debug2("Intel PT decoding without timestamps\n"); 4389 4390 return 0; 4391 4392 err_delete_thread: 4393 zfree(&pt->chain); 4394 thread__zput(pt->unknown_thread); 4395 err_free_queues: 4396 intel_pt_log_disable(); 4397 auxtrace_queues__free(&pt->queues); 4398 session->auxtrace = NULL; 4399 err_free: 4400 addr_filters__exit(&pt->filts); 4401 zfree(&pt->filter); 4402 zfree(&pt->time_ranges); 4403 free(pt); 4404 return err; 4405 } 4406