1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * intel_pt_decoder.h: Intel Processor Trace support 4 * Copyright (c) 2013-2014, Intel Corporation. 5 */ 6 7 #ifndef INCLUDE__INTEL_PT_DECODER_H__ 8 #define INCLUDE__INTEL_PT_DECODER_H__ 9 10 #include <stdint.h> 11 #include <stddef.h> 12 #include <stdbool.h> 13 14 #include <linux/rbtree.h> 15 16 #include "intel-pt-insn-decoder.h" 17 18 #define INTEL_PT_IN_TX (1 << 0) 19 #define INTEL_PT_ABORT_TX (1 << 1) 20 #define INTEL_PT_ASYNC (1 << 2) 21 #define INTEL_PT_FUP_IP (1 << 3) 22 #define INTEL_PT_SAMPLE_IPC (1 << 4) 23 24 enum intel_pt_sample_type { 25 INTEL_PT_BRANCH = 1 << 0, 26 INTEL_PT_INSTRUCTION = 1 << 1, 27 INTEL_PT_TRANSACTION = 1 << 2, 28 INTEL_PT_PTW = 1 << 3, 29 INTEL_PT_MWAIT_OP = 1 << 4, 30 INTEL_PT_PWR_ENTRY = 1 << 5, 31 INTEL_PT_EX_STOP = 1 << 6, 32 INTEL_PT_PWR_EXIT = 1 << 7, 33 INTEL_PT_CBR_CHG = 1 << 8, 34 INTEL_PT_TRACE_BEGIN = 1 << 9, 35 INTEL_PT_TRACE_END = 1 << 10, 36 INTEL_PT_BLK_ITEMS = 1 << 11, 37 INTEL_PT_PSB_EVT = 1 << 12, 38 }; 39 40 enum intel_pt_period_type { 41 INTEL_PT_PERIOD_NONE, 42 INTEL_PT_PERIOD_INSTRUCTIONS, 43 INTEL_PT_PERIOD_TICKS, 44 INTEL_PT_PERIOD_MTC, 45 }; 46 47 enum { 48 INTEL_PT_ERR_NOMEM = 1, 49 INTEL_PT_ERR_INTERN, 50 INTEL_PT_ERR_BADPKT, 51 INTEL_PT_ERR_NODATA, 52 INTEL_PT_ERR_NOINSN, 53 INTEL_PT_ERR_MISMAT, 54 INTEL_PT_ERR_OVR, 55 INTEL_PT_ERR_LOST, 56 INTEL_PT_ERR_UNK, 57 INTEL_PT_ERR_NELOOP, 58 INTEL_PT_ERR_MAX, 59 }; 60 61 enum intel_pt_param_flags { 62 /* 63 * FUP packet can contain next linear instruction pointer instead of 64 * current linear instruction pointer. 65 */ 66 INTEL_PT_FUP_WITH_NLIP = 1 << 0, 67 }; 68 69 enum intel_pt_blk_type { 70 INTEL_PT_GP_REGS = 1, 71 INTEL_PT_PEBS_BASIC = 4, 72 INTEL_PT_PEBS_MEM = 5, 73 INTEL_PT_LBR_0 = 8, 74 INTEL_PT_LBR_1 = 9, 75 INTEL_PT_LBR_2 = 10, 76 INTEL_PT_XMM = 16, 77 INTEL_PT_BLK_TYPE_MAX 78 }; 79 80 /* 81 * The block type numbers are not sequential but here they are given sequential 82 * positions to avoid wasting space for array placement. 83 */ 84 enum intel_pt_blk_type_pos { 85 INTEL_PT_GP_REGS_POS, 86 INTEL_PT_PEBS_BASIC_POS, 87 INTEL_PT_PEBS_MEM_POS, 88 INTEL_PT_LBR_0_POS, 89 INTEL_PT_LBR_1_POS, 90 INTEL_PT_LBR_2_POS, 91 INTEL_PT_XMM_POS, 92 INTEL_PT_BLK_TYPE_CNT 93 }; 94 95 /* Get the array position for a block type */ 96 static inline int intel_pt_blk_type_pos(enum intel_pt_blk_type blk_type) 97 { 98 #define BLK_TYPE(bt) [INTEL_PT_##bt] = INTEL_PT_##bt##_POS + 1 99 const int map[INTEL_PT_BLK_TYPE_MAX] = { 100 BLK_TYPE(GP_REGS), 101 BLK_TYPE(PEBS_BASIC), 102 BLK_TYPE(PEBS_MEM), 103 BLK_TYPE(LBR_0), 104 BLK_TYPE(LBR_1), 105 BLK_TYPE(LBR_2), 106 BLK_TYPE(XMM), 107 }; 108 #undef BLK_TYPE 109 110 return blk_type < INTEL_PT_BLK_TYPE_MAX ? map[blk_type] - 1 : -1; 111 } 112 113 #define INTEL_PT_BLK_ITEM_ID_CNT 32 114 115 /* 116 * Use unions so that the block items can be accessed by name or by array index. 117 * There is an array of 32-bit masks for each block type, which indicate which 118 * values are present. Then arrays of 32 64-bit values for each block type. 119 */ 120 struct intel_pt_blk_items { 121 union { 122 uint32_t mask[INTEL_PT_BLK_TYPE_CNT]; 123 struct { 124 uint32_t has_rflags:1; 125 uint32_t has_rip:1; 126 uint32_t has_rax:1; 127 uint32_t has_rcx:1; 128 uint32_t has_rdx:1; 129 uint32_t has_rbx:1; 130 uint32_t has_rsp:1; 131 uint32_t has_rbp:1; 132 uint32_t has_rsi:1; 133 uint32_t has_rdi:1; 134 uint32_t has_r8:1; 135 uint32_t has_r9:1; 136 uint32_t has_r10:1; 137 uint32_t has_r11:1; 138 uint32_t has_r12:1; 139 uint32_t has_r13:1; 140 uint32_t has_r14:1; 141 uint32_t has_r15:1; 142 uint32_t has_unused_0:14; 143 uint32_t has_ip:1; 144 uint32_t has_applicable_counters:1; 145 uint32_t has_timestamp:1; 146 uint32_t has_unused_1:29; 147 uint32_t has_mem_access_address:1; 148 uint32_t has_mem_aux_info:1; 149 uint32_t has_mem_access_latency:1; 150 uint32_t has_tsx_aux_info:1; 151 uint32_t has_unused_2:28; 152 uint32_t has_lbr_0; 153 uint32_t has_lbr_1; 154 uint32_t has_lbr_2; 155 uint32_t has_xmm; 156 }; 157 }; 158 union { 159 uint64_t val[INTEL_PT_BLK_TYPE_CNT][INTEL_PT_BLK_ITEM_ID_CNT]; 160 struct { 161 struct { 162 uint64_t rflags; 163 uint64_t rip; 164 uint64_t rax; 165 uint64_t rcx; 166 uint64_t rdx; 167 uint64_t rbx; 168 uint64_t rsp; 169 uint64_t rbp; 170 uint64_t rsi; 171 uint64_t rdi; 172 uint64_t r8; 173 uint64_t r9; 174 uint64_t r10; 175 uint64_t r11; 176 uint64_t r12; 177 uint64_t r13; 178 uint64_t r14; 179 uint64_t r15; 180 uint64_t unused_0[INTEL_PT_BLK_ITEM_ID_CNT - 18]; 181 }; 182 struct { 183 uint64_t ip; 184 uint64_t applicable_counters; 185 uint64_t timestamp; 186 uint64_t unused_1[INTEL_PT_BLK_ITEM_ID_CNT - 3]; 187 }; 188 struct { 189 uint64_t mem_access_address; 190 uint64_t mem_aux_info; 191 uint64_t mem_access_latency; 192 uint64_t tsx_aux_info; 193 uint64_t unused_2[INTEL_PT_BLK_ITEM_ID_CNT - 4]; 194 }; 195 uint64_t lbr_0[INTEL_PT_BLK_ITEM_ID_CNT]; 196 uint64_t lbr_1[INTEL_PT_BLK_ITEM_ID_CNT]; 197 uint64_t lbr_2[INTEL_PT_BLK_ITEM_ID_CNT]; 198 uint64_t xmm[INTEL_PT_BLK_ITEM_ID_CNT]; 199 }; 200 }; 201 bool is_32_bit; 202 }; 203 204 struct intel_pt_vmcs_info { 205 struct rb_node rb_node; 206 uint64_t vmcs; 207 uint64_t tsc_offset; 208 bool reliable; 209 bool error_printed; 210 }; 211 212 struct intel_pt_state { 213 enum intel_pt_sample_type type; 214 bool from_nr; 215 bool to_nr; 216 int err; 217 uint64_t from_ip; 218 uint64_t to_ip; 219 uint64_t tot_insn_cnt; 220 uint64_t tot_cyc_cnt; 221 uint64_t cycles; 222 uint64_t timestamp; 223 uint64_t est_timestamp; 224 uint64_t trace_nr; 225 uint64_t ptw_payload; 226 uint64_t mwait_payload; 227 uint64_t pwre_payload; 228 uint64_t pwrx_payload; 229 uint64_t cbr_payload; 230 uint64_t psb_offset; 231 uint32_t cbr; 232 uint32_t flags; 233 enum intel_pt_insn_op insn_op; 234 int insn_len; 235 char insn[INTEL_PT_INSN_BUF_SZ]; 236 struct intel_pt_blk_items items; 237 }; 238 239 struct intel_pt_insn; 240 241 struct intel_pt_buffer { 242 const unsigned char *buf; 243 size_t len; 244 bool consecutive; 245 uint64_t ref_timestamp; 246 uint64_t trace_nr; 247 }; 248 249 typedef int (*intel_pt_lookahead_cb_t)(struct intel_pt_buffer *, void *); 250 251 struct intel_pt_params { 252 int (*get_trace)(struct intel_pt_buffer *buffer, void *data); 253 int (*walk_insn)(struct intel_pt_insn *intel_pt_insn, 254 uint64_t *insn_cnt_ptr, uint64_t *ip, uint64_t to_ip, 255 uint64_t max_insn_cnt, void *data); 256 bool (*pgd_ip)(uint64_t ip, void *data); 257 int (*lookahead)(void *data, intel_pt_lookahead_cb_t cb, void *cb_data); 258 struct intel_pt_vmcs_info *(*findnew_vmcs_info)(void *data, uint64_t vmcs); 259 void *data; 260 bool return_compression; 261 bool branch_enable; 262 bool vm_time_correlation; 263 bool vm_tm_corr_dry_run; 264 uint64_t first_timestamp; 265 uint64_t ctl; 266 uint64_t period; 267 enum intel_pt_period_type period_type; 268 unsigned max_non_turbo_ratio; 269 unsigned int mtc_period; 270 uint32_t tsc_ctc_ratio_n; 271 uint32_t tsc_ctc_ratio_d; 272 enum intel_pt_param_flags flags; 273 unsigned int quick; 274 int max_loops; 275 }; 276 277 struct intel_pt_decoder; 278 279 struct intel_pt_decoder *intel_pt_decoder_new(struct intel_pt_params *params); 280 void intel_pt_decoder_free(struct intel_pt_decoder *decoder); 281 282 const struct intel_pt_state *intel_pt_decode(struct intel_pt_decoder *decoder); 283 284 int intel_pt_fast_forward(struct intel_pt_decoder *decoder, uint64_t timestamp); 285 286 unsigned char *intel_pt_find_overlap(unsigned char *buf_a, size_t len_a, 287 unsigned char *buf_b, size_t len_b, 288 bool have_tsc, bool *consecutive, 289 bool ooo_tsc); 290 291 int intel_pt__strerror(int code, char *buf, size_t buflen); 292 293 void intel_pt_set_first_timestamp(struct intel_pt_decoder *decoder, 294 uint64_t first_timestamp); 295 296 #endif 297