1*5e91e57eSQi Liu /* SPDX-License-Identifier: GPL-2.0 */ 2*5e91e57eSQi Liu /* 3*5e91e57eSQi Liu * HiSilicon PCIe Trace and Tuning (PTT) support 4*5e91e57eSQi Liu * Copyright (c) 2022 HiSilicon Technologies Co., Ltd. 5*5e91e57eSQi Liu */ 6*5e91e57eSQi Liu 7*5e91e57eSQi Liu #ifndef INCLUDE__HISI_PTT_PKT_DECODER_H__ 8*5e91e57eSQi Liu #define INCLUDE__HISI_PTT_PKT_DECODER_H__ 9*5e91e57eSQi Liu 10*5e91e57eSQi Liu #include <stddef.h> 11*5e91e57eSQi Liu #include <stdint.h> 12*5e91e57eSQi Liu 13*5e91e57eSQi Liu #define HISI_PTT_8DW_CHECK_MASK GENMASK(31, 11) 14*5e91e57eSQi Liu #define HISI_PTT_IS_8DW_PKT GENMASK(31, 11) 15*5e91e57eSQi Liu #define HISI_PTT_MAX_SPACE_LEN 10 16*5e91e57eSQi Liu #define HISI_PTT_FIELD_LENTH 4 17*5e91e57eSQi Liu 18*5e91e57eSQi Liu enum hisi_ptt_pkt_type { 19*5e91e57eSQi Liu HISI_PTT_4DW_PKT, 20*5e91e57eSQi Liu HISI_PTT_8DW_PKT, 21*5e91e57eSQi Liu HISI_PTT_PKT_MAX 22*5e91e57eSQi Liu }; 23*5e91e57eSQi Liu 24*5e91e57eSQi Liu static int hisi_ptt_pkt_size[] = { 25*5e91e57eSQi Liu [HISI_PTT_4DW_PKT] = 16, 26*5e91e57eSQi Liu [HISI_PTT_8DW_PKT] = 32, 27*5e91e57eSQi Liu }; 28*5e91e57eSQi Liu 29*5e91e57eSQi Liu int hisi_ptt_pkt_desc(const unsigned char *buf, int pos, enum hisi_ptt_pkt_type type); 30*5e91e57eSQi Liu 31*5e91e57eSQi Liu #endif 32