1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__ 8 #define INCLUDE__UTIL_PERF_CS_ETM_H__ 9 10 #include "util/event.h" 11 #include "util/session.h" 12 13 /* Versionning header in case things need tro change in the future. That way 14 * decoding of old snapshot is still possible. 15 */ 16 enum { 17 /* Starting with 0x0 */ 18 CS_HEADER_VERSION_0, 19 /* PMU->type (32 bit), total # of CPUs (32 bit) */ 20 CS_PMU_TYPE_CPUS, 21 CS_ETM_SNAPSHOT, 22 CS_HEADER_VERSION_0_MAX, 23 }; 24 25 /* Beginning of header common to both ETMv3 and V4 */ 26 enum { 27 CS_ETM_MAGIC, 28 CS_ETM_CPU, 29 }; 30 31 /* ETMv3/PTM metadata */ 32 enum { 33 /* Dynamic, configurable parameters */ 34 CS_ETM_ETMCR = CS_ETM_CPU + 1, 35 CS_ETM_ETMTRACEIDR, 36 /* RO, taken from sysFS */ 37 CS_ETM_ETMCCER, 38 CS_ETM_ETMIDR, 39 CS_ETM_PRIV_MAX, 40 }; 41 42 /* ETMv4 metadata */ 43 enum { 44 /* Dynamic, configurable parameters */ 45 CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1, 46 CS_ETMV4_TRCTRACEIDR, 47 /* RO, taken from sysFS */ 48 CS_ETMV4_TRCIDR0, 49 CS_ETMV4_TRCIDR1, 50 CS_ETMV4_TRCIDR2, 51 CS_ETMV4_TRCIDR8, 52 CS_ETMV4_TRCAUTHSTATUS, 53 CS_ETMV4_PRIV_MAX, 54 }; 55 56 /* 57 * ETMv3 exception encoding number: 58 * See Embedded Trace Macrocell spcification (ARM IHI 0014Q) 59 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors. 60 */ 61 enum { 62 CS_ETMV3_EXC_NONE = 0, 63 CS_ETMV3_EXC_DEBUG_HALT = 1, 64 CS_ETMV3_EXC_SMC = 2, 65 CS_ETMV3_EXC_HYP = 3, 66 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4, 67 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5, 68 CS_ETMV3_EXC_PE_RESET = 8, 69 CS_ETMV3_EXC_UNDEFINED_INSTR = 9, 70 CS_ETMV3_EXC_SVC = 10, 71 CS_ETMV3_EXC_PREFETCH_ABORT = 11, 72 CS_ETMV3_EXC_DATA_FAULT = 12, 73 CS_ETMV3_EXC_GENERIC = 13, 74 CS_ETMV3_EXC_IRQ = 14, 75 CS_ETMV3_EXC_FIQ = 15, 76 }; 77 78 /* 79 * ETMv4 exception encoding number: 80 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D) 81 * table 6-12 Possible values for the TYPE field in an Exception instruction 82 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs. 83 */ 84 enum { 85 CS_ETMV4_EXC_RESET = 0, 86 CS_ETMV4_EXC_DEBUG_HALT = 1, 87 CS_ETMV4_EXC_CALL = 2, 88 CS_ETMV4_EXC_TRAP = 3, 89 CS_ETMV4_EXC_SYSTEM_ERROR = 4, 90 CS_ETMV4_EXC_INST_DEBUG = 6, 91 CS_ETMV4_EXC_DATA_DEBUG = 7, 92 CS_ETMV4_EXC_ALIGNMENT = 10, 93 CS_ETMV4_EXC_INST_FAULT = 11, 94 CS_ETMV4_EXC_DATA_FAULT = 12, 95 CS_ETMV4_EXC_IRQ = 14, 96 CS_ETMV4_EXC_FIQ = 15, 97 CS_ETMV4_EXC_END = 31, 98 }; 99 100 /* RB tree for quick conversion between traceID and metadata pointers */ 101 struct intlist *traceid_list; 102 103 #define KiB(x) ((x) * 1024) 104 #define MiB(x) ((x) * 1024 * 1024) 105 106 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64)) 107 108 #define __perf_cs_etmv3_magic 0x3030303030303030ULL 109 #define __perf_cs_etmv4_magic 0x4040404040404040ULL 110 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64)) 111 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64)) 112 113 #ifdef HAVE_CSTRACE_SUPPORT 114 int cs_etm__process_auxtrace_info(union perf_event *event, 115 struct perf_session *session); 116 int cs_etm__get_cpu(u8 trace_chan_id, int *cpu); 117 #else 118 static inline int 119 cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused, 120 struct perf_session *session __maybe_unused) 121 { 122 return -1; 123 } 124 125 static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused, 126 int *cpu __maybe_unused) 127 { 128 return -1; 129 } 130 #endif 131 132 #endif 133