1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__ 8 #define INCLUDE__UTIL_PERF_CS_ETM_H__ 9 10 #include "debug.h" 11 #include "util/event.h" 12 #include <linux/bits.h> 13 14 struct perf_session; 15 16 /* 17 * Versioning header in case things need to change in the future. That way 18 * decoding of old snapshot is still possible. 19 */ 20 enum { 21 /* Starting with 0x0 */ 22 CS_HEADER_VERSION, 23 /* PMU->type (32 bit), total # of CPUs (32 bit) */ 24 CS_PMU_TYPE_CPUS, 25 CS_ETM_SNAPSHOT, 26 CS_HEADER_VERSION_MAX, 27 }; 28 29 /* 30 * Update the version for new format. 31 * 32 * New version 1 format adds a param count to the per cpu metadata. 33 * This allows easy adding of new metadata parameters. 34 * Requires that new params always added after current ones. 35 * Also allows client reader to handle file versions that are different by 36 * checking the number of params in the file vs the number expected. 37 */ 38 #define CS_HEADER_CURRENT_VERSION 1 39 40 /* Beginning of header common to both ETMv3 and V4 */ 41 enum { 42 CS_ETM_MAGIC, 43 CS_ETM_CPU, 44 /* Number of trace config params in following ETM specific block */ 45 CS_ETM_NR_TRC_PARAMS, 46 CS_ETM_COMMON_BLK_MAX_V1, 47 }; 48 49 /* ETMv3/PTM metadata */ 50 enum { 51 /* Dynamic, configurable parameters */ 52 CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V1, 53 CS_ETM_ETMTRACEIDR, 54 /* RO, taken from sysFS */ 55 CS_ETM_ETMCCER, 56 CS_ETM_ETMIDR, 57 CS_ETM_PRIV_MAX, 58 }; 59 60 /* define fixed version 0 length - allow new format reader to read old files. */ 61 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1) 62 63 /* ETMv4 metadata */ 64 enum { 65 /* Dynamic, configurable parameters */ 66 CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1, 67 CS_ETMV4_TRCTRACEIDR, 68 /* RO, taken from sysFS */ 69 CS_ETMV4_TRCIDR0, 70 CS_ETMV4_TRCIDR1, 71 CS_ETMV4_TRCIDR2, 72 CS_ETMV4_TRCIDR8, 73 CS_ETMV4_TRCAUTHSTATUS, 74 CS_ETMV4_TS_SOURCE, 75 CS_ETMV4_PRIV_MAX, 76 }; 77 78 /* define fixed version 0 length - allow new format reader to read old files. */ 79 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1) 80 81 /* 82 * ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was 83 * added in header V1 84 */ 85 enum { 86 /* Dynamic, configurable parameters */ 87 CS_ETE_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1, 88 CS_ETE_TRCTRACEIDR, 89 /* RO, taken from sysFS */ 90 CS_ETE_TRCIDR0, 91 CS_ETE_TRCIDR1, 92 CS_ETE_TRCIDR2, 93 CS_ETE_TRCIDR8, 94 CS_ETE_TRCAUTHSTATUS, 95 CS_ETE_TRCDEVARCH, 96 CS_ETE_TS_SOURCE, 97 CS_ETE_PRIV_MAX 98 }; 99 100 /* 101 * ETMv3 exception encoding number: 102 * See Embedded Trace Macrocell specification (ARM IHI 0014Q) 103 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors. 104 */ 105 enum { 106 CS_ETMV3_EXC_NONE = 0, 107 CS_ETMV3_EXC_DEBUG_HALT = 1, 108 CS_ETMV3_EXC_SMC = 2, 109 CS_ETMV3_EXC_HYP = 3, 110 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4, 111 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5, 112 CS_ETMV3_EXC_PE_RESET = 8, 113 CS_ETMV3_EXC_UNDEFINED_INSTR = 9, 114 CS_ETMV3_EXC_SVC = 10, 115 CS_ETMV3_EXC_PREFETCH_ABORT = 11, 116 CS_ETMV3_EXC_DATA_FAULT = 12, 117 CS_ETMV3_EXC_GENERIC = 13, 118 CS_ETMV3_EXC_IRQ = 14, 119 CS_ETMV3_EXC_FIQ = 15, 120 }; 121 122 /* 123 * ETMv4 exception encoding number: 124 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D) 125 * table 6-12 Possible values for the TYPE field in an Exception instruction 126 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs. 127 */ 128 enum { 129 CS_ETMV4_EXC_RESET = 0, 130 CS_ETMV4_EXC_DEBUG_HALT = 1, 131 CS_ETMV4_EXC_CALL = 2, 132 CS_ETMV4_EXC_TRAP = 3, 133 CS_ETMV4_EXC_SYSTEM_ERROR = 4, 134 CS_ETMV4_EXC_INST_DEBUG = 6, 135 CS_ETMV4_EXC_DATA_DEBUG = 7, 136 CS_ETMV4_EXC_ALIGNMENT = 10, 137 CS_ETMV4_EXC_INST_FAULT = 11, 138 CS_ETMV4_EXC_DATA_FAULT = 12, 139 CS_ETMV4_EXC_IRQ = 14, 140 CS_ETMV4_EXC_FIQ = 15, 141 CS_ETMV4_EXC_END = 31, 142 }; 143 144 enum cs_etm_sample_type { 145 CS_ETM_EMPTY, 146 CS_ETM_RANGE, 147 CS_ETM_DISCONTINUITY, 148 CS_ETM_EXCEPTION, 149 CS_ETM_EXCEPTION_RET, 150 }; 151 152 enum cs_etm_isa { 153 CS_ETM_ISA_UNKNOWN, 154 CS_ETM_ISA_A64, 155 CS_ETM_ISA_A32, 156 CS_ETM_ISA_T32, 157 }; 158 159 struct cs_etm_queue; 160 161 struct cs_etm_packet { 162 enum cs_etm_sample_type sample_type; 163 enum cs_etm_isa isa; 164 u64 start_addr; 165 u64 end_addr; 166 u32 instr_count; 167 u32 last_instr_type; 168 u32 last_instr_subtype; 169 u32 flags; 170 u32 exception_number; 171 u8 last_instr_cond; 172 u8 last_instr_taken_branch; 173 u8 last_instr_size; 174 u8 trace_chan_id; 175 int cpu; 176 }; 177 178 #define CS_ETM_PACKET_MAX_BUFFER 1024 179 180 /* 181 * When working with per-thread scenarios the process under trace can 182 * be scheduled on any CPU and as such, more than one traceID may be 183 * associated with the same process. Since a traceID of '0' is illegal 184 * as per the CoreSight architecture, use that specific value to 185 * identify the queue where all packets (with any traceID) are 186 * aggregated. 187 */ 188 #define CS_ETM_PER_THREAD_TRACEID 0 189 190 struct cs_etm_packet_queue { 191 u32 packet_count; 192 u32 head; 193 u32 tail; 194 u32 instr_count; 195 u64 cs_timestamp; /* Timestamp from trace data, converted to ns if possible */ 196 u64 next_cs_timestamp; 197 struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER]; 198 }; 199 200 #define KiB(x) ((x) * 1024) 201 #define MiB(x) ((x) * 1024 * 1024) 202 203 #define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL 204 205 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) 206 207 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_MAX * sizeof(u64)) 208 209 #define __perf_cs_etmv3_magic 0x3030303030303030ULL 210 #define __perf_cs_etmv4_magic 0x4040404040404040ULL 211 #define __perf_cs_ete_magic 0x5050505050505050ULL 212 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64)) 213 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64)) 214 #define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * sizeof(u64)) 215 216 #define INFO_HEADER_SIZE (sizeof(((struct perf_record_auxtrace_info *)0)->type) + \ 217 sizeof(((struct perf_record_auxtrace_info *)0)->reserved__)) 218 219 int cs_etm__process_auxtrace_info(union perf_event *event, 220 struct perf_session *session); 221 222 #ifdef HAVE_CSTRACE_SUPPORT 223 int cs_etm__get_cpu(u8 trace_chan_id, int *cpu); 224 int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt); 225 int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq, 226 pid_t tid, u8 trace_chan_id); 227 bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq); 228 void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, 229 u8 trace_chan_id); 230 struct cs_etm_packet_queue 231 *cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id); 232 int cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused, 233 struct perf_session *session __maybe_unused); 234 u64 cs_etm__convert_sample_time(struct cs_etm_queue *etmq, u64 cs_timestamp); 235 #else 236 static inline int 237 cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused, 238 struct perf_session *session __maybe_unused) 239 { 240 pr_err("\nCS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1\n"); 241 return -1; 242 } 243 #endif 244 245 #endif 246