1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__ 8 #define INCLUDE__UTIL_PERF_CS_ETM_H__ 9 10 #include "debug.h" 11 #include "util/event.h" 12 #include <linux/bits.h> 13 14 struct perf_session; 15 16 /* 17 * Versioning header in case things need to change in the future. That way 18 * decoding of old snapshot is still possible. 19 */ 20 enum { 21 /* Starting with 0x0 */ 22 CS_HEADER_VERSION, 23 /* PMU->type (32 bit), total # of CPUs (32 bit) */ 24 CS_PMU_TYPE_CPUS, 25 CS_ETM_SNAPSHOT, 26 CS_HEADER_VERSION_MAX, 27 }; 28 29 /* 30 * Update the version for new format. 31 * 32 * New version 1 format adds a param count to the per cpu metadata. 33 * This allows easy adding of new metadata parameters. 34 * Requires that new params always added after current ones. 35 * Also allows client reader to handle file versions that are different by 36 * checking the number of params in the file vs the number expected. 37 */ 38 #define CS_HEADER_CURRENT_VERSION 1 39 40 /* Beginning of header common to both ETMv3 and V4 */ 41 enum { 42 CS_ETM_MAGIC, 43 CS_ETM_CPU, 44 /* Number of trace config params in following ETM specific block */ 45 CS_ETM_NR_TRC_PARAMS, 46 CS_ETM_COMMON_BLK_MAX_V1, 47 }; 48 49 /* ETMv3/PTM metadata */ 50 enum { 51 /* Dynamic, configurable parameters */ 52 CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V1, 53 CS_ETM_ETMTRACEIDR, 54 /* RO, taken from sysFS */ 55 CS_ETM_ETMCCER, 56 CS_ETM_ETMIDR, 57 CS_ETM_PRIV_MAX, 58 }; 59 60 /* define fixed version 0 length - allow new format reader to read old files. */ 61 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1) 62 63 /* ETMv4 metadata */ 64 enum { 65 /* Dynamic, configurable parameters */ 66 CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1, 67 CS_ETMV4_TRCTRACEIDR, 68 /* RO, taken from sysFS */ 69 CS_ETMV4_TRCIDR0, 70 CS_ETMV4_TRCIDR1, 71 CS_ETMV4_TRCIDR2, 72 CS_ETMV4_TRCIDR8, 73 CS_ETMV4_TRCAUTHSTATUS, 74 CS_ETMV4_PRIV_MAX, 75 }; 76 77 /* define fixed version 0 length - allow new format reader to read old files. */ 78 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1) 79 80 /* 81 * ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was 82 * added in header V1 83 */ 84 enum { 85 CS_ETE_TRCDEVARCH = CS_ETMV4_PRIV_MAX, 86 CS_ETE_PRIV_MAX 87 }; 88 89 /* 90 * ETMv3 exception encoding number: 91 * See Embedded Trace Macrocell specification (ARM IHI 0014Q) 92 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors. 93 */ 94 enum { 95 CS_ETMV3_EXC_NONE = 0, 96 CS_ETMV3_EXC_DEBUG_HALT = 1, 97 CS_ETMV3_EXC_SMC = 2, 98 CS_ETMV3_EXC_HYP = 3, 99 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4, 100 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5, 101 CS_ETMV3_EXC_PE_RESET = 8, 102 CS_ETMV3_EXC_UNDEFINED_INSTR = 9, 103 CS_ETMV3_EXC_SVC = 10, 104 CS_ETMV3_EXC_PREFETCH_ABORT = 11, 105 CS_ETMV3_EXC_DATA_FAULT = 12, 106 CS_ETMV3_EXC_GENERIC = 13, 107 CS_ETMV3_EXC_IRQ = 14, 108 CS_ETMV3_EXC_FIQ = 15, 109 }; 110 111 /* 112 * ETMv4 exception encoding number: 113 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D) 114 * table 6-12 Possible values for the TYPE field in an Exception instruction 115 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs. 116 */ 117 enum { 118 CS_ETMV4_EXC_RESET = 0, 119 CS_ETMV4_EXC_DEBUG_HALT = 1, 120 CS_ETMV4_EXC_CALL = 2, 121 CS_ETMV4_EXC_TRAP = 3, 122 CS_ETMV4_EXC_SYSTEM_ERROR = 4, 123 CS_ETMV4_EXC_INST_DEBUG = 6, 124 CS_ETMV4_EXC_DATA_DEBUG = 7, 125 CS_ETMV4_EXC_ALIGNMENT = 10, 126 CS_ETMV4_EXC_INST_FAULT = 11, 127 CS_ETMV4_EXC_DATA_FAULT = 12, 128 CS_ETMV4_EXC_IRQ = 14, 129 CS_ETMV4_EXC_FIQ = 15, 130 CS_ETMV4_EXC_END = 31, 131 }; 132 133 enum cs_etm_sample_type { 134 CS_ETM_EMPTY, 135 CS_ETM_RANGE, 136 CS_ETM_DISCONTINUITY, 137 CS_ETM_EXCEPTION, 138 CS_ETM_EXCEPTION_RET, 139 }; 140 141 enum cs_etm_isa { 142 CS_ETM_ISA_UNKNOWN, 143 CS_ETM_ISA_A64, 144 CS_ETM_ISA_A32, 145 CS_ETM_ISA_T32, 146 }; 147 148 struct cs_etm_queue; 149 150 struct cs_etm_packet { 151 enum cs_etm_sample_type sample_type; 152 enum cs_etm_isa isa; 153 u64 start_addr; 154 u64 end_addr; 155 u32 instr_count; 156 u32 last_instr_type; 157 u32 last_instr_subtype; 158 u32 flags; 159 u32 exception_number; 160 u8 last_instr_cond; 161 u8 last_instr_taken_branch; 162 u8 last_instr_size; 163 u8 trace_chan_id; 164 int cpu; 165 }; 166 167 #define CS_ETM_PACKET_MAX_BUFFER 1024 168 169 /* 170 * When working with per-thread scenarios the process under trace can 171 * be scheduled on any CPU and as such, more than one traceID may be 172 * associated with the same process. Since a traceID of '0' is illegal 173 * as per the CoreSight architecture, use that specific value to 174 * identify the queue where all packets (with any traceID) are 175 * aggregated. 176 */ 177 #define CS_ETM_PER_THREAD_TRACEID 0 178 179 struct cs_etm_packet_queue { 180 u32 packet_count; 181 u32 head; 182 u32 tail; 183 u32 instr_count; 184 u64 cs_timestamp; 185 u64 next_cs_timestamp; 186 struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER]; 187 }; 188 189 #define KiB(x) ((x) * 1024) 190 #define MiB(x) ((x) * 1024 * 1024) 191 192 #define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL 193 194 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) 195 196 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_MAX * sizeof(u64)) 197 198 #define __perf_cs_etmv3_magic 0x3030303030303030ULL 199 #define __perf_cs_etmv4_magic 0x4040404040404040ULL 200 #define __perf_cs_ete_magic 0x5050505050505050ULL 201 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64)) 202 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64)) 203 #define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * sizeof(u64)) 204 205 #define INFO_HEADER_SIZE (sizeof(((struct perf_record_auxtrace_info *)0)->type) + \ 206 sizeof(((struct perf_record_auxtrace_info *)0)->reserved__)) 207 208 int cs_etm__process_auxtrace_info(union perf_event *event, 209 struct perf_session *session); 210 211 #ifdef HAVE_CSTRACE_SUPPORT 212 int cs_etm__get_cpu(u8 trace_chan_id, int *cpu); 213 int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt); 214 int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq, 215 pid_t tid, u8 trace_chan_id); 216 bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq); 217 void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, 218 u8 trace_chan_id); 219 struct cs_etm_packet_queue 220 *cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id); 221 int cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused, 222 struct perf_session *session __maybe_unused); 223 #else 224 static inline int 225 cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused, 226 struct perf_session *session __maybe_unused) 227 { 228 pr_err("\nCS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1\n"); 229 return -1; 230 } 231 #endif 232 233 #endif 234