18a9fd832SMathieu Poirier /* SPDX-License-Identifier: GPL-2.0 */ 2a818c563SMathieu Poirier /* 3a818c563SMathieu Poirier * Copyright(C) 2015 Linaro Limited. All rights reserved. 4a818c563SMathieu Poirier * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5a818c563SMathieu Poirier */ 6a818c563SMathieu Poirier 7a818c563SMathieu Poirier #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__ 8a818c563SMathieu Poirier #define INCLUDE__UTIL_PERF_CS_ETM_H__ 9a818c563SMathieu Poirier 10fe55ba18SJames Clark #include "debug.h" 11440a23b3SMathieu Poirier #include "util/event.h" 12965e176fSArnaldo Carvalho de Melo #include <linux/bits.h> 13440a23b3SMathieu Poirier 14f2a39fe8SArnaldo Carvalho de Melo struct perf_session; 15f2a39fe8SArnaldo Carvalho de Melo 164d39c89fSIngo Molnar /* 174d39c89fSIngo Molnar * Versioning header in case things need to change in the future. That way 18a818c563SMathieu Poirier * decoding of old snapshot is still possible. 19a818c563SMathieu Poirier */ 20a818c563SMathieu Poirier enum { 21a818c563SMathieu Poirier /* Starting with 0x0 */ 2242b2b570SMike Leach CS_HEADER_VERSION, 23a818c563SMathieu Poirier /* PMU->type (32 bit), total # of CPUs (32 bit) */ 24a818c563SMathieu Poirier CS_PMU_TYPE_CPUS, 25a818c563SMathieu Poirier CS_ETM_SNAPSHOT, 2642b2b570SMike Leach CS_HEADER_VERSION_MAX, 27a818c563SMathieu Poirier }; 28a818c563SMathieu Poirier 2942b2b570SMike Leach /* 3042b2b570SMike Leach * Update the version for new format. 3142b2b570SMike Leach * 3242b2b570SMike Leach * New version 1 format adds a param count to the per cpu metadata. 3342b2b570SMike Leach * This allows easy adding of new metadata parameters. 3442b2b570SMike Leach * Requires that new params always added after current ones. 3542b2b570SMike Leach * Also allows client reader to handle file versions that are different by 3642b2b570SMike Leach * checking the number of params in the file vs the number expected. 3742b2b570SMike Leach */ 3842b2b570SMike Leach #define CS_HEADER_CURRENT_VERSION 1 3942b2b570SMike Leach 40a818c563SMathieu Poirier /* Beginning of header common to both ETMv3 and V4 */ 41a818c563SMathieu Poirier enum { 42a818c563SMathieu Poirier CS_ETM_MAGIC, 43a818c563SMathieu Poirier CS_ETM_CPU, 4442b2b570SMike Leach /* Number of trace config params in following ETM specific block */ 4542b2b570SMike Leach CS_ETM_NR_TRC_PARAMS, 4642b2b570SMike Leach CS_ETM_COMMON_BLK_MAX_V1, 47a818c563SMathieu Poirier }; 48a818c563SMathieu Poirier 49a818c563SMathieu Poirier /* ETMv3/PTM metadata */ 50a818c563SMathieu Poirier enum { 51a818c563SMathieu Poirier /* Dynamic, configurable parameters */ 5242b2b570SMike Leach CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V1, 53a818c563SMathieu Poirier CS_ETM_ETMTRACEIDR, 54a818c563SMathieu Poirier /* RO, taken from sysFS */ 55a818c563SMathieu Poirier CS_ETM_ETMCCER, 56a818c563SMathieu Poirier CS_ETM_ETMIDR, 57a818c563SMathieu Poirier CS_ETM_PRIV_MAX, 58a818c563SMathieu Poirier }; 59a818c563SMathieu Poirier 6042b2b570SMike Leach /* define fixed version 0 length - allow new format reader to read old files. */ 6142b2b570SMike Leach #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1) 6242b2b570SMike Leach 63a818c563SMathieu Poirier /* ETMv4 metadata */ 64a818c563SMathieu Poirier enum { 65a818c563SMathieu Poirier /* Dynamic, configurable parameters */ 6642b2b570SMike Leach CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1, 67a818c563SMathieu Poirier CS_ETMV4_TRCTRACEIDR, 68a818c563SMathieu Poirier /* RO, taken from sysFS */ 69a818c563SMathieu Poirier CS_ETMV4_TRCIDR0, 70a818c563SMathieu Poirier CS_ETMV4_TRCIDR1, 71a818c563SMathieu Poirier CS_ETMV4_TRCIDR2, 72a818c563SMathieu Poirier CS_ETMV4_TRCIDR8, 73a818c563SMathieu Poirier CS_ETMV4_TRCAUTHSTATUS, 74a818c563SMathieu Poirier CS_ETMV4_PRIV_MAX, 75a818c563SMathieu Poirier }; 76a818c563SMathieu Poirier 7742b2b570SMike Leach /* define fixed version 0 length - allow new format reader to read old files. */ 7842b2b570SMike Leach #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1) 7942b2b570SMike Leach 8096dce7f4SLeo Yan /* 8151ba8811SJames Clark * ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was 8251ba8811SJames Clark * added in header V1 8351ba8811SJames Clark */ 8451ba8811SJames Clark enum { 85*326163c5SGerman Gomez /* Dynamic, configurable parameters */ 86*326163c5SGerman Gomez CS_ETE_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1, 87*326163c5SGerman Gomez CS_ETE_TRCTRACEIDR, 88*326163c5SGerman Gomez /* RO, taken from sysFS */ 89*326163c5SGerman Gomez CS_ETE_TRCIDR0, 90*326163c5SGerman Gomez CS_ETE_TRCIDR1, 91*326163c5SGerman Gomez CS_ETE_TRCIDR2, 92*326163c5SGerman Gomez CS_ETE_TRCIDR8, 93*326163c5SGerman Gomez CS_ETE_TRCAUTHSTATUS, 94*326163c5SGerman Gomez CS_ETE_TRCDEVARCH, 9551ba8811SJames Clark CS_ETE_PRIV_MAX 9651ba8811SJames Clark }; 9751ba8811SJames Clark 9851ba8811SJames Clark /* 9996dce7f4SLeo Yan * ETMv3 exception encoding number: 1004d39c89fSIngo Molnar * See Embedded Trace Macrocell specification (ARM IHI 0014Q) 10196dce7f4SLeo Yan * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors. 10296dce7f4SLeo Yan */ 10396dce7f4SLeo Yan enum { 10496dce7f4SLeo Yan CS_ETMV3_EXC_NONE = 0, 10596dce7f4SLeo Yan CS_ETMV3_EXC_DEBUG_HALT = 1, 10696dce7f4SLeo Yan CS_ETMV3_EXC_SMC = 2, 10796dce7f4SLeo Yan CS_ETMV3_EXC_HYP = 3, 10896dce7f4SLeo Yan CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4, 10996dce7f4SLeo Yan CS_ETMV3_EXC_JAZELLE_THUMBEE = 5, 11096dce7f4SLeo Yan CS_ETMV3_EXC_PE_RESET = 8, 11196dce7f4SLeo Yan CS_ETMV3_EXC_UNDEFINED_INSTR = 9, 11296dce7f4SLeo Yan CS_ETMV3_EXC_SVC = 10, 11396dce7f4SLeo Yan CS_ETMV3_EXC_PREFETCH_ABORT = 11, 11496dce7f4SLeo Yan CS_ETMV3_EXC_DATA_FAULT = 12, 11596dce7f4SLeo Yan CS_ETMV3_EXC_GENERIC = 13, 11696dce7f4SLeo Yan CS_ETMV3_EXC_IRQ = 14, 11796dce7f4SLeo Yan CS_ETMV3_EXC_FIQ = 15, 11896dce7f4SLeo Yan }; 11996dce7f4SLeo Yan 12096dce7f4SLeo Yan /* 12196dce7f4SLeo Yan * ETMv4 exception encoding number: 12296dce7f4SLeo Yan * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D) 12396dce7f4SLeo Yan * table 6-12 Possible values for the TYPE field in an Exception instruction 12496dce7f4SLeo Yan * trace packet, for ARMv7-A/R and ARMv8-A/R PEs. 12596dce7f4SLeo Yan */ 12696dce7f4SLeo Yan enum { 12796dce7f4SLeo Yan CS_ETMV4_EXC_RESET = 0, 12896dce7f4SLeo Yan CS_ETMV4_EXC_DEBUG_HALT = 1, 12996dce7f4SLeo Yan CS_ETMV4_EXC_CALL = 2, 13096dce7f4SLeo Yan CS_ETMV4_EXC_TRAP = 3, 13196dce7f4SLeo Yan CS_ETMV4_EXC_SYSTEM_ERROR = 4, 13296dce7f4SLeo Yan CS_ETMV4_EXC_INST_DEBUG = 6, 13396dce7f4SLeo Yan CS_ETMV4_EXC_DATA_DEBUG = 7, 13496dce7f4SLeo Yan CS_ETMV4_EXC_ALIGNMENT = 10, 13596dce7f4SLeo Yan CS_ETMV4_EXC_INST_FAULT = 11, 13696dce7f4SLeo Yan CS_ETMV4_EXC_DATA_FAULT = 12, 13796dce7f4SLeo Yan CS_ETMV4_EXC_IRQ = 14, 13896dce7f4SLeo Yan CS_ETMV4_EXC_FIQ = 15, 13996dce7f4SLeo Yan CS_ETMV4_EXC_END = 31, 14096dce7f4SLeo Yan }; 14196dce7f4SLeo Yan 1425f7cb035SMathieu Poirier enum cs_etm_sample_type { 1435f7cb035SMathieu Poirier CS_ETM_EMPTY, 1445f7cb035SMathieu Poirier CS_ETM_RANGE, 1455f7cb035SMathieu Poirier CS_ETM_DISCONTINUITY, 1465f7cb035SMathieu Poirier CS_ETM_EXCEPTION, 1475f7cb035SMathieu Poirier CS_ETM_EXCEPTION_RET, 1485f7cb035SMathieu Poirier }; 1495f7cb035SMathieu Poirier 1505f7cb035SMathieu Poirier enum cs_etm_isa { 1515f7cb035SMathieu Poirier CS_ETM_ISA_UNKNOWN, 1525f7cb035SMathieu Poirier CS_ETM_ISA_A64, 1535f7cb035SMathieu Poirier CS_ETM_ISA_A32, 1545f7cb035SMathieu Poirier CS_ETM_ISA_T32, 1555f7cb035SMathieu Poirier }; 1565f7cb035SMathieu Poirier 1575f7cb035SMathieu Poirier struct cs_etm_queue; 1585f7cb035SMathieu Poirier 1595f7cb035SMathieu Poirier struct cs_etm_packet { 1605f7cb035SMathieu Poirier enum cs_etm_sample_type sample_type; 1615f7cb035SMathieu Poirier enum cs_etm_isa isa; 1625f7cb035SMathieu Poirier u64 start_addr; 1635f7cb035SMathieu Poirier u64 end_addr; 1645f7cb035SMathieu Poirier u32 instr_count; 1655f7cb035SMathieu Poirier u32 last_instr_type; 1665f7cb035SMathieu Poirier u32 last_instr_subtype; 1675f7cb035SMathieu Poirier u32 flags; 1685f7cb035SMathieu Poirier u32 exception_number; 1695f7cb035SMathieu Poirier u8 last_instr_cond; 1705f7cb035SMathieu Poirier u8 last_instr_taken_branch; 1715f7cb035SMathieu Poirier u8 last_instr_size; 1725f7cb035SMathieu Poirier u8 trace_chan_id; 1735f7cb035SMathieu Poirier int cpu; 1745f7cb035SMathieu Poirier }; 1755f7cb035SMathieu Poirier 1765f7cb035SMathieu Poirier #define CS_ETM_PACKET_MAX_BUFFER 1024 1775f7cb035SMathieu Poirier 178c7bfa2fdSMathieu Poirier /* 179c7bfa2fdSMathieu Poirier * When working with per-thread scenarios the process under trace can 180c7bfa2fdSMathieu Poirier * be scheduled on any CPU and as such, more than one traceID may be 181c7bfa2fdSMathieu Poirier * associated with the same process. Since a traceID of '0' is illegal 182c7bfa2fdSMathieu Poirier * as per the CoreSight architecture, use that specific value to 183c7bfa2fdSMathieu Poirier * identify the queue where all packets (with any traceID) are 184c7bfa2fdSMathieu Poirier * aggregated. 185c7bfa2fdSMathieu Poirier */ 186c7bfa2fdSMathieu Poirier #define CS_ETM_PER_THREAD_TRACEID 0 187c7bfa2fdSMathieu Poirier 1885f7cb035SMathieu Poirier struct cs_etm_packet_queue { 1895f7cb035SMathieu Poirier u32 packet_count; 1905f7cb035SMathieu Poirier u32 head; 1915f7cb035SMathieu Poirier u32 tail; 192675f302fSMathieu Poirier u32 instr_count; 193aadd6ba4SJames Clark u64 cs_timestamp; 194aadd6ba4SJames Clark u64 next_cs_timestamp; 1955f7cb035SMathieu Poirier struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER]; 1965f7cb035SMathieu Poirier }; 1975f7cb035SMathieu Poirier 198a818c563SMathieu Poirier #define KiB(x) ((x) * 1024) 199a818c563SMathieu Poirier #define MiB(x) ((x) * 1024 * 1024) 200a818c563SMathieu Poirier 2015f7cb035SMathieu Poirier #define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL 2025f7cb035SMathieu Poirier 2033399ad9aSMathieu Poirier #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) 2043399ad9aSMathieu Poirier 20542b2b570SMike Leach #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_MAX * sizeof(u64)) 206a818c563SMathieu Poirier 2072507a3d9SMathieu Poirier #define __perf_cs_etmv3_magic 0x3030303030303030ULL 2082507a3d9SMathieu Poirier #define __perf_cs_etmv4_magic 0x4040404040404040ULL 20951ba8811SJames Clark #define __perf_cs_ete_magic 0x5050505050505050ULL 210a818c563SMathieu Poirier #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64)) 211a818c563SMathieu Poirier #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64)) 21251ba8811SJames Clark #define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * sizeof(u64)) 213a818c563SMathieu Poirier 21455c1de99SJames Clark #define INFO_HEADER_SIZE (sizeof(((struct perf_record_auxtrace_info *)0)->type) + \ 21555c1de99SJames Clark sizeof(((struct perf_record_auxtrace_info *)0)->reserved__)) 21655c1de99SJames Clark 217440a23b3SMathieu Poirier int cs_etm__process_auxtrace_info(union perf_event *event, 218440a23b3SMathieu Poirier struct perf_session *session); 21955c1de99SJames Clark 22055c1de99SJames Clark #ifdef HAVE_CSTRACE_SUPPORT 22195c6fe97SLeo Yan int cs_etm__get_cpu(u8 trace_chan_id, int *cpu); 22247f0d94cSLeo Yan int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt); 2230a6be300SMathieu Poirier int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq, 2240a6be300SMathieu Poirier pid_t tid, u8 trace_chan_id); 225675f302fSMathieu Poirier bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq); 226675f302fSMathieu Poirier void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, 227675f302fSMathieu Poirier u8 trace_chan_id); 2285f7cb035SMathieu Poirier struct cs_etm_packet_queue 229c7bfa2fdSMathieu Poirier *cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id); 23055c1de99SJames Clark int cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused, 23155c1de99SJames Clark struct perf_session *session __maybe_unused); 232440a23b3SMathieu Poirier #else 233440a23b3SMathieu Poirier static inline int 23455c1de99SJames Clark cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused, 235440a23b3SMathieu Poirier struct perf_session *session __maybe_unused) 236440a23b3SMathieu Poirier { 237fe55ba18SJames Clark pr_err("\nCS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1\n"); 238440a23b3SMathieu Poirier return -1; 239440a23b3SMathieu Poirier } 240440a23b3SMathieu Poirier #endif 241440a23b3SMathieu Poirier 242a818c563SMathieu Poirier #endif 243