1[
2    {
3        "BriefDescription": "Cycles the divider is busy",
4        "Counter": "0,1,2,3",
5        "EventCode": "0x14",
6        "EventName": "ARITH.CYCLES_DIV_BUSY",
7        "SampleAfterValue": "2000000",
8        "UMask": "0x1"
9    },
10    {
11        "BriefDescription": "Divide Operations executed",
12        "Counter": "0,1,2,3",
13        "CounterMask": "1",
14        "EdgeDetect": "1",
15        "EventCode": "0x14",
16        "EventName": "ARITH.DIV",
17        "Invert": "1",
18        "SampleAfterValue": "2000000",
19        "UMask": "0x1"
20    },
21    {
22        "BriefDescription": "Multiply operations executed",
23        "Counter": "0,1,2,3",
24        "EventCode": "0x14",
25        "EventName": "ARITH.MUL",
26        "SampleAfterValue": "2000000",
27        "UMask": "0x2"
28    },
29    {
30        "BriefDescription": "BACLEAR asserted with bad target address",
31        "Counter": "0,1,2,3",
32        "EventCode": "0xE6",
33        "EventName": "BACLEAR.BAD_TARGET",
34        "SampleAfterValue": "2000000",
35        "UMask": "0x2"
36    },
37    {
38        "BriefDescription": "BACLEAR asserted, regardless of cause",
39        "Counter": "0,1,2,3",
40        "EventCode": "0xE6",
41        "EventName": "BACLEAR.CLEAR",
42        "SampleAfterValue": "2000000",
43        "UMask": "0x1"
44    },
45    {
46        "BriefDescription": "Instruction queue forced BACLEAR",
47        "Counter": "0,1,2,3",
48        "EventCode": "0xA7",
49        "EventName": "BACLEAR_FORCE_IQ",
50        "SampleAfterValue": "2000000",
51        "UMask": "0x1"
52    },
53    {
54        "BriefDescription": "Branch instructions decoded",
55        "Counter": "0,1,2,3",
56        "EventCode": "0xE0",
57        "EventName": "BR_INST_DECODED",
58        "SampleAfterValue": "2000000",
59        "UMask": "0x1"
60    },
61    {
62        "BriefDescription": "Branch instructions executed",
63        "Counter": "0,1,2,3",
64        "EventCode": "0x88",
65        "EventName": "BR_INST_EXEC.ANY",
66        "SampleAfterValue": "200000",
67        "UMask": "0x7f"
68    },
69    {
70        "BriefDescription": "Conditional branch instructions executed",
71        "Counter": "0,1,2,3",
72        "EventCode": "0x88",
73        "EventName": "BR_INST_EXEC.COND",
74        "SampleAfterValue": "200000",
75        "UMask": "0x1"
76    },
77    {
78        "BriefDescription": "Unconditional branches executed",
79        "Counter": "0,1,2,3",
80        "EventCode": "0x88",
81        "EventName": "BR_INST_EXEC.DIRECT",
82        "SampleAfterValue": "200000",
83        "UMask": "0x2"
84    },
85    {
86        "BriefDescription": "Unconditional call branches executed",
87        "Counter": "0,1,2,3",
88        "EventCode": "0x88",
89        "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
90        "SampleAfterValue": "20000",
91        "UMask": "0x10"
92    },
93    {
94        "BriefDescription": "Indirect call branches executed",
95        "Counter": "0,1,2,3",
96        "EventCode": "0x88",
97        "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
98        "SampleAfterValue": "20000",
99        "UMask": "0x20"
100    },
101    {
102        "BriefDescription": "Indirect non call branches executed",
103        "Counter": "0,1,2,3",
104        "EventCode": "0x88",
105        "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
106        "SampleAfterValue": "20000",
107        "UMask": "0x4"
108    },
109    {
110        "BriefDescription": "Call branches executed",
111        "Counter": "0,1,2,3",
112        "EventCode": "0x88",
113        "EventName": "BR_INST_EXEC.NEAR_CALLS",
114        "SampleAfterValue": "20000",
115        "UMask": "0x30"
116    },
117    {
118        "BriefDescription": "All non call branches executed",
119        "Counter": "0,1,2,3",
120        "EventCode": "0x88",
121        "EventName": "BR_INST_EXEC.NON_CALLS",
122        "SampleAfterValue": "200000",
123        "UMask": "0x7"
124    },
125    {
126        "BriefDescription": "Indirect return branches executed",
127        "Counter": "0,1,2,3",
128        "EventCode": "0x88",
129        "EventName": "BR_INST_EXEC.RETURN_NEAR",
130        "SampleAfterValue": "20000",
131        "UMask": "0x8"
132    },
133    {
134        "BriefDescription": "Taken branches executed",
135        "Counter": "0,1,2,3",
136        "EventCode": "0x88",
137        "EventName": "BR_INST_EXEC.TAKEN",
138        "SampleAfterValue": "200000",
139        "UMask": "0x40"
140    },
141    {
142        "BriefDescription": "Retired branch instructions (Precise Event)",
143        "Counter": "0,1,2,3",
144        "EventCode": "0xC4",
145        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
146        "PEBS": "1",
147        "SampleAfterValue": "200000",
148        "UMask": "0x4"
149    },
150    {
151        "BriefDescription": "Retired conditional branch instructions (Precise Event)",
152        "Counter": "0,1,2,3",
153        "EventCode": "0xC4",
154        "EventName": "BR_INST_RETIRED.CONDITIONAL",
155        "PEBS": "1",
156        "SampleAfterValue": "200000",
157        "UMask": "0x1"
158    },
159    {
160        "BriefDescription": "Retired near call instructions (Precise Event)",
161        "Counter": "0,1,2,3",
162        "EventCode": "0xC4",
163        "EventName": "BR_INST_RETIRED.NEAR_CALL",
164        "PEBS": "1",
165        "SampleAfterValue": "20000",
166        "UMask": "0x2"
167    },
168    {
169        "BriefDescription": "Mispredicted branches executed",
170        "Counter": "0,1,2,3",
171        "EventCode": "0x89",
172        "EventName": "BR_MISP_EXEC.ANY",
173        "SampleAfterValue": "20000",
174        "UMask": "0x7f"
175    },
176    {
177        "BriefDescription": "Mispredicted conditional branches executed",
178        "Counter": "0,1,2,3",
179        "EventCode": "0x89",
180        "EventName": "BR_MISP_EXEC.COND",
181        "SampleAfterValue": "20000",
182        "UMask": "0x1"
183    },
184    {
185        "BriefDescription": "Mispredicted unconditional branches executed",
186        "Counter": "0,1,2,3",
187        "EventCode": "0x89",
188        "EventName": "BR_MISP_EXEC.DIRECT",
189        "SampleAfterValue": "20000",
190        "UMask": "0x2"
191    },
192    {
193        "BriefDescription": "Mispredicted non call branches executed",
194        "Counter": "0,1,2,3",
195        "EventCode": "0x89",
196        "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
197        "SampleAfterValue": "2000",
198        "UMask": "0x10"
199    },
200    {
201        "BriefDescription": "Mispredicted indirect call branches executed",
202        "Counter": "0,1,2,3",
203        "EventCode": "0x89",
204        "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
205        "SampleAfterValue": "2000",
206        "UMask": "0x20"
207    },
208    {
209        "BriefDescription": "Mispredicted indirect non call branches executed",
210        "Counter": "0,1,2,3",
211        "EventCode": "0x89",
212        "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
213        "SampleAfterValue": "2000",
214        "UMask": "0x4"
215    },
216    {
217        "BriefDescription": "Mispredicted call branches executed",
218        "Counter": "0,1,2,3",
219        "EventCode": "0x89",
220        "EventName": "BR_MISP_EXEC.NEAR_CALLS",
221        "SampleAfterValue": "2000",
222        "UMask": "0x30"
223    },
224    {
225        "BriefDescription": "Mispredicted non call branches executed",
226        "Counter": "0,1,2,3",
227        "EventCode": "0x89",
228        "EventName": "BR_MISP_EXEC.NON_CALLS",
229        "SampleAfterValue": "20000",
230        "UMask": "0x7"
231    },
232    {
233        "BriefDescription": "Mispredicted return branches executed",
234        "Counter": "0,1,2,3",
235        "EventCode": "0x89",
236        "EventName": "BR_MISP_EXEC.RETURN_NEAR",
237        "SampleAfterValue": "2000",
238        "UMask": "0x8"
239    },
240    {
241        "BriefDescription": "Mispredicted taken branches executed",
242        "Counter": "0,1,2,3",
243        "EventCode": "0x89",
244        "EventName": "BR_MISP_EXEC.TAKEN",
245        "SampleAfterValue": "20000",
246        "UMask": "0x40"
247    },
248    {
249        "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
250        "Counter": "0,1,2,3",
251        "EventCode": "0xC5",
252        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
253        "PEBS": "1",
254        "SampleAfterValue": "20000",
255        "UMask": "0x4"
256    },
257    {
258        "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
259        "Counter": "0,1,2,3",
260        "EventCode": "0xC5",
261        "EventName": "BR_MISP_RETIRED.CONDITIONAL",
262        "PEBS": "1",
263        "SampleAfterValue": "20000",
264        "UMask": "0x1"
265    },
266    {
267        "BriefDescription": "Mispredicted near retired calls (Precise Event)",
268        "Counter": "0,1,2,3",
269        "EventCode": "0xC5",
270        "EventName": "BR_MISP_RETIRED.NEAR_CALL",
271        "PEBS": "1",
272        "SampleAfterValue": "2000",
273        "UMask": "0x2"
274    },
275    {
276        "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
277        "Counter": "Fixed counter 3",
278        "EventCode": "0x0",
279        "EventName": "CPU_CLK_UNHALTED.REF",
280        "SampleAfterValue": "2000000",
281        "UMask": "0x0"
282    },
283    {
284        "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
285        "Counter": "0,1,2,3",
286        "EventCode": "0x3C",
287        "EventName": "CPU_CLK_UNHALTED.REF_P",
288        "SampleAfterValue": "100000",
289        "UMask": "0x1"
290    },
291    {
292        "BriefDescription": "Cycles when thread is not halted (fixed counter)",
293        "Counter": "Fixed counter 2",
294        "EventCode": "0x0",
295        "EventName": "CPU_CLK_UNHALTED.THREAD",
296        "SampleAfterValue": "2000000",
297        "UMask": "0x0"
298    },
299    {
300        "BriefDescription": "Cycles when thread is not halted (programmable counter)",
301        "Counter": "0,1,2,3",
302        "EventCode": "0x3C",
303        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
304        "SampleAfterValue": "2000000",
305        "UMask": "0x0"
306    },
307    {
308        "BriefDescription": "Total CPU cycles",
309        "Counter": "0,1,2,3",
310        "CounterMask": "2",
311        "EventCode": "0x3C",
312        "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
313        "Invert": "1",
314        "SampleAfterValue": "2000000",
315        "UMask": "0x0"
316    },
317    {
318        "BriefDescription": "Any Instruction Length Decoder stall cycles",
319        "Counter": "0,1,2,3",
320        "EventCode": "0x87",
321        "EventName": "ILD_STALL.ANY",
322        "SampleAfterValue": "2000000",
323        "UMask": "0xf"
324    },
325    {
326        "BriefDescription": "Instruction Queue full stall cycles",
327        "Counter": "0,1,2,3",
328        "EventCode": "0x87",
329        "EventName": "ILD_STALL.IQ_FULL",
330        "SampleAfterValue": "2000000",
331        "UMask": "0x4"
332    },
333    {
334        "BriefDescription": "Length Change Prefix stall cycles",
335        "Counter": "0,1,2,3",
336        "EventCode": "0x87",
337        "EventName": "ILD_STALL.LCP",
338        "SampleAfterValue": "2000000",
339        "UMask": "0x1"
340    },
341    {
342        "BriefDescription": "Stall cycles due to BPU MRU bypass",
343        "Counter": "0,1,2,3",
344        "EventCode": "0x87",
345        "EventName": "ILD_STALL.MRU",
346        "SampleAfterValue": "2000000",
347        "UMask": "0x2"
348    },
349    {
350        "BriefDescription": "Regen stall cycles",
351        "Counter": "0,1,2,3",
352        "EventCode": "0x87",
353        "EventName": "ILD_STALL.REGEN",
354        "SampleAfterValue": "2000000",
355        "UMask": "0x8"
356    },
357    {
358        "BriefDescription": "Instructions that must be decoded by decoder 0",
359        "Counter": "0,1,2,3",
360        "EventCode": "0x18",
361        "EventName": "INST_DECODED.DEC0",
362        "SampleAfterValue": "2000000",
363        "UMask": "0x1"
364    },
365    {
366        "BriefDescription": "Instructions written to instruction queue.",
367        "Counter": "0,1,2,3",
368        "EventCode": "0x17",
369        "EventName": "INST_QUEUE_WRITES",
370        "SampleAfterValue": "2000000",
371        "UMask": "0x1"
372    },
373    {
374        "BriefDescription": "Cycles instructions are written to the instruction queue",
375        "Counter": "0,1,2,3",
376        "EventCode": "0x1E",
377        "EventName": "INST_QUEUE_WRITE_CYCLES",
378        "SampleAfterValue": "2000000",
379        "UMask": "0x1"
380    },
381    {
382        "BriefDescription": "Instructions retired (fixed counter)",
383        "Counter": "Fixed counter 1",
384        "EventCode": "0x0",
385        "EventName": "INST_RETIRED.ANY",
386        "SampleAfterValue": "2000000",
387        "UMask": "0x0"
388    },
389    {
390        "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
391        "Counter": "0,1,2,3",
392        "EventCode": "0xC0",
393        "EventName": "INST_RETIRED.ANY_P",
394        "PEBS": "1",
395        "SampleAfterValue": "2000000",
396        "UMask": "0x1"
397    },
398    {
399        "BriefDescription": "Retired MMX instructions (Precise Event)",
400        "Counter": "0,1,2,3",
401        "EventCode": "0xC0",
402        "EventName": "INST_RETIRED.MMX",
403        "PEBS": "1",
404        "SampleAfterValue": "2000000",
405        "UMask": "0x4"
406    },
407    {
408        "BriefDescription": "Total cycles (Precise Event)",
409        "Counter": "0,1,2,3",
410        "CounterMask": "16",
411        "EventCode": "0xC0",
412        "EventName": "INST_RETIRED.TOTAL_CYCLES",
413        "Invert": "1",
414        "PEBS": "1",
415        "SampleAfterValue": "2000000",
416        "UMask": "0x1"
417    },
418    {
419        "BriefDescription": "Total cycles (Precise Event)",
420        "Counter": "0,1,2,3",
421        "CounterMask": "16",
422        "EventCode": "0xC0",
423        "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
424        "Invert": "1",
425        "PEBS": "2",
426        "SampleAfterValue": "2000000",
427        "UMask": "0x1"
428    },
429    {
430        "BriefDescription": "Retired floating-point operations (Precise Event)",
431        "Counter": "0,1,2,3",
432        "EventCode": "0xC0",
433        "EventName": "INST_RETIRED.X87",
434        "PEBS": "1",
435        "SampleAfterValue": "2000000",
436        "UMask": "0x2"
437    },
438    {
439        "BriefDescription": "Load operations conflicting with software prefetches",
440        "Counter": "0,1",
441        "EventCode": "0x4C",
442        "EventName": "LOAD_HIT_PRE",
443        "SampleAfterValue": "200000",
444        "UMask": "0x1"
445    },
446    {
447        "BriefDescription": "Cycles when uops were delivered by the LSD",
448        "Counter": "0,1,2,3",
449        "CounterMask": "1",
450        "EventCode": "0xA8",
451        "EventName": "LSD.ACTIVE",
452        "SampleAfterValue": "2000000",
453        "UMask": "0x1"
454    },
455    {
456        "BriefDescription": "Cycles no uops were delivered by the LSD",
457        "Counter": "0,1,2,3",
458        "CounterMask": "1",
459        "EventCode": "0xA8",
460        "EventName": "LSD.INACTIVE",
461        "Invert": "1",
462        "SampleAfterValue": "2000000",
463        "UMask": "0x1"
464    },
465    {
466        "BriefDescription": "Loops that can't stream from the instruction queue",
467        "Counter": "0,1,2,3",
468        "EventCode": "0x20",
469        "EventName": "LSD_OVERFLOW",
470        "SampleAfterValue": "2000000",
471        "UMask": "0x1"
472    },
473    {
474        "BriefDescription": "Cycles machine clear asserted",
475        "Counter": "0,1,2,3",
476        "EventCode": "0xC3",
477        "EventName": "MACHINE_CLEARS.CYCLES",
478        "SampleAfterValue": "20000",
479        "UMask": "0x1"
480    },
481    {
482        "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
483        "Counter": "0,1,2,3",
484        "EventCode": "0xC3",
485        "EventName": "MACHINE_CLEARS.MEM_ORDER",
486        "SampleAfterValue": "20000",
487        "UMask": "0x2"
488    },
489    {
490        "BriefDescription": "Self-Modifying Code detected",
491        "Counter": "0,1,2,3",
492        "EventCode": "0xC3",
493        "EventName": "MACHINE_CLEARS.SMC",
494        "SampleAfterValue": "20000",
495        "UMask": "0x4"
496    },
497    {
498        "BriefDescription": "Resource related stall cycles",
499        "Counter": "0,1,2,3",
500        "EventCode": "0xA2",
501        "EventName": "RESOURCE_STALLS.ANY",
502        "SampleAfterValue": "2000000",
503        "UMask": "0x1"
504    },
505    {
506        "BriefDescription": "FPU control word write stall cycles",
507        "Counter": "0,1,2,3",
508        "EventCode": "0xA2",
509        "EventName": "RESOURCE_STALLS.FPCW",
510        "SampleAfterValue": "2000000",
511        "UMask": "0x20"
512    },
513    {
514        "BriefDescription": "Load buffer stall cycles",
515        "Counter": "0,1,2,3",
516        "EventCode": "0xA2",
517        "EventName": "RESOURCE_STALLS.LOAD",
518        "SampleAfterValue": "2000000",
519        "UMask": "0x2"
520    },
521    {
522        "BriefDescription": "MXCSR rename stall cycles",
523        "Counter": "0,1,2,3",
524        "EventCode": "0xA2",
525        "EventName": "RESOURCE_STALLS.MXCSR",
526        "SampleAfterValue": "2000000",
527        "UMask": "0x40"
528    },
529    {
530        "BriefDescription": "Other Resource related stall cycles",
531        "Counter": "0,1,2,3",
532        "EventCode": "0xA2",
533        "EventName": "RESOURCE_STALLS.OTHER",
534        "SampleAfterValue": "2000000",
535        "UMask": "0x80"
536    },
537    {
538        "BriefDescription": "ROB full stall cycles",
539        "Counter": "0,1,2,3",
540        "EventCode": "0xA2",
541        "EventName": "RESOURCE_STALLS.ROB_FULL",
542        "SampleAfterValue": "2000000",
543        "UMask": "0x10"
544    },
545    {
546        "BriefDescription": "Reservation Station full stall cycles",
547        "Counter": "0,1,2,3",
548        "EventCode": "0xA2",
549        "EventName": "RESOURCE_STALLS.RS_FULL",
550        "SampleAfterValue": "2000000",
551        "UMask": "0x4"
552    },
553    {
554        "BriefDescription": "Store buffer stall cycles",
555        "Counter": "0,1,2,3",
556        "EventCode": "0xA2",
557        "EventName": "RESOURCE_STALLS.STORE",
558        "SampleAfterValue": "2000000",
559        "UMask": "0x8"
560    },
561    {
562        "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
563        "Counter": "0,1,2,3",
564        "EventCode": "0xC7",
565        "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
566        "PEBS": "1",
567        "SampleAfterValue": "200000",
568        "UMask": "0x4"
569    },
570    {
571        "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
572        "Counter": "0,1,2,3",
573        "EventCode": "0xC7",
574        "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
575        "PEBS": "1",
576        "SampleAfterValue": "200000",
577        "UMask": "0x1"
578    },
579    {
580        "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
581        "Counter": "0,1,2,3",
582        "EventCode": "0xC7",
583        "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
584        "PEBS": "1",
585        "SampleAfterValue": "200000",
586        "UMask": "0x8"
587    },
588    {
589        "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
590        "Counter": "0,1,2,3",
591        "EventCode": "0xC7",
592        "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
593        "PEBS": "1",
594        "SampleAfterValue": "200000",
595        "UMask": "0x2"
596    },
597    {
598        "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
599        "Counter": "0,1,2,3",
600        "EventCode": "0xC7",
601        "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
602        "PEBS": "1",
603        "SampleAfterValue": "200000",
604        "UMask": "0x10"
605    },
606    {
607        "BriefDescription": "Stack pointer instructions decoded",
608        "Counter": "0,1,2,3",
609        "EventCode": "0xD1",
610        "EventName": "UOPS_DECODED.ESP_FOLDING",
611        "SampleAfterValue": "2000000",
612        "UMask": "0x4"
613    },
614    {
615        "BriefDescription": "Stack pointer sync operations",
616        "Counter": "0,1,2,3",
617        "EventCode": "0xD1",
618        "EventName": "UOPS_DECODED.ESP_SYNC",
619        "SampleAfterValue": "2000000",
620        "UMask": "0x8"
621    },
622    {
623        "BriefDescription": "Uops decoded by Microcode Sequencer",
624        "Counter": "0,1,2,3",
625        "CounterMask": "1",
626        "EventCode": "0xD1",
627        "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
628        "SampleAfterValue": "2000000",
629        "UMask": "0x2"
630    },
631    {
632        "BriefDescription": "Cycles no Uops are decoded",
633        "Counter": "0,1,2,3",
634        "CounterMask": "1",
635        "EventCode": "0xD1",
636        "EventName": "UOPS_DECODED.STALL_CYCLES",
637        "Invert": "1",
638        "SampleAfterValue": "2000000",
639        "UMask": "0x1"
640    },
641    {
642        "AnyThread": "1",
643        "BriefDescription": "Cycles Uops executed on any port (core count)",
644        "Counter": "0,1,2,3",
645        "CounterMask": "1",
646        "EventCode": "0xB1",
647        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
648        "SampleAfterValue": "2000000",
649        "UMask": "0x3f"
650    },
651    {
652        "AnyThread": "1",
653        "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
654        "Counter": "0,1,2,3",
655        "CounterMask": "1",
656        "EventCode": "0xB1",
657        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
658        "SampleAfterValue": "2000000",
659        "UMask": "0x1f"
660    },
661    {
662        "BriefDescription": "Uops executed on any port (core count)",
663        "Counter": "0,1,2,3",
664        "CounterMask": "1",
665        "EdgeDetect": "1",
666        "EventCode": "0xB1",
667        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
668        "Invert": "1",
669        "SampleAfterValue": "2000000",
670        "UMask": "0x3f"
671    },
672    {
673        "BriefDescription": "Uops executed on ports 0-4 (core count)",
674        "Counter": "0,1,2,3",
675        "CounterMask": "1",
676        "EdgeDetect": "1",
677        "EventCode": "0xB1",
678        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
679        "Invert": "1",
680        "SampleAfterValue": "2000000",
681        "UMask": "0x1f"
682    },
683    {
684        "AnyThread": "1",
685        "BriefDescription": "Cycles no Uops issued on any port (core count)",
686        "Counter": "0,1,2,3",
687        "CounterMask": "1",
688        "EventCode": "0xB1",
689        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
690        "Invert": "1",
691        "SampleAfterValue": "2000000",
692        "UMask": "0x3f"
693    },
694    {
695        "AnyThread": "1",
696        "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
697        "Counter": "0,1,2,3",
698        "CounterMask": "1",
699        "EventCode": "0xB1",
700        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
701        "Invert": "1",
702        "SampleAfterValue": "2000000",
703        "UMask": "0x1f"
704    },
705    {
706        "BriefDescription": "Uops executed on port 0",
707        "Counter": "0,1,2,3",
708        "EventCode": "0xB1",
709        "EventName": "UOPS_EXECUTED.PORT0",
710        "SampleAfterValue": "2000000",
711        "UMask": "0x1"
712    },
713    {
714        "BriefDescription": "Uops issued on ports 0, 1 or 5",
715        "Counter": "0,1,2,3",
716        "EventCode": "0xB1",
717        "EventName": "UOPS_EXECUTED.PORT015",
718        "SampleAfterValue": "2000000",
719        "UMask": "0x40"
720    },
721    {
722        "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
723        "Counter": "0,1,2,3",
724        "CounterMask": "1",
725        "EventCode": "0xB1",
726        "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
727        "Invert": "1",
728        "SampleAfterValue": "2000000",
729        "UMask": "0x40"
730    },
731    {
732        "BriefDescription": "Uops executed on port 1",
733        "Counter": "0,1,2,3",
734        "EventCode": "0xB1",
735        "EventName": "UOPS_EXECUTED.PORT1",
736        "SampleAfterValue": "2000000",
737        "UMask": "0x2"
738    },
739    {
740        "AnyThread": "1",
741        "BriefDescription": "Uops issued on ports 2, 3 or 4",
742        "Counter": "0,1,2,3",
743        "EventCode": "0xB1",
744        "EventName": "UOPS_EXECUTED.PORT234_CORE",
745        "SampleAfterValue": "2000000",
746        "UMask": "0x80"
747    },
748    {
749        "AnyThread": "1",
750        "BriefDescription": "Uops executed on port 2 (core count)",
751        "Counter": "0,1,2,3",
752        "EventCode": "0xB1",
753        "EventName": "UOPS_EXECUTED.PORT2_CORE",
754        "SampleAfterValue": "2000000",
755        "UMask": "0x4"
756    },
757    {
758        "AnyThread": "1",
759        "BriefDescription": "Uops executed on port 3 (core count)",
760        "Counter": "0,1,2,3",
761        "EventCode": "0xB1",
762        "EventName": "UOPS_EXECUTED.PORT3_CORE",
763        "SampleAfterValue": "2000000",
764        "UMask": "0x8"
765    },
766    {
767        "AnyThread": "1",
768        "BriefDescription": "Uops executed on port 4 (core count)",
769        "Counter": "0,1,2,3",
770        "EventCode": "0xB1",
771        "EventName": "UOPS_EXECUTED.PORT4_CORE",
772        "SampleAfterValue": "2000000",
773        "UMask": "0x10"
774    },
775    {
776        "BriefDescription": "Uops executed on port 5",
777        "Counter": "0,1,2,3",
778        "EventCode": "0xB1",
779        "EventName": "UOPS_EXECUTED.PORT5",
780        "SampleAfterValue": "2000000",
781        "UMask": "0x20"
782    },
783    {
784        "BriefDescription": "Uops issued",
785        "Counter": "0,1,2,3",
786        "EventCode": "0xE",
787        "EventName": "UOPS_ISSUED.ANY",
788        "SampleAfterValue": "2000000",
789        "UMask": "0x1"
790    },
791    {
792        "AnyThread": "1",
793        "BriefDescription": "Cycles no Uops were issued on any thread",
794        "Counter": "0,1,2,3",
795        "CounterMask": "1",
796        "EventCode": "0xE",
797        "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
798        "Invert": "1",
799        "SampleAfterValue": "2000000",
800        "UMask": "0x1"
801    },
802    {
803        "AnyThread": "1",
804        "BriefDescription": "Cycles Uops were issued on either thread",
805        "Counter": "0,1,2,3",
806        "CounterMask": "1",
807        "EventCode": "0xE",
808        "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
809        "SampleAfterValue": "2000000",
810        "UMask": "0x1"
811    },
812    {
813        "BriefDescription": "Fused Uops issued",
814        "Counter": "0,1,2,3",
815        "EventCode": "0xE",
816        "EventName": "UOPS_ISSUED.FUSED",
817        "SampleAfterValue": "2000000",
818        "UMask": "0x2"
819    },
820    {
821        "BriefDescription": "Cycles no Uops were issued",
822        "Counter": "0,1,2,3",
823        "CounterMask": "1",
824        "EventCode": "0xE",
825        "EventName": "UOPS_ISSUED.STALL_CYCLES",
826        "Invert": "1",
827        "SampleAfterValue": "2000000",
828        "UMask": "0x1"
829    },
830    {
831        "BriefDescription": "Cycles Uops are being retired",
832        "Counter": "0,1,2,3",
833        "CounterMask": "1",
834        "EventCode": "0xC2",
835        "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
836        "PEBS": "1",
837        "SampleAfterValue": "2000000",
838        "UMask": "0x1"
839    },
840    {
841        "BriefDescription": "Uops retired (Precise Event)",
842        "Counter": "0,1,2,3",
843        "EventCode": "0xC2",
844        "EventName": "UOPS_RETIRED.ANY",
845        "PEBS": "1",
846        "SampleAfterValue": "2000000",
847        "UMask": "0x1"
848    },
849    {
850        "BriefDescription": "Macro-fused Uops retired (Precise Event)",
851        "Counter": "0,1,2,3",
852        "EventCode": "0xC2",
853        "EventName": "UOPS_RETIRED.MACRO_FUSED",
854        "PEBS": "1",
855        "SampleAfterValue": "2000000",
856        "UMask": "0x4"
857    },
858    {
859        "BriefDescription": "Retirement slots used (Precise Event)",
860        "Counter": "0,1,2,3",
861        "EventCode": "0xC2",
862        "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
863        "PEBS": "1",
864        "SampleAfterValue": "2000000",
865        "UMask": "0x2"
866    },
867    {
868        "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
869        "Counter": "0,1,2,3",
870        "CounterMask": "1",
871        "EventCode": "0xC2",
872        "EventName": "UOPS_RETIRED.STALL_CYCLES",
873        "Invert": "1",
874        "PEBS": "1",
875        "SampleAfterValue": "2000000",
876        "UMask": "0x1"
877    },
878    {
879        "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
880        "Counter": "0,1,2,3",
881        "CounterMask": "16",
882        "EventCode": "0xC2",
883        "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
884        "Invert": "1",
885        "PEBS": "1",
886        "SampleAfterValue": "2000000",
887        "UMask": "0x1"
888    },
889    {
890        "BriefDescription": "Uop unfusions due to FP exceptions",
891        "Counter": "0,1,2,3",
892        "EventCode": "0xDB",
893        "EventName": "UOP_UNFUSION",
894        "SampleAfterValue": "2000000",
895        "UMask": "0x1"
896    }
897]