1[
2    {
3        "BriefDescription": "Cycles L1D locked",
4        "EventCode": "0x63",
5        "EventName": "CACHE_LOCK_CYCLES.L1D",
6        "SampleAfterValue": "2000000",
7        "UMask": "0x2"
8    },
9    {
10        "BriefDescription": "Cycles L1D and L2 locked",
11        "EventCode": "0x63",
12        "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
13        "SampleAfterValue": "2000000",
14        "UMask": "0x1"
15    },
16    {
17        "BriefDescription": "L1D cache lines replaced in M state",
18        "EventCode": "0x51",
19        "EventName": "L1D.M_EVICT",
20        "SampleAfterValue": "2000000",
21        "UMask": "0x4"
22    },
23    {
24        "BriefDescription": "L1D cache lines allocated in the M state",
25        "EventCode": "0x51",
26        "EventName": "L1D.M_REPL",
27        "SampleAfterValue": "2000000",
28        "UMask": "0x2"
29    },
30    {
31        "BriefDescription": "L1D snoop eviction of cache lines in M state",
32        "EventCode": "0x51",
33        "EventName": "L1D.M_SNOOP_EVICT",
34        "SampleAfterValue": "2000000",
35        "UMask": "0x8"
36    },
37    {
38        "BriefDescription": "L1 data cache lines allocated",
39        "EventCode": "0x51",
40        "EventName": "L1D.REPL",
41        "SampleAfterValue": "2000000",
42        "UMask": "0x1"
43    },
44    {
45        "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
46        "EventCode": "0x52",
47        "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
48        "SampleAfterValue": "2000000",
49        "UMask": "0x1"
50    },
51    {
52        "BriefDescription": "L1D hardware prefetch misses",
53        "EventCode": "0x4E",
54        "EventName": "L1D_PREFETCH.MISS",
55        "SampleAfterValue": "200000",
56        "UMask": "0x2"
57    },
58    {
59        "BriefDescription": "L1D hardware prefetch requests",
60        "EventCode": "0x4E",
61        "EventName": "L1D_PREFETCH.REQUESTS",
62        "SampleAfterValue": "200000",
63        "UMask": "0x1"
64    },
65    {
66        "BriefDescription": "L1D hardware prefetch requests triggered",
67        "EventCode": "0x4E",
68        "EventName": "L1D_PREFETCH.TRIGGERS",
69        "SampleAfterValue": "200000",
70        "UMask": "0x4"
71    },
72    {
73        "BriefDescription": "L1 writebacks to L2 in E state",
74        "EventCode": "0x28",
75        "EventName": "L1D_WB_L2.E_STATE",
76        "SampleAfterValue": "100000",
77        "UMask": "0x4"
78    },
79    {
80        "BriefDescription": "L1 writebacks to L2 in I state (misses)",
81        "EventCode": "0x28",
82        "EventName": "L1D_WB_L2.I_STATE",
83        "SampleAfterValue": "100000",
84        "UMask": "0x1"
85    },
86    {
87        "BriefDescription": "All L1 writebacks to L2",
88        "EventCode": "0x28",
89        "EventName": "L1D_WB_L2.MESI",
90        "SampleAfterValue": "100000",
91        "UMask": "0xf"
92    },
93    {
94        "BriefDescription": "L1 writebacks to L2 in M state",
95        "EventCode": "0x28",
96        "EventName": "L1D_WB_L2.M_STATE",
97        "SampleAfterValue": "100000",
98        "UMask": "0x8"
99    },
100    {
101        "BriefDescription": "L1 writebacks to L2 in S state",
102        "EventCode": "0x28",
103        "EventName": "L1D_WB_L2.S_STATE",
104        "SampleAfterValue": "100000",
105        "UMask": "0x2"
106    },
107    {
108        "BriefDescription": "All L2 data requests",
109        "EventCode": "0x26",
110        "EventName": "L2_DATA_RQSTS.ANY",
111        "SampleAfterValue": "200000",
112        "UMask": "0xff"
113    },
114    {
115        "BriefDescription": "L2 data demand loads in E state",
116        "EventCode": "0x26",
117        "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
118        "SampleAfterValue": "200000",
119        "UMask": "0x4"
120    },
121    {
122        "BriefDescription": "L2 data demand loads in I state (misses)",
123        "EventCode": "0x26",
124        "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
125        "SampleAfterValue": "200000",
126        "UMask": "0x1"
127    },
128    {
129        "BriefDescription": "L2 data demand requests",
130        "EventCode": "0x26",
131        "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
132        "SampleAfterValue": "200000",
133        "UMask": "0xf"
134    },
135    {
136        "BriefDescription": "L2 data demand loads in M state",
137        "EventCode": "0x26",
138        "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
139        "SampleAfterValue": "200000",
140        "UMask": "0x8"
141    },
142    {
143        "BriefDescription": "L2 data demand loads in S state",
144        "EventCode": "0x26",
145        "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
146        "SampleAfterValue": "200000",
147        "UMask": "0x2"
148    },
149    {
150        "BriefDescription": "L2 data prefetches in E state",
151        "EventCode": "0x26",
152        "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
153        "SampleAfterValue": "200000",
154        "UMask": "0x40"
155    },
156    {
157        "BriefDescription": "L2 data prefetches in the I state (misses)",
158        "EventCode": "0x26",
159        "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
160        "SampleAfterValue": "200000",
161        "UMask": "0x10"
162    },
163    {
164        "BriefDescription": "All L2 data prefetches",
165        "EventCode": "0x26",
166        "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
167        "SampleAfterValue": "200000",
168        "UMask": "0xf0"
169    },
170    {
171        "BriefDescription": "L2 data prefetches in M state",
172        "EventCode": "0x26",
173        "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
174        "SampleAfterValue": "200000",
175        "UMask": "0x80"
176    },
177    {
178        "BriefDescription": "L2 data prefetches in the S state",
179        "EventCode": "0x26",
180        "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
181        "SampleAfterValue": "200000",
182        "UMask": "0x20"
183    },
184    {
185        "BriefDescription": "L2 lines alloacated",
186        "EventCode": "0xF1",
187        "EventName": "L2_LINES_IN.ANY",
188        "SampleAfterValue": "100000",
189        "UMask": "0x7"
190    },
191    {
192        "BriefDescription": "L2 lines allocated in the E state",
193        "EventCode": "0xF1",
194        "EventName": "L2_LINES_IN.E_STATE",
195        "SampleAfterValue": "100000",
196        "UMask": "0x4"
197    },
198    {
199        "BriefDescription": "L2 lines allocated in the S state",
200        "EventCode": "0xF1",
201        "EventName": "L2_LINES_IN.S_STATE",
202        "SampleAfterValue": "100000",
203        "UMask": "0x2"
204    },
205    {
206        "BriefDescription": "L2 lines evicted",
207        "EventCode": "0xF2",
208        "EventName": "L2_LINES_OUT.ANY",
209        "SampleAfterValue": "100000",
210        "UMask": "0xf"
211    },
212    {
213        "BriefDescription": "L2 lines evicted by a demand request",
214        "EventCode": "0xF2",
215        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
216        "SampleAfterValue": "100000",
217        "UMask": "0x1"
218    },
219    {
220        "BriefDescription": "L2 modified lines evicted by a demand request",
221        "EventCode": "0xF2",
222        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
223        "SampleAfterValue": "100000",
224        "UMask": "0x2"
225    },
226    {
227        "BriefDescription": "L2 lines evicted by a prefetch request",
228        "EventCode": "0xF2",
229        "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
230        "SampleAfterValue": "100000",
231        "UMask": "0x4"
232    },
233    {
234        "BriefDescription": "L2 modified lines evicted by a prefetch request",
235        "EventCode": "0xF2",
236        "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
237        "SampleAfterValue": "100000",
238        "UMask": "0x8"
239    },
240    {
241        "BriefDescription": "L2 instruction fetches",
242        "EventCode": "0x24",
243        "EventName": "L2_RQSTS.IFETCHES",
244        "SampleAfterValue": "200000",
245        "UMask": "0x30"
246    },
247    {
248        "BriefDescription": "L2 instruction fetch hits",
249        "EventCode": "0x24",
250        "EventName": "L2_RQSTS.IFETCH_HIT",
251        "SampleAfterValue": "200000",
252        "UMask": "0x10"
253    },
254    {
255        "BriefDescription": "L2 instruction fetch misses",
256        "EventCode": "0x24",
257        "EventName": "L2_RQSTS.IFETCH_MISS",
258        "SampleAfterValue": "200000",
259        "UMask": "0x20"
260    },
261    {
262        "BriefDescription": "L2 load hits",
263        "EventCode": "0x24",
264        "EventName": "L2_RQSTS.LD_HIT",
265        "SampleAfterValue": "200000",
266        "UMask": "0x1"
267    },
268    {
269        "BriefDescription": "L2 load misses",
270        "EventCode": "0x24",
271        "EventName": "L2_RQSTS.LD_MISS",
272        "SampleAfterValue": "200000",
273        "UMask": "0x2"
274    },
275    {
276        "BriefDescription": "L2 requests",
277        "EventCode": "0x24",
278        "EventName": "L2_RQSTS.LOADS",
279        "SampleAfterValue": "200000",
280        "UMask": "0x3"
281    },
282    {
283        "BriefDescription": "All L2 misses",
284        "EventCode": "0x24",
285        "EventName": "L2_RQSTS.MISS",
286        "SampleAfterValue": "200000",
287        "UMask": "0xaa"
288    },
289    {
290        "BriefDescription": "All L2 prefetches",
291        "EventCode": "0x24",
292        "EventName": "L2_RQSTS.PREFETCHES",
293        "SampleAfterValue": "200000",
294        "UMask": "0xc0"
295    },
296    {
297        "BriefDescription": "L2 prefetch hits",
298        "EventCode": "0x24",
299        "EventName": "L2_RQSTS.PREFETCH_HIT",
300        "SampleAfterValue": "200000",
301        "UMask": "0x40"
302    },
303    {
304        "BriefDescription": "L2 prefetch misses",
305        "EventCode": "0x24",
306        "EventName": "L2_RQSTS.PREFETCH_MISS",
307        "SampleAfterValue": "200000",
308        "UMask": "0x80"
309    },
310    {
311        "BriefDescription": "All L2 requests",
312        "EventCode": "0x24",
313        "EventName": "L2_RQSTS.REFERENCES",
314        "SampleAfterValue": "200000",
315        "UMask": "0xff"
316    },
317    {
318        "BriefDescription": "L2 RFO requests",
319        "EventCode": "0x24",
320        "EventName": "L2_RQSTS.RFOS",
321        "SampleAfterValue": "200000",
322        "UMask": "0xc"
323    },
324    {
325        "BriefDescription": "L2 RFO hits",
326        "EventCode": "0x24",
327        "EventName": "L2_RQSTS.RFO_HIT",
328        "SampleAfterValue": "200000",
329        "UMask": "0x4"
330    },
331    {
332        "BriefDescription": "L2 RFO misses",
333        "EventCode": "0x24",
334        "EventName": "L2_RQSTS.RFO_MISS",
335        "SampleAfterValue": "200000",
336        "UMask": "0x8"
337    },
338    {
339        "BriefDescription": "All L2 transactions",
340        "EventCode": "0xF0",
341        "EventName": "L2_TRANSACTIONS.ANY",
342        "SampleAfterValue": "200000",
343        "UMask": "0x80"
344    },
345    {
346        "BriefDescription": "L2 fill transactions",
347        "EventCode": "0xF0",
348        "EventName": "L2_TRANSACTIONS.FILL",
349        "SampleAfterValue": "200000",
350        "UMask": "0x20"
351    },
352    {
353        "BriefDescription": "L2 instruction fetch transactions",
354        "EventCode": "0xF0",
355        "EventName": "L2_TRANSACTIONS.IFETCH",
356        "SampleAfterValue": "200000",
357        "UMask": "0x4"
358    },
359    {
360        "BriefDescription": "L1D writeback to L2 transactions",
361        "EventCode": "0xF0",
362        "EventName": "L2_TRANSACTIONS.L1D_WB",
363        "SampleAfterValue": "200000",
364        "UMask": "0x10"
365    },
366    {
367        "BriefDescription": "L2 Load transactions",
368        "EventCode": "0xF0",
369        "EventName": "L2_TRANSACTIONS.LOAD",
370        "SampleAfterValue": "200000",
371        "UMask": "0x1"
372    },
373    {
374        "BriefDescription": "L2 prefetch transactions",
375        "EventCode": "0xF0",
376        "EventName": "L2_TRANSACTIONS.PREFETCH",
377        "SampleAfterValue": "200000",
378        "UMask": "0x8"
379    },
380    {
381        "BriefDescription": "L2 RFO transactions",
382        "EventCode": "0xF0",
383        "EventName": "L2_TRANSACTIONS.RFO",
384        "SampleAfterValue": "200000",
385        "UMask": "0x2"
386    },
387    {
388        "BriefDescription": "L2 writeback to LLC transactions",
389        "EventCode": "0xF0",
390        "EventName": "L2_TRANSACTIONS.WB",
391        "SampleAfterValue": "200000",
392        "UMask": "0x40"
393    },
394    {
395        "BriefDescription": "L2 demand lock RFOs in E state",
396        "EventCode": "0x27",
397        "EventName": "L2_WRITE.LOCK.E_STATE",
398        "SampleAfterValue": "100000",
399        "UMask": "0x40"
400    },
401    {
402        "BriefDescription": "All demand L2 lock RFOs that hit the cache",
403        "EventCode": "0x27",
404        "EventName": "L2_WRITE.LOCK.HIT",
405        "SampleAfterValue": "100000",
406        "UMask": "0xe0"
407    },
408    {
409        "BriefDescription": "L2 demand lock RFOs in I state (misses)",
410        "EventCode": "0x27",
411        "EventName": "L2_WRITE.LOCK.I_STATE",
412        "SampleAfterValue": "100000",
413        "UMask": "0x10"
414    },
415    {
416        "BriefDescription": "All demand L2 lock RFOs",
417        "EventCode": "0x27",
418        "EventName": "L2_WRITE.LOCK.MESI",
419        "SampleAfterValue": "100000",
420        "UMask": "0xf0"
421    },
422    {
423        "BriefDescription": "L2 demand lock RFOs in M state",
424        "EventCode": "0x27",
425        "EventName": "L2_WRITE.LOCK.M_STATE",
426        "SampleAfterValue": "100000",
427        "UMask": "0x80"
428    },
429    {
430        "BriefDescription": "L2 demand lock RFOs in S state",
431        "EventCode": "0x27",
432        "EventName": "L2_WRITE.LOCK.S_STATE",
433        "SampleAfterValue": "100000",
434        "UMask": "0x20"
435    },
436    {
437        "BriefDescription": "All L2 demand store RFOs that hit the cache",
438        "EventCode": "0x27",
439        "EventName": "L2_WRITE.RFO.HIT",
440        "SampleAfterValue": "100000",
441        "UMask": "0xe"
442    },
443    {
444        "BriefDescription": "L2 demand store RFOs in I state (misses)",
445        "EventCode": "0x27",
446        "EventName": "L2_WRITE.RFO.I_STATE",
447        "SampleAfterValue": "100000",
448        "UMask": "0x1"
449    },
450    {
451        "BriefDescription": "All L2 demand store RFOs",
452        "EventCode": "0x27",
453        "EventName": "L2_WRITE.RFO.MESI",
454        "SampleAfterValue": "100000",
455        "UMask": "0xf"
456    },
457    {
458        "BriefDescription": "L2 demand store RFOs in M state",
459        "EventCode": "0x27",
460        "EventName": "L2_WRITE.RFO.M_STATE",
461        "SampleAfterValue": "100000",
462        "UMask": "0x8"
463    },
464    {
465        "BriefDescription": "L2 demand store RFOs in S state",
466        "EventCode": "0x27",
467        "EventName": "L2_WRITE.RFO.S_STATE",
468        "SampleAfterValue": "100000",
469        "UMask": "0x2"
470    },
471    {
472        "BriefDescription": "Longest latency cache miss",
473        "EventCode": "0x2E",
474        "EventName": "LONGEST_LAT_CACHE.MISS",
475        "SampleAfterValue": "100000",
476        "UMask": "0x41"
477    },
478    {
479        "BriefDescription": "Longest latency cache reference",
480        "EventCode": "0x2E",
481        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
482        "SampleAfterValue": "200000",
483        "UMask": "0x4f"
484    },
485    {
486        "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
487        "EventCode": "0xB",
488        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
489        "MSRIndex": "0x3F6",
490        "PEBS": "2",
491        "SampleAfterValue": "2000000",
492        "UMask": "0x10"
493    },
494    {
495        "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
496        "EventCode": "0xB",
497        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
498        "MSRIndex": "0x3F6",
499        "MSRValue": "0x400",
500        "PEBS": "2",
501        "SampleAfterValue": "100",
502        "UMask": "0x10"
503    },
504    {
505        "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
506        "EventCode": "0xB",
507        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
508        "MSRIndex": "0x3F6",
509        "MSRValue": "0x80",
510        "PEBS": "2",
511        "SampleAfterValue": "1000",
512        "UMask": "0x10"
513    },
514    {
515        "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
516        "EventCode": "0xB",
517        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
518        "MSRIndex": "0x3F6",
519        "MSRValue": "0x10",
520        "PEBS": "2",
521        "SampleAfterValue": "10000",
522        "UMask": "0x10"
523    },
524    {
525        "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
526        "EventCode": "0xB",
527        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
528        "MSRIndex": "0x3F6",
529        "MSRValue": "0x4000",
530        "PEBS": "2",
531        "SampleAfterValue": "5",
532        "UMask": "0x10"
533    },
534    {
535        "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
536        "EventCode": "0xB",
537        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
538        "MSRIndex": "0x3F6",
539        "MSRValue": "0x800",
540        "PEBS": "2",
541        "SampleAfterValue": "50",
542        "UMask": "0x10"
543    },
544    {
545        "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
546        "EventCode": "0xB",
547        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
548        "MSRIndex": "0x3F6",
549        "MSRValue": "0x100",
550        "PEBS": "2",
551        "SampleAfterValue": "500",
552        "UMask": "0x10"
553    },
554    {
555        "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
556        "EventCode": "0xB",
557        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
558        "MSRIndex": "0x3F6",
559        "MSRValue": "0x20",
560        "PEBS": "2",
561        "SampleAfterValue": "5000",
562        "UMask": "0x10"
563    },
564    {
565        "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
566        "EventCode": "0xB",
567        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
568        "MSRIndex": "0x3F6",
569        "MSRValue": "0x8000",
570        "PEBS": "2",
571        "SampleAfterValue": "3",
572        "UMask": "0x10"
573    },
574    {
575        "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
576        "EventCode": "0xB",
577        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
578        "MSRIndex": "0x3F6",
579        "MSRValue": "0x4",
580        "PEBS": "2",
581        "SampleAfterValue": "50000",
582        "UMask": "0x10"
583    },
584    {
585        "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
586        "EventCode": "0xB",
587        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
588        "MSRIndex": "0x3F6",
589        "MSRValue": "0x1000",
590        "PEBS": "2",
591        "SampleAfterValue": "20",
592        "UMask": "0x10"
593    },
594    {
595        "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
596        "EventCode": "0xB",
597        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
598        "MSRIndex": "0x3F6",
599        "MSRValue": "0x200",
600        "PEBS": "2",
601        "SampleAfterValue": "200",
602        "UMask": "0x10"
603    },
604    {
605        "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
606        "EventCode": "0xB",
607        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
608        "MSRIndex": "0x3F6",
609        "MSRValue": "0x40",
610        "PEBS": "2",
611        "SampleAfterValue": "2000",
612        "UMask": "0x10"
613    },
614    {
615        "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
616        "EventCode": "0xB",
617        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
618        "MSRIndex": "0x3F6",
619        "MSRValue": "0x8",
620        "PEBS": "2",
621        "SampleAfterValue": "20000",
622        "UMask": "0x10"
623    },
624    {
625        "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
626        "EventCode": "0xB",
627        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
628        "MSRIndex": "0x3F6",
629        "MSRValue": "0x2000",
630        "PEBS": "2",
631        "SampleAfterValue": "10",
632        "UMask": "0x10"
633    },
634    {
635        "BriefDescription": "Instructions retired which contains a load (Precise Event)",
636        "EventCode": "0xB",
637        "EventName": "MEM_INST_RETIRED.LOADS",
638        "PEBS": "1",
639        "SampleAfterValue": "2000000",
640        "UMask": "0x1"
641    },
642    {
643        "BriefDescription": "Instructions retired which contains a store (Precise Event)",
644        "EventCode": "0xB",
645        "EventName": "MEM_INST_RETIRED.STORES",
646        "PEBS": "1",
647        "SampleAfterValue": "2000000",
648        "UMask": "0x2"
649    },
650    {
651        "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
652        "EventCode": "0xCB",
653        "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
654        "PEBS": "1",
655        "SampleAfterValue": "200000",
656        "UMask": "0x40"
657    },
658    {
659        "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
660        "EventCode": "0xCB",
661        "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
662        "PEBS": "1",
663        "SampleAfterValue": "2000000",
664        "UMask": "0x1"
665    },
666    {
667        "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
668        "EventCode": "0xCB",
669        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
670        "PEBS": "1",
671        "SampleAfterValue": "200000",
672        "UMask": "0x2"
673    },
674    {
675        "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
676        "EventCode": "0xCB",
677        "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
678        "PEBS": "1",
679        "SampleAfterValue": "10000",
680        "UMask": "0x10"
681    },
682    {
683        "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
684        "EventCode": "0xCB",
685        "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
686        "PEBS": "1",
687        "SampleAfterValue": "40000",
688        "UMask": "0x4"
689    },
690    {
691        "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
692        "EventCode": "0xCB",
693        "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
694        "PEBS": "1",
695        "SampleAfterValue": "40000",
696        "UMask": "0x8"
697    },
698    {
699        "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)",
700        "EventCode": "0xF",
701        "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
702        "PEBS": "1",
703        "SampleAfterValue": "20000",
704        "UMask": "0x8"
705    },
706    {
707        "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
708        "EventCode": "0xF",
709        "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM",
710        "PEBS": "1",
711        "SampleAfterValue": "40000",
712        "UMask": "0x2"
713    },
714    {
715        "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
716        "EventCode": "0xF",
717        "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
718        "PEBS": "1",
719        "SampleAfterValue": "10000",
720        "UMask": "0x20"
721    },
722    {
723        "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)",
724        "EventCode": "0xF",
725        "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM",
726        "PEBS": "1",
727        "SampleAfterValue": "40000",
728        "UMask": "0x4"
729    },
730    {
731        "BriefDescription": "Load instructions retired IO (Precise Event)",
732        "EventCode": "0xF",
733        "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
734        "PEBS": "1",
735        "SampleAfterValue": "4000",
736        "UMask": "0x80"
737    },
738    {
739        "BriefDescription": "All offcore requests",
740        "EventCode": "0xB0",
741        "EventName": "OFFCORE_REQUESTS.ANY",
742        "SampleAfterValue": "100000",
743        "UMask": "0x80"
744    },
745    {
746        "BriefDescription": "Offcore read requests",
747        "EventCode": "0xB0",
748        "EventName": "OFFCORE_REQUESTS.ANY.READ",
749        "SampleAfterValue": "100000",
750        "UMask": "0x8"
751    },
752    {
753        "BriefDescription": "Offcore RFO requests",
754        "EventCode": "0xB0",
755        "EventName": "OFFCORE_REQUESTS.ANY.RFO",
756        "SampleAfterValue": "100000",
757        "UMask": "0x10"
758    },
759    {
760        "BriefDescription": "Offcore demand code read requests",
761        "EventCode": "0xB0",
762        "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
763        "SampleAfterValue": "100000",
764        "UMask": "0x2"
765    },
766    {
767        "BriefDescription": "Offcore demand data read requests",
768        "EventCode": "0xB0",
769        "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
770        "SampleAfterValue": "100000",
771        "UMask": "0x1"
772    },
773    {
774        "BriefDescription": "Offcore demand RFO requests",
775        "EventCode": "0xB0",
776        "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
777        "SampleAfterValue": "100000",
778        "UMask": "0x4"
779    },
780    {
781        "BriefDescription": "Offcore L1 data cache writebacks",
782        "EventCode": "0xB0",
783        "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
784        "SampleAfterValue": "100000",
785        "UMask": "0x40"
786    },
787    {
788        "BriefDescription": "Outstanding offcore reads",
789        "EventCode": "0x60",
790        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
791        "SampleAfterValue": "2000000",
792        "UMask": "0x8"
793    },
794    {
795        "BriefDescription": "Cycles offcore reads busy",
796        "CounterMask": "1",
797        "EventCode": "0x60",
798        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
799        "SampleAfterValue": "2000000",
800        "UMask": "0x8"
801    },
802    {
803        "BriefDescription": "Outstanding offcore demand code reads",
804        "EventCode": "0x60",
805        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
806        "SampleAfterValue": "2000000",
807        "UMask": "0x2"
808    },
809    {
810        "BriefDescription": "Cycles offcore demand code read busy",
811        "CounterMask": "1",
812        "EventCode": "0x60",
813        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
814        "SampleAfterValue": "2000000",
815        "UMask": "0x2"
816    },
817    {
818        "BriefDescription": "Outstanding offcore demand data reads",
819        "EventCode": "0x60",
820        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
821        "SampleAfterValue": "2000000",
822        "UMask": "0x1"
823    },
824    {
825        "BriefDescription": "Cycles offcore demand data read busy",
826        "CounterMask": "1",
827        "EventCode": "0x60",
828        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
829        "SampleAfterValue": "2000000",
830        "UMask": "0x1"
831    },
832    {
833        "BriefDescription": "Outstanding offcore demand RFOs",
834        "EventCode": "0x60",
835        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
836        "SampleAfterValue": "2000000",
837        "UMask": "0x4"
838    },
839    {
840        "BriefDescription": "Cycles offcore demand RFOs busy",
841        "CounterMask": "1",
842        "EventCode": "0x60",
843        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
844        "SampleAfterValue": "2000000",
845        "UMask": "0x4"
846    },
847    {
848        "BriefDescription": "Offcore requests blocked due to Super Queue full",
849        "EventCode": "0xB2",
850        "EventName": "OFFCORE_REQUESTS_SQ_FULL",
851        "SampleAfterValue": "100000",
852        "UMask": "0x1"
853    },
854    {
855        "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
856        "EventCode": "0xB7",
857        "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
858        "MSRIndex": "0x1A6",
859        "MSRValue": "0x7F11",
860        "SampleAfterValue": "100000",
861        "UMask": "0x1"
862    },
863    {
864        "BriefDescription": "All offcore data reads",
865        "EventCode": "0xB7",
866        "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
867        "MSRIndex": "0x1A6",
868        "MSRValue": "0xFF11",
869        "SampleAfterValue": "100000",
870        "UMask": "0x1"
871    },
872    {
873        "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
874        "EventCode": "0xB7",
875        "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
876        "MSRIndex": "0x1A6",
877        "MSRValue": "0x8011",
878        "SampleAfterValue": "100000",
879        "UMask": "0x1"
880    },
881    {
882        "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
883        "EventCode": "0xB7",
884        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
885        "MSRIndex": "0x1A6",
886        "MSRValue": "0x111",
887        "SampleAfterValue": "100000",
888        "UMask": "0x1"
889    },
890    {
891        "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
892        "EventCode": "0xB7",
893        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
894        "MSRIndex": "0x1A6",
895        "MSRValue": "0x211",
896        "SampleAfterValue": "100000",
897        "UMask": "0x1"
898    },
899    {
900        "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
901        "EventCode": "0xB7",
902        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
903        "MSRIndex": "0x1A6",
904        "MSRValue": "0x411",
905        "SampleAfterValue": "100000",
906        "UMask": "0x1"
907    },
908    {
909        "BriefDescription": "Offcore data reads satisfied by the LLC",
910        "EventCode": "0xB7",
911        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
912        "MSRIndex": "0x1A6",
913        "MSRValue": "0x711",
914        "SampleAfterValue": "100000",
915        "UMask": "0x1"
916    },
917    {
918        "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
919        "EventCode": "0xB7",
920        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
921        "MSRIndex": "0x1A6",
922        "MSRValue": "0x4711",
923        "SampleAfterValue": "100000",
924        "UMask": "0x1"
925    },
926    {
927        "BriefDescription": "Offcore data reads satisfied by a remote cache",
928        "EventCode": "0xB7",
929        "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
930        "MSRIndex": "0x1A6",
931        "MSRValue": "0x1811",
932        "SampleAfterValue": "100000",
933        "UMask": "0x1"
934    },
935    {
936        "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
937        "EventCode": "0xB7",
938        "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
939        "MSRIndex": "0x1A6",
940        "MSRValue": "0x3811",
941        "SampleAfterValue": "100000",
942        "UMask": "0x1"
943    },
944    {
945        "BriefDescription": "Offcore data reads that HIT in a remote cache",
946        "EventCode": "0xB7",
947        "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
948        "MSRIndex": "0x1A6",
949        "MSRValue": "0x1011",
950        "SampleAfterValue": "100000",
951        "UMask": "0x1"
952    },
953    {
954        "BriefDescription": "Offcore data reads that HITM in a remote cache",
955        "EventCode": "0xB7",
956        "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
957        "MSRIndex": "0x1A6",
958        "MSRValue": "0x811",
959        "SampleAfterValue": "100000",
960        "UMask": "0x1"
961    },
962    {
963        "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
964        "EventCode": "0xB7",
965        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
966        "MSRIndex": "0x1A6",
967        "MSRValue": "0x7F44",
968        "SampleAfterValue": "100000",
969        "UMask": "0x1"
970    },
971    {
972        "BriefDescription": "All offcore code reads",
973        "EventCode": "0xB7",
974        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
975        "MSRIndex": "0x1A6",
976        "MSRValue": "0xFF44",
977        "SampleAfterValue": "100000",
978        "UMask": "0x1"
979    },
980    {
981        "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
982        "EventCode": "0xB7",
983        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
984        "MSRIndex": "0x1A6",
985        "MSRValue": "0x8044",
986        "SampleAfterValue": "100000",
987        "UMask": "0x1"
988    },
989    {
990        "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
991        "EventCode": "0xB7",
992        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
993        "MSRIndex": "0x1A6",
994        "MSRValue": "0x144",
995        "SampleAfterValue": "100000",
996        "UMask": "0x1"
997    },
998    {
999        "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
1000        "EventCode": "0xB7",
1001        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1002        "MSRIndex": "0x1A6",
1003        "MSRValue": "0x244",
1004        "SampleAfterValue": "100000",
1005        "UMask": "0x1"
1006    },
1007    {
1008        "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
1009        "EventCode": "0xB7",
1010        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1011        "MSRIndex": "0x1A6",
1012        "MSRValue": "0x444",
1013        "SampleAfterValue": "100000",
1014        "UMask": "0x1"
1015    },
1016    {
1017        "BriefDescription": "Offcore code reads satisfied by the LLC",
1018        "EventCode": "0xB7",
1019        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1020        "MSRIndex": "0x1A6",
1021        "MSRValue": "0x744",
1022        "SampleAfterValue": "100000",
1023        "UMask": "0x1"
1024    },
1025    {
1026        "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
1027        "EventCode": "0xB7",
1028        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
1029        "MSRIndex": "0x1A6",
1030        "MSRValue": "0x4744",
1031        "SampleAfterValue": "100000",
1032        "UMask": "0x1"
1033    },
1034    {
1035        "BriefDescription": "Offcore code reads satisfied by a remote cache",
1036        "EventCode": "0xB7",
1037        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
1038        "MSRIndex": "0x1A6",
1039        "MSRValue": "0x1844",
1040        "SampleAfterValue": "100000",
1041        "UMask": "0x1"
1042    },
1043    {
1044        "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
1045        "EventCode": "0xB7",
1046        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
1047        "MSRIndex": "0x1A6",
1048        "MSRValue": "0x3844",
1049        "SampleAfterValue": "100000",
1050        "UMask": "0x1"
1051    },
1052    {
1053        "BriefDescription": "Offcore code reads that HIT in a remote cache",
1054        "EventCode": "0xB7",
1055        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
1056        "MSRIndex": "0x1A6",
1057        "MSRValue": "0x1044",
1058        "SampleAfterValue": "100000",
1059        "UMask": "0x1"
1060    },
1061    {
1062        "BriefDescription": "Offcore code reads that HITM in a remote cache",
1063        "EventCode": "0xB7",
1064        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1065        "MSRIndex": "0x1A6",
1066        "MSRValue": "0x844",
1067        "SampleAfterValue": "100000",
1068        "UMask": "0x1"
1069    },
1070    {
1071        "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
1072        "EventCode": "0xB7",
1073        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1074        "MSRIndex": "0x1A6",
1075        "MSRValue": "0x7FFF",
1076        "SampleAfterValue": "100000",
1077        "UMask": "0x1"
1078    },
1079    {
1080        "BriefDescription": "All offcore requests",
1081        "EventCode": "0xB7",
1082        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1083        "MSRIndex": "0x1A6",
1084        "MSRValue": "0xFFFF",
1085        "SampleAfterValue": "100000",
1086        "UMask": "0x1"
1087    },
1088    {
1089        "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
1090        "EventCode": "0xB7",
1091        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1092        "MSRIndex": "0x1A6",
1093        "MSRValue": "0x80FF",
1094        "SampleAfterValue": "100000",
1095        "UMask": "0x1"
1096    },
1097    {
1098        "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
1099        "EventCode": "0xB7",
1100        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1101        "MSRIndex": "0x1A6",
1102        "MSRValue": "0x1FF",
1103        "SampleAfterValue": "100000",
1104        "UMask": "0x1"
1105    },
1106    {
1107        "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
1108        "EventCode": "0xB7",
1109        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1110        "MSRIndex": "0x1A6",
1111        "MSRValue": "0x2FF",
1112        "SampleAfterValue": "100000",
1113        "UMask": "0x1"
1114    },
1115    {
1116        "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
1117        "EventCode": "0xB7",
1118        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1119        "MSRIndex": "0x1A6",
1120        "MSRValue": "0x4FF",
1121        "SampleAfterValue": "100000",
1122        "UMask": "0x1"
1123    },
1124    {
1125        "BriefDescription": "Offcore requests satisfied by the LLC",
1126        "EventCode": "0xB7",
1127        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1128        "MSRIndex": "0x1A6",
1129        "MSRValue": "0x7FF",
1130        "SampleAfterValue": "100000",
1131        "UMask": "0x1"
1132    },
1133    {
1134        "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
1135        "EventCode": "0xB7",
1136        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
1137        "MSRIndex": "0x1A6",
1138        "MSRValue": "0x47FF",
1139        "SampleAfterValue": "100000",
1140        "UMask": "0x1"
1141    },
1142    {
1143        "BriefDescription": "Offcore requests satisfied by a remote cache",
1144        "EventCode": "0xB7",
1145        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
1146        "MSRIndex": "0x1A6",
1147        "MSRValue": "0x18FF",
1148        "SampleAfterValue": "100000",
1149        "UMask": "0x1"
1150    },
1151    {
1152        "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
1153        "EventCode": "0xB7",
1154        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
1155        "MSRIndex": "0x1A6",
1156        "MSRValue": "0x38FF",
1157        "SampleAfterValue": "100000",
1158        "UMask": "0x1"
1159    },
1160    {
1161        "BriefDescription": "Offcore requests that HIT in a remote cache",
1162        "EventCode": "0xB7",
1163        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
1164        "MSRIndex": "0x1A6",
1165        "MSRValue": "0x10FF",
1166        "SampleAfterValue": "100000",
1167        "UMask": "0x1"
1168    },
1169    {
1170        "BriefDescription": "Offcore requests that HITM in a remote cache",
1171        "EventCode": "0xB7",
1172        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1173        "MSRIndex": "0x1A6",
1174        "MSRValue": "0x8FF",
1175        "SampleAfterValue": "100000",
1176        "UMask": "0x1"
1177    },
1178    {
1179        "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
1180        "EventCode": "0xB7",
1181        "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1182        "MSRIndex": "0x1A6",
1183        "MSRValue": "0x7F22",
1184        "SampleAfterValue": "100000",
1185        "UMask": "0x1"
1186    },
1187    {
1188        "BriefDescription": "All offcore RFO requests",
1189        "EventCode": "0xB7",
1190        "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1191        "MSRIndex": "0x1A6",
1192        "MSRValue": "0xFF22",
1193        "SampleAfterValue": "100000",
1194        "UMask": "0x1"
1195    },
1196    {
1197        "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
1198        "EventCode": "0xB7",
1199        "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1200        "MSRIndex": "0x1A6",
1201        "MSRValue": "0x8022",
1202        "SampleAfterValue": "100000",
1203        "UMask": "0x1"
1204    },
1205    {
1206        "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
1207        "EventCode": "0xB7",
1208        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1209        "MSRIndex": "0x1A6",
1210        "MSRValue": "0x122",
1211        "SampleAfterValue": "100000",
1212        "UMask": "0x1"
1213    },
1214    {
1215        "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
1216        "EventCode": "0xB7",
1217        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1218        "MSRIndex": "0x1A6",
1219        "MSRValue": "0x222",
1220        "SampleAfterValue": "100000",
1221        "UMask": "0x1"
1222    },
1223    {
1224        "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
1225        "EventCode": "0xB7",
1226        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1227        "MSRIndex": "0x1A6",
1228        "MSRValue": "0x422",
1229        "SampleAfterValue": "100000",
1230        "UMask": "0x1"
1231    },
1232    {
1233        "BriefDescription": "Offcore RFO requests satisfied by the LLC",
1234        "EventCode": "0xB7",
1235        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1236        "MSRIndex": "0x1A6",
1237        "MSRValue": "0x722",
1238        "SampleAfterValue": "100000",
1239        "UMask": "0x1"
1240    },
1241    {
1242        "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
1243        "EventCode": "0xB7",
1244        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
1245        "MSRIndex": "0x1A6",
1246        "MSRValue": "0x4722",
1247        "SampleAfterValue": "100000",
1248        "UMask": "0x1"
1249    },
1250    {
1251        "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
1252        "EventCode": "0xB7",
1253        "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
1254        "MSRIndex": "0x1A6",
1255        "MSRValue": "0x1822",
1256        "SampleAfterValue": "100000",
1257        "UMask": "0x1"
1258    },
1259    {
1260        "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
1261        "EventCode": "0xB7",
1262        "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
1263        "MSRIndex": "0x1A6",
1264        "MSRValue": "0x3822",
1265        "SampleAfterValue": "100000",
1266        "UMask": "0x1"
1267    },
1268    {
1269        "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
1270        "EventCode": "0xB7",
1271        "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
1272        "MSRIndex": "0x1A6",
1273        "MSRValue": "0x1022",
1274        "SampleAfterValue": "100000",
1275        "UMask": "0x1"
1276    },
1277    {
1278        "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
1279        "EventCode": "0xB7",
1280        "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1281        "MSRIndex": "0x1A6",
1282        "MSRValue": "0x822",
1283        "SampleAfterValue": "100000",
1284        "UMask": "0x1"
1285    },
1286    {
1287        "BriefDescription": "Offcore writebacks to any cache or DRAM.",
1288        "EventCode": "0xB7",
1289        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1290        "MSRIndex": "0x1A6",
1291        "MSRValue": "0x7F08",
1292        "SampleAfterValue": "100000",
1293        "UMask": "0x1"
1294    },
1295    {
1296        "BriefDescription": "All offcore writebacks",
1297        "EventCode": "0xB7",
1298        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1299        "MSRIndex": "0x1A6",
1300        "MSRValue": "0xFF08",
1301        "SampleAfterValue": "100000",
1302        "UMask": "0x1"
1303    },
1304    {
1305        "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
1306        "EventCode": "0xB7",
1307        "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1308        "MSRIndex": "0x1A6",
1309        "MSRValue": "0x8008",
1310        "SampleAfterValue": "100000",
1311        "UMask": "0x1"
1312    },
1313    {
1314        "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
1315        "EventCode": "0xB7",
1316        "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1317        "MSRIndex": "0x1A6",
1318        "MSRValue": "0x108",
1319        "SampleAfterValue": "100000",
1320        "UMask": "0x1"
1321    },
1322    {
1323        "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
1324        "EventCode": "0xB7",
1325        "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1326        "MSRIndex": "0x1A6",
1327        "MSRValue": "0x408",
1328        "SampleAfterValue": "100000",
1329        "UMask": "0x1"
1330    },
1331    {
1332        "BriefDescription": "Offcore writebacks to the LLC",
1333        "EventCode": "0xB7",
1334        "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1335        "MSRIndex": "0x1A6",
1336        "MSRValue": "0x708",
1337        "SampleAfterValue": "100000",
1338        "UMask": "0x1"
1339    },
1340    {
1341        "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
1342        "EventCode": "0xB7",
1343        "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
1344        "MSRIndex": "0x1A6",
1345        "MSRValue": "0x4708",
1346        "SampleAfterValue": "100000",
1347        "UMask": "0x1"
1348    },
1349    {
1350        "BriefDescription": "Offcore writebacks to a remote cache",
1351        "EventCode": "0xB7",
1352        "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
1353        "MSRIndex": "0x1A6",
1354        "MSRValue": "0x1808",
1355        "SampleAfterValue": "100000",
1356        "UMask": "0x1"
1357    },
1358    {
1359        "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
1360        "EventCode": "0xB7",
1361        "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
1362        "MSRIndex": "0x1A6",
1363        "MSRValue": "0x3808",
1364        "SampleAfterValue": "100000",
1365        "UMask": "0x1"
1366    },
1367    {
1368        "BriefDescription": "Offcore writebacks that HIT in a remote cache",
1369        "EventCode": "0xB7",
1370        "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
1371        "MSRIndex": "0x1A6",
1372        "MSRValue": "0x1008",
1373        "SampleAfterValue": "100000",
1374        "UMask": "0x1"
1375    },
1376    {
1377        "BriefDescription": "Offcore writebacks that HITM in a remote cache",
1378        "EventCode": "0xB7",
1379        "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1380        "MSRIndex": "0x1A6",
1381        "MSRValue": "0x808",
1382        "SampleAfterValue": "100000",
1383        "UMask": "0x1"
1384    },
1385    {
1386        "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
1387        "EventCode": "0xB7",
1388        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1389        "MSRIndex": "0x1A6",
1390        "MSRValue": "0x7F77",
1391        "SampleAfterValue": "100000",
1392        "UMask": "0x1"
1393    },
1394    {
1395        "BriefDescription": "All offcore code or data read requests",
1396        "EventCode": "0xB7",
1397        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1398        "MSRIndex": "0x1A6",
1399        "MSRValue": "0xFF77",
1400        "SampleAfterValue": "100000",
1401        "UMask": "0x1"
1402    },
1403    {
1404        "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
1405        "EventCode": "0xB7",
1406        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1407        "MSRIndex": "0x1A6",
1408        "MSRValue": "0x8077",
1409        "SampleAfterValue": "100000",
1410        "UMask": "0x1"
1411    },
1412    {
1413        "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
1414        "EventCode": "0xB7",
1415        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1416        "MSRIndex": "0x1A6",
1417        "MSRValue": "0x177",
1418        "SampleAfterValue": "100000",
1419        "UMask": "0x1"
1420    },
1421    {
1422        "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
1423        "EventCode": "0xB7",
1424        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1425        "MSRIndex": "0x1A6",
1426        "MSRValue": "0x277",
1427        "SampleAfterValue": "100000",
1428        "UMask": "0x1"
1429    },
1430    {
1431        "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
1432        "EventCode": "0xB7",
1433        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1434        "MSRIndex": "0x1A6",
1435        "MSRValue": "0x477",
1436        "SampleAfterValue": "100000",
1437        "UMask": "0x1"
1438    },
1439    {
1440        "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
1441        "EventCode": "0xB7",
1442        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1443        "MSRIndex": "0x1A6",
1444        "MSRValue": "0x777",
1445        "SampleAfterValue": "100000",
1446        "UMask": "0x1"
1447    },
1448    {
1449        "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
1450        "EventCode": "0xB7",
1451        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
1452        "MSRIndex": "0x1A6",
1453        "MSRValue": "0x4777",
1454        "SampleAfterValue": "100000",
1455        "UMask": "0x1"
1456    },
1457    {
1458        "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
1459        "EventCode": "0xB7",
1460        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
1461        "MSRIndex": "0x1A6",
1462        "MSRValue": "0x1877",
1463        "SampleAfterValue": "100000",
1464        "UMask": "0x1"
1465    },
1466    {
1467        "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
1468        "EventCode": "0xB7",
1469        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
1470        "MSRIndex": "0x1A6",
1471        "MSRValue": "0x3877",
1472        "SampleAfterValue": "100000",
1473        "UMask": "0x1"
1474    },
1475    {
1476        "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
1477        "EventCode": "0xB7",
1478        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
1479        "MSRIndex": "0x1A6",
1480        "MSRValue": "0x1077",
1481        "SampleAfterValue": "100000",
1482        "UMask": "0x1"
1483    },
1484    {
1485        "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
1486        "EventCode": "0xB7",
1487        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1488        "MSRIndex": "0x1A6",
1489        "MSRValue": "0x877",
1490        "SampleAfterValue": "100000",
1491        "UMask": "0x1"
1492    },
1493    {
1494        "BriefDescription": "Offcore request = all data, response = any cache_dram",
1495        "EventCode": "0xB7",
1496        "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1497        "MSRIndex": "0x1A6",
1498        "MSRValue": "0x7F33",
1499        "SampleAfterValue": "100000",
1500        "UMask": "0x1"
1501    },
1502    {
1503        "BriefDescription": "Offcore request = all data, response = any location",
1504        "EventCode": "0xB7",
1505        "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1506        "MSRIndex": "0x1A6",
1507        "MSRValue": "0xFF33",
1508        "SampleAfterValue": "100000",
1509        "UMask": "0x1"
1510    },
1511    {
1512        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
1513        "EventCode": "0xB7",
1514        "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1515        "MSRIndex": "0x1A6",
1516        "MSRValue": "0x8033",
1517        "SampleAfterValue": "100000",
1518        "UMask": "0x1"
1519    },
1520    {
1521        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
1522        "EventCode": "0xB7",
1523        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1524        "MSRIndex": "0x1A6",
1525        "MSRValue": "0x133",
1526        "SampleAfterValue": "100000",
1527        "UMask": "0x1"
1528    },
1529    {
1530        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
1531        "EventCode": "0xB7",
1532        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1533        "MSRIndex": "0x1A6",
1534        "MSRValue": "0x233",
1535        "SampleAfterValue": "100000",
1536        "UMask": "0x1"
1537    },
1538    {
1539        "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC  and HITM in a sibling core",
1540        "EventCode": "0xB7",
1541        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1542        "MSRIndex": "0x1A6",
1543        "MSRValue": "0x433",
1544        "SampleAfterValue": "100000",
1545        "UMask": "0x1"
1546    },
1547    {
1548        "BriefDescription": "Offcore request = all data, response = local cache",
1549        "EventCode": "0xB7",
1550        "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1551        "MSRIndex": "0x1A6",
1552        "MSRValue": "0x733",
1553        "SampleAfterValue": "100000",
1554        "UMask": "0x1"
1555    },
1556    {
1557        "BriefDescription": "Offcore request = all data, response = local cache or dram",
1558        "EventCode": "0xB7",
1559        "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
1560        "MSRIndex": "0x1A6",
1561        "MSRValue": "0x4733",
1562        "SampleAfterValue": "100000",
1563        "UMask": "0x1"
1564    },
1565    {
1566        "BriefDescription": "Offcore request = all data, response = remote cache",
1567        "EventCode": "0xB7",
1568        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
1569        "MSRIndex": "0x1A6",
1570        "MSRValue": "0x1833",
1571        "SampleAfterValue": "100000",
1572        "UMask": "0x1"
1573    },
1574    {
1575        "BriefDescription": "Offcore request = all data, response = remote cache or dram",
1576        "EventCode": "0xB7",
1577        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
1578        "MSRIndex": "0x1A6",
1579        "MSRValue": "0x3833",
1580        "SampleAfterValue": "100000",
1581        "UMask": "0x1"
1582    },
1583    {
1584        "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
1585        "EventCode": "0xB7",
1586        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
1587        "MSRIndex": "0x1A6",
1588        "MSRValue": "0x1033",
1589        "SampleAfterValue": "100000",
1590        "UMask": "0x1"
1591    },
1592    {
1593        "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
1594        "EventCode": "0xB7",
1595        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1596        "MSRIndex": "0x1A6",
1597        "MSRValue": "0x833",
1598        "SampleAfterValue": "100000",
1599        "UMask": "0x1"
1600    },
1601    {
1602        "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
1603        "EventCode": "0xB7",
1604        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1605        "MSRIndex": "0x1A6",
1606        "MSRValue": "0x7F03",
1607        "SampleAfterValue": "100000",
1608        "UMask": "0x1"
1609    },
1610    {
1611        "BriefDescription": "All offcore demand data requests",
1612        "EventCode": "0xB7",
1613        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1614        "MSRIndex": "0x1A6",
1615        "MSRValue": "0xFF03",
1616        "SampleAfterValue": "100000",
1617        "UMask": "0x1"
1618    },
1619    {
1620        "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
1621        "EventCode": "0xB7",
1622        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1623        "MSRIndex": "0x1A6",
1624        "MSRValue": "0x8003",
1625        "SampleAfterValue": "100000",
1626        "UMask": "0x1"
1627    },
1628    {
1629        "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
1630        "EventCode": "0xB7",
1631        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1632        "MSRIndex": "0x1A6",
1633        "MSRValue": "0x103",
1634        "SampleAfterValue": "100000",
1635        "UMask": "0x1"
1636    },
1637    {
1638        "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
1639        "EventCode": "0xB7",
1640        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1641        "MSRIndex": "0x1A6",
1642        "MSRValue": "0x203",
1643        "SampleAfterValue": "100000",
1644        "UMask": "0x1"
1645    },
1646    {
1647        "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
1648        "EventCode": "0xB7",
1649        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1650        "MSRIndex": "0x1A6",
1651        "MSRValue": "0x403",
1652        "SampleAfterValue": "100000",
1653        "UMask": "0x1"
1654    },
1655    {
1656        "BriefDescription": "Offcore demand data requests satisfied by the LLC",
1657        "EventCode": "0xB7",
1658        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1659        "MSRIndex": "0x1A6",
1660        "MSRValue": "0x703",
1661        "SampleAfterValue": "100000",
1662        "UMask": "0x1"
1663    },
1664    {
1665        "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
1666        "EventCode": "0xB7",
1667        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
1668        "MSRIndex": "0x1A6",
1669        "MSRValue": "0x4703",
1670        "SampleAfterValue": "100000",
1671        "UMask": "0x1"
1672    },
1673    {
1674        "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
1675        "EventCode": "0xB7",
1676        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
1677        "MSRIndex": "0x1A6",
1678        "MSRValue": "0x1803",
1679        "SampleAfterValue": "100000",
1680        "UMask": "0x1"
1681    },
1682    {
1683        "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
1684        "EventCode": "0xB7",
1685        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
1686        "MSRIndex": "0x1A6",
1687        "MSRValue": "0x3803",
1688        "SampleAfterValue": "100000",
1689        "UMask": "0x1"
1690    },
1691    {
1692        "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
1693        "EventCode": "0xB7",
1694        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
1695        "MSRIndex": "0x1A6",
1696        "MSRValue": "0x1003",
1697        "SampleAfterValue": "100000",
1698        "UMask": "0x1"
1699    },
1700    {
1701        "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
1702        "EventCode": "0xB7",
1703        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
1704        "MSRIndex": "0x1A6",
1705        "MSRValue": "0x803",
1706        "SampleAfterValue": "100000",
1707        "UMask": "0x1"
1708    },
1709    {
1710        "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
1711        "EventCode": "0xB7",
1712        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
1713        "MSRIndex": "0x1A6",
1714        "MSRValue": "0x7F01",
1715        "SampleAfterValue": "100000",
1716        "UMask": "0x1"
1717    },
1718    {
1719        "BriefDescription": "All offcore demand data reads",
1720        "EventCode": "0xB7",
1721        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
1722        "MSRIndex": "0x1A6",
1723        "MSRValue": "0xFF01",
1724        "SampleAfterValue": "100000",
1725        "UMask": "0x1"
1726    },
1727    {
1728        "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
1729        "EventCode": "0xB7",
1730        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
1731        "MSRIndex": "0x1A6",
1732        "MSRValue": "0x8001",
1733        "SampleAfterValue": "100000",
1734        "UMask": "0x1"
1735    },
1736    {
1737        "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
1738        "EventCode": "0xB7",
1739        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
1740        "MSRIndex": "0x1A6",
1741        "MSRValue": "0x101",
1742        "SampleAfterValue": "100000",
1743        "UMask": "0x1"
1744    },
1745    {
1746        "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
1747        "EventCode": "0xB7",
1748        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
1749        "MSRIndex": "0x1A6",
1750        "MSRValue": "0x201",
1751        "SampleAfterValue": "100000",
1752        "UMask": "0x1"
1753    },
1754    {
1755        "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
1756        "EventCode": "0xB7",
1757        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
1758        "MSRIndex": "0x1A6",
1759        "MSRValue": "0x401",
1760        "SampleAfterValue": "100000",
1761        "UMask": "0x1"
1762    },
1763    {
1764        "BriefDescription": "Offcore demand data reads satisfied by the LLC",
1765        "EventCode": "0xB7",
1766        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
1767        "MSRIndex": "0x1A6",
1768        "MSRValue": "0x701",
1769        "SampleAfterValue": "100000",
1770        "UMask": "0x1"
1771    },
1772    {
1773        "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
1774        "EventCode": "0xB7",
1775        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
1776        "MSRIndex": "0x1A6",
1777        "MSRValue": "0x4701",
1778        "SampleAfterValue": "100000",
1779        "UMask": "0x1"
1780    },
1781    {
1782        "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
1783        "EventCode": "0xB7",
1784        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
1785        "MSRIndex": "0x1A6",
1786        "MSRValue": "0x1801",
1787        "SampleAfterValue": "100000",
1788        "UMask": "0x1"
1789    },
1790    {
1791        "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
1792        "EventCode": "0xB7",
1793        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
1794        "MSRIndex": "0x1A6",
1795        "MSRValue": "0x3801",
1796        "SampleAfterValue": "100000",
1797        "UMask": "0x1"
1798    },
1799    {
1800        "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
1801        "EventCode": "0xB7",
1802        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
1803        "MSRIndex": "0x1A6",
1804        "MSRValue": "0x1001",
1805        "SampleAfterValue": "100000",
1806        "UMask": "0x1"
1807    },
1808    {
1809        "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
1810        "EventCode": "0xB7",
1811        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
1812        "MSRIndex": "0x1A6",
1813        "MSRValue": "0x801",
1814        "SampleAfterValue": "100000",
1815        "UMask": "0x1"
1816    },
1817    {
1818        "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
1819        "EventCode": "0xB7",
1820        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
1821        "MSRIndex": "0x1A6",
1822        "MSRValue": "0x7F04",
1823        "SampleAfterValue": "100000",
1824        "UMask": "0x1"
1825    },
1826    {
1827        "BriefDescription": "All offcore demand code reads",
1828        "EventCode": "0xB7",
1829        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
1830        "MSRIndex": "0x1A6",
1831        "MSRValue": "0xFF04",
1832        "SampleAfterValue": "100000",
1833        "UMask": "0x1"
1834    },
1835    {
1836        "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
1837        "EventCode": "0xB7",
1838        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
1839        "MSRIndex": "0x1A6",
1840        "MSRValue": "0x8004",
1841        "SampleAfterValue": "100000",
1842        "UMask": "0x1"
1843    },
1844    {
1845        "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
1846        "EventCode": "0xB7",
1847        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
1848        "MSRIndex": "0x1A6",
1849        "MSRValue": "0x104",
1850        "SampleAfterValue": "100000",
1851        "UMask": "0x1"
1852    },
1853    {
1854        "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
1855        "EventCode": "0xB7",
1856        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1857        "MSRIndex": "0x1A6",
1858        "MSRValue": "0x204",
1859        "SampleAfterValue": "100000",
1860        "UMask": "0x1"
1861    },
1862    {
1863        "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
1864        "EventCode": "0xB7",
1865        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1866        "MSRIndex": "0x1A6",
1867        "MSRValue": "0x404",
1868        "SampleAfterValue": "100000",
1869        "UMask": "0x1"
1870    },
1871    {
1872        "BriefDescription": "Offcore demand code reads satisfied by the LLC",
1873        "EventCode": "0xB7",
1874        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
1875        "MSRIndex": "0x1A6",
1876        "MSRValue": "0x704",
1877        "SampleAfterValue": "100000",
1878        "UMask": "0x1"
1879    },
1880    {
1881        "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
1882        "EventCode": "0xB7",
1883        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
1884        "MSRIndex": "0x1A6",
1885        "MSRValue": "0x4704",
1886        "SampleAfterValue": "100000",
1887        "UMask": "0x1"
1888    },
1889    {
1890        "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
1891        "EventCode": "0xB7",
1892        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
1893        "MSRIndex": "0x1A6",
1894        "MSRValue": "0x1804",
1895        "SampleAfterValue": "100000",
1896        "UMask": "0x1"
1897    },
1898    {
1899        "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
1900        "EventCode": "0xB7",
1901        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
1902        "MSRIndex": "0x1A6",
1903        "MSRValue": "0x3804",
1904        "SampleAfterValue": "100000",
1905        "UMask": "0x1"
1906    },
1907    {
1908        "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
1909        "EventCode": "0xB7",
1910        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
1911        "MSRIndex": "0x1A6",
1912        "MSRValue": "0x1004",
1913        "SampleAfterValue": "100000",
1914        "UMask": "0x1"
1915    },
1916    {
1917        "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
1918        "EventCode": "0xB7",
1919        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
1920        "MSRIndex": "0x1A6",
1921        "MSRValue": "0x804",
1922        "SampleAfterValue": "100000",
1923        "UMask": "0x1"
1924    },
1925    {
1926        "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
1927        "EventCode": "0xB7",
1928        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
1929        "MSRIndex": "0x1A6",
1930        "MSRValue": "0x7F02",
1931        "SampleAfterValue": "100000",
1932        "UMask": "0x1"
1933    },
1934    {
1935        "BriefDescription": "All offcore demand RFO requests",
1936        "EventCode": "0xB7",
1937        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
1938        "MSRIndex": "0x1A6",
1939        "MSRValue": "0xFF02",
1940        "SampleAfterValue": "100000",
1941        "UMask": "0x1"
1942    },
1943    {
1944        "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
1945        "EventCode": "0xB7",
1946        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
1947        "MSRIndex": "0x1A6",
1948        "MSRValue": "0x8002",
1949        "SampleAfterValue": "100000",
1950        "UMask": "0x1"
1951    },
1952    {
1953        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
1954        "EventCode": "0xB7",
1955        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
1956        "MSRIndex": "0x1A6",
1957        "MSRValue": "0x102",
1958        "SampleAfterValue": "100000",
1959        "UMask": "0x1"
1960    },
1961    {
1962        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
1963        "EventCode": "0xB7",
1964        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
1965        "MSRIndex": "0x1A6",
1966        "MSRValue": "0x202",
1967        "SampleAfterValue": "100000",
1968        "UMask": "0x1"
1969    },
1970    {
1971        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
1972        "EventCode": "0xB7",
1973        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
1974        "MSRIndex": "0x1A6",
1975        "MSRValue": "0x402",
1976        "SampleAfterValue": "100000",
1977        "UMask": "0x1"
1978    },
1979    {
1980        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
1981        "EventCode": "0xB7",
1982        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
1983        "MSRIndex": "0x1A6",
1984        "MSRValue": "0x702",
1985        "SampleAfterValue": "100000",
1986        "UMask": "0x1"
1987    },
1988    {
1989        "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
1990        "EventCode": "0xB7",
1991        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
1992        "MSRIndex": "0x1A6",
1993        "MSRValue": "0x4702",
1994        "SampleAfterValue": "100000",
1995        "UMask": "0x1"
1996    },
1997    {
1998        "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
1999        "EventCode": "0xB7",
2000        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
2001        "MSRIndex": "0x1A6",
2002        "MSRValue": "0x1802",
2003        "SampleAfterValue": "100000",
2004        "UMask": "0x1"
2005    },
2006    {
2007        "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
2008        "EventCode": "0xB7",
2009        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
2010        "MSRIndex": "0x1A6",
2011        "MSRValue": "0x3802",
2012        "SampleAfterValue": "100000",
2013        "UMask": "0x1"
2014    },
2015    {
2016        "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
2017        "EventCode": "0xB7",
2018        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
2019        "MSRIndex": "0x1A6",
2020        "MSRValue": "0x1002",
2021        "SampleAfterValue": "100000",
2022        "UMask": "0x1"
2023    },
2024    {
2025        "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
2026        "EventCode": "0xB7",
2027        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2028        "MSRIndex": "0x1A6",
2029        "MSRValue": "0x802",
2030        "SampleAfterValue": "100000",
2031        "UMask": "0x1"
2032    },
2033    {
2034        "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
2035        "EventCode": "0xB7",
2036        "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2037        "MSRIndex": "0x1A6",
2038        "MSRValue": "0x7F80",
2039        "SampleAfterValue": "100000",
2040        "UMask": "0x1"
2041    },
2042    {
2043        "BriefDescription": "All offcore other requests",
2044        "EventCode": "0xB7",
2045        "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2046        "MSRIndex": "0x1A6",
2047        "MSRValue": "0xFF80",
2048        "SampleAfterValue": "100000",
2049        "UMask": "0x1"
2050    },
2051    {
2052        "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
2053        "EventCode": "0xB7",
2054        "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2055        "MSRIndex": "0x1A6",
2056        "MSRValue": "0x8080",
2057        "SampleAfterValue": "100000",
2058        "UMask": "0x1"
2059    },
2060    {
2061        "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
2062        "EventCode": "0xB7",
2063        "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2064        "MSRIndex": "0x1A6",
2065        "MSRValue": "0x180",
2066        "SampleAfterValue": "100000",
2067        "UMask": "0x1"
2068    },
2069    {
2070        "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
2071        "EventCode": "0xB7",
2072        "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2073        "MSRIndex": "0x1A6",
2074        "MSRValue": "0x280",
2075        "SampleAfterValue": "100000",
2076        "UMask": "0x1"
2077    },
2078    {
2079        "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
2080        "EventCode": "0xB7",
2081        "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2082        "MSRIndex": "0x1A6",
2083        "MSRValue": "0x480",
2084        "SampleAfterValue": "100000",
2085        "UMask": "0x1"
2086    },
2087    {
2088        "BriefDescription": "Offcore other requests satisfied by the LLC",
2089        "EventCode": "0xB7",
2090        "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2091        "MSRIndex": "0x1A6",
2092        "MSRValue": "0x780",
2093        "SampleAfterValue": "100000",
2094        "UMask": "0x1"
2095    },
2096    {
2097        "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
2098        "EventCode": "0xB7",
2099        "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
2100        "MSRIndex": "0x1A6",
2101        "MSRValue": "0x4780",
2102        "SampleAfterValue": "100000",
2103        "UMask": "0x1"
2104    },
2105    {
2106        "BriefDescription": "Offcore other requests satisfied by a remote cache",
2107        "EventCode": "0xB7",
2108        "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
2109        "MSRIndex": "0x1A6",
2110        "MSRValue": "0x1880",
2111        "SampleAfterValue": "100000",
2112        "UMask": "0x1"
2113    },
2114    {
2115        "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
2116        "EventCode": "0xB7",
2117        "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
2118        "MSRIndex": "0x1A6",
2119        "MSRValue": "0x3880",
2120        "SampleAfterValue": "100000",
2121        "UMask": "0x1"
2122    },
2123    {
2124        "BriefDescription": "Offcore other requests that HIT in a remote cache",
2125        "EventCode": "0xB7",
2126        "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
2127        "MSRIndex": "0x1A6",
2128        "MSRValue": "0x1080",
2129        "SampleAfterValue": "100000",
2130        "UMask": "0x1"
2131    },
2132    {
2133        "BriefDescription": "Offcore other requests that HITM in a remote cache",
2134        "EventCode": "0xB7",
2135        "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2136        "MSRIndex": "0x1A6",
2137        "MSRValue": "0x880",
2138        "SampleAfterValue": "100000",
2139        "UMask": "0x1"
2140    },
2141    {
2142        "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
2143        "EventCode": "0xB7",
2144        "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2145        "MSRIndex": "0x1A6",
2146        "MSRValue": "0x7F30",
2147        "SampleAfterValue": "100000",
2148        "UMask": "0x1"
2149    },
2150    {
2151        "BriefDescription": "All offcore prefetch data requests",
2152        "EventCode": "0xB7",
2153        "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2154        "MSRIndex": "0x1A6",
2155        "MSRValue": "0xFF30",
2156        "SampleAfterValue": "100000",
2157        "UMask": "0x1"
2158    },
2159    {
2160        "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
2161        "EventCode": "0xB7",
2162        "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2163        "MSRIndex": "0x1A6",
2164        "MSRValue": "0x8030",
2165        "SampleAfterValue": "100000",
2166        "UMask": "0x1"
2167    },
2168    {
2169        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
2170        "EventCode": "0xB7",
2171        "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2172        "MSRIndex": "0x1A6",
2173        "MSRValue": "0x130",
2174        "SampleAfterValue": "100000",
2175        "UMask": "0x1"
2176    },
2177    {
2178        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
2179        "EventCode": "0xB7",
2180        "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2181        "MSRIndex": "0x1A6",
2182        "MSRValue": "0x230",
2183        "SampleAfterValue": "100000",
2184        "UMask": "0x1"
2185    },
2186    {
2187        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
2188        "EventCode": "0xB7",
2189        "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2190        "MSRIndex": "0x1A6",
2191        "MSRValue": "0x430",
2192        "SampleAfterValue": "100000",
2193        "UMask": "0x1"
2194    },
2195    {
2196        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
2197        "EventCode": "0xB7",
2198        "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2199        "MSRIndex": "0x1A6",
2200        "MSRValue": "0x730",
2201        "SampleAfterValue": "100000",
2202        "UMask": "0x1"
2203    },
2204    {
2205        "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
2206        "EventCode": "0xB7",
2207        "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
2208        "MSRIndex": "0x1A6",
2209        "MSRValue": "0x4730",
2210        "SampleAfterValue": "100000",
2211        "UMask": "0x1"
2212    },
2213    {
2214        "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
2215        "EventCode": "0xB7",
2216        "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
2217        "MSRIndex": "0x1A6",
2218        "MSRValue": "0x1830",
2219        "SampleAfterValue": "100000",
2220        "UMask": "0x1"
2221    },
2222    {
2223        "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
2224        "EventCode": "0xB7",
2225        "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
2226        "MSRIndex": "0x1A6",
2227        "MSRValue": "0x3830",
2228        "SampleAfterValue": "100000",
2229        "UMask": "0x1"
2230    },
2231    {
2232        "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
2233        "EventCode": "0xB7",
2234        "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
2235        "MSRIndex": "0x1A6",
2236        "MSRValue": "0x1030",
2237        "SampleAfterValue": "100000",
2238        "UMask": "0x1"
2239    },
2240    {
2241        "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
2242        "EventCode": "0xB7",
2243        "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2244        "MSRIndex": "0x1A6",
2245        "MSRValue": "0x830",
2246        "SampleAfterValue": "100000",
2247        "UMask": "0x1"
2248    },
2249    {
2250        "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
2251        "EventCode": "0xB7",
2252        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2253        "MSRIndex": "0x1A6",
2254        "MSRValue": "0x7F10",
2255        "SampleAfterValue": "100000",
2256        "UMask": "0x1"
2257    },
2258    {
2259        "BriefDescription": "All offcore prefetch data reads",
2260        "EventCode": "0xB7",
2261        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2262        "MSRIndex": "0x1A6",
2263        "MSRValue": "0xFF10",
2264        "SampleAfterValue": "100000",
2265        "UMask": "0x1"
2266    },
2267    {
2268        "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
2269        "EventCode": "0xB7",
2270        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2271        "MSRIndex": "0x1A6",
2272        "MSRValue": "0x8010",
2273        "SampleAfterValue": "100000",
2274        "UMask": "0x1"
2275    },
2276    {
2277        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
2278        "EventCode": "0xB7",
2279        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2280        "MSRIndex": "0x1A6",
2281        "MSRValue": "0x110",
2282        "SampleAfterValue": "100000",
2283        "UMask": "0x1"
2284    },
2285    {
2286        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
2287        "EventCode": "0xB7",
2288        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2289        "MSRIndex": "0x1A6",
2290        "MSRValue": "0x210",
2291        "SampleAfterValue": "100000",
2292        "UMask": "0x1"
2293    },
2294    {
2295        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
2296        "EventCode": "0xB7",
2297        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2298        "MSRIndex": "0x1A6",
2299        "MSRValue": "0x410",
2300        "SampleAfterValue": "100000",
2301        "UMask": "0x1"
2302    },
2303    {
2304        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
2305        "EventCode": "0xB7",
2306        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2307        "MSRIndex": "0x1A6",
2308        "MSRValue": "0x710",
2309        "SampleAfterValue": "100000",
2310        "UMask": "0x1"
2311    },
2312    {
2313        "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
2314        "EventCode": "0xB7",
2315        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
2316        "MSRIndex": "0x1A6",
2317        "MSRValue": "0x4710",
2318        "SampleAfterValue": "100000",
2319        "UMask": "0x1"
2320    },
2321    {
2322        "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
2323        "EventCode": "0xB7",
2324        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
2325        "MSRIndex": "0x1A6",
2326        "MSRValue": "0x1810",
2327        "SampleAfterValue": "100000",
2328        "UMask": "0x1"
2329    },
2330    {
2331        "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
2332        "EventCode": "0xB7",
2333        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
2334        "MSRIndex": "0x1A6",
2335        "MSRValue": "0x3810",
2336        "SampleAfterValue": "100000",
2337        "UMask": "0x1"
2338    },
2339    {
2340        "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
2341        "EventCode": "0xB7",
2342        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
2343        "MSRIndex": "0x1A6",
2344        "MSRValue": "0x1010",
2345        "SampleAfterValue": "100000",
2346        "UMask": "0x1"
2347    },
2348    {
2349        "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
2350        "EventCode": "0xB7",
2351        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2352        "MSRIndex": "0x1A6",
2353        "MSRValue": "0x810",
2354        "SampleAfterValue": "100000",
2355        "UMask": "0x1"
2356    },
2357    {
2358        "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
2359        "EventCode": "0xB7",
2360        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2361        "MSRIndex": "0x1A6",
2362        "MSRValue": "0x7F40",
2363        "SampleAfterValue": "100000",
2364        "UMask": "0x1"
2365    },
2366    {
2367        "BriefDescription": "All offcore prefetch code reads",
2368        "EventCode": "0xB7",
2369        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2370        "MSRIndex": "0x1A6",
2371        "MSRValue": "0xFF40",
2372        "SampleAfterValue": "100000",
2373        "UMask": "0x1"
2374    },
2375    {
2376        "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
2377        "EventCode": "0xB7",
2378        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2379        "MSRIndex": "0x1A6",
2380        "MSRValue": "0x8040",
2381        "SampleAfterValue": "100000",
2382        "UMask": "0x1"
2383    },
2384    {
2385        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
2386        "EventCode": "0xB7",
2387        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2388        "MSRIndex": "0x1A6",
2389        "MSRValue": "0x140",
2390        "SampleAfterValue": "100000",
2391        "UMask": "0x1"
2392    },
2393    {
2394        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
2395        "EventCode": "0xB7",
2396        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2397        "MSRIndex": "0x1A6",
2398        "MSRValue": "0x240",
2399        "SampleAfterValue": "100000",
2400        "UMask": "0x1"
2401    },
2402    {
2403        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
2404        "EventCode": "0xB7",
2405        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2406        "MSRIndex": "0x1A6",
2407        "MSRValue": "0x440",
2408        "SampleAfterValue": "100000",
2409        "UMask": "0x1"
2410    },
2411    {
2412        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
2413        "EventCode": "0xB7",
2414        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2415        "MSRIndex": "0x1A6",
2416        "MSRValue": "0x740",
2417        "SampleAfterValue": "100000",
2418        "UMask": "0x1"
2419    },
2420    {
2421        "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
2422        "EventCode": "0xB7",
2423        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
2424        "MSRIndex": "0x1A6",
2425        "MSRValue": "0x4740",
2426        "SampleAfterValue": "100000",
2427        "UMask": "0x1"
2428    },
2429    {
2430        "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
2431        "EventCode": "0xB7",
2432        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
2433        "MSRIndex": "0x1A6",
2434        "MSRValue": "0x1840",
2435        "SampleAfterValue": "100000",
2436        "UMask": "0x1"
2437    },
2438    {
2439        "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
2440        "EventCode": "0xB7",
2441        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
2442        "MSRIndex": "0x1A6",
2443        "MSRValue": "0x3840",
2444        "SampleAfterValue": "100000",
2445        "UMask": "0x1"
2446    },
2447    {
2448        "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
2449        "EventCode": "0xB7",
2450        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
2451        "MSRIndex": "0x1A6",
2452        "MSRValue": "0x1040",
2453        "SampleAfterValue": "100000",
2454        "UMask": "0x1"
2455    },
2456    {
2457        "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
2458        "EventCode": "0xB7",
2459        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2460        "MSRIndex": "0x1A6",
2461        "MSRValue": "0x840",
2462        "SampleAfterValue": "100000",
2463        "UMask": "0x1"
2464    },
2465    {
2466        "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
2467        "EventCode": "0xB7",
2468        "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2469        "MSRIndex": "0x1A6",
2470        "MSRValue": "0x7F20",
2471        "SampleAfterValue": "100000",
2472        "UMask": "0x1"
2473    },
2474    {
2475        "BriefDescription": "All offcore prefetch RFO requests",
2476        "EventCode": "0xB7",
2477        "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2478        "MSRIndex": "0x1A6",
2479        "MSRValue": "0xFF20",
2480        "SampleAfterValue": "100000",
2481        "UMask": "0x1"
2482    },
2483    {
2484        "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
2485        "EventCode": "0xB7",
2486        "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2487        "MSRIndex": "0x1A6",
2488        "MSRValue": "0x8020",
2489        "SampleAfterValue": "100000",
2490        "UMask": "0x1"
2491    },
2492    {
2493        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
2494        "EventCode": "0xB7",
2495        "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
2496        "MSRIndex": "0x1A6",
2497        "MSRValue": "0x120",
2498        "SampleAfterValue": "100000",
2499        "UMask": "0x1"
2500    },
2501    {
2502        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
2503        "EventCode": "0xB7",
2504        "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
2505        "MSRIndex": "0x1A6",
2506        "MSRValue": "0x220",
2507        "SampleAfterValue": "100000",
2508        "UMask": "0x1"
2509    },
2510    {
2511        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
2512        "EventCode": "0xB7",
2513        "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
2514        "MSRIndex": "0x1A6",
2515        "MSRValue": "0x420",
2516        "SampleAfterValue": "100000",
2517        "UMask": "0x1"
2518    },
2519    {
2520        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
2521        "EventCode": "0xB7",
2522        "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
2523        "MSRIndex": "0x1A6",
2524        "MSRValue": "0x720",
2525        "SampleAfterValue": "100000",
2526        "UMask": "0x1"
2527    },
2528    {
2529        "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
2530        "EventCode": "0xB7",
2531        "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
2532        "MSRIndex": "0x1A6",
2533        "MSRValue": "0x4720",
2534        "SampleAfterValue": "100000",
2535        "UMask": "0x1"
2536    },
2537    {
2538        "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
2539        "EventCode": "0xB7",
2540        "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
2541        "MSRIndex": "0x1A6",
2542        "MSRValue": "0x1820",
2543        "SampleAfterValue": "100000",
2544        "UMask": "0x1"
2545    },
2546    {
2547        "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
2548        "EventCode": "0xB7",
2549        "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
2550        "MSRIndex": "0x1A6",
2551        "MSRValue": "0x3820",
2552        "SampleAfterValue": "100000",
2553        "UMask": "0x1"
2554    },
2555    {
2556        "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
2557        "EventCode": "0xB7",
2558        "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
2559        "MSRIndex": "0x1A6",
2560        "MSRValue": "0x1020",
2561        "SampleAfterValue": "100000",
2562        "UMask": "0x1"
2563    },
2564    {
2565        "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
2566        "EventCode": "0xB7",
2567        "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
2568        "MSRIndex": "0x1A6",
2569        "MSRValue": "0x820",
2570        "SampleAfterValue": "100000",
2571        "UMask": "0x1"
2572    },
2573    {
2574        "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
2575        "EventCode": "0xB7",
2576        "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
2577        "MSRIndex": "0x1A6",
2578        "MSRValue": "0x7F70",
2579        "SampleAfterValue": "100000",
2580        "UMask": "0x1"
2581    },
2582    {
2583        "BriefDescription": "All offcore prefetch requests",
2584        "EventCode": "0xB7",
2585        "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
2586        "MSRIndex": "0x1A6",
2587        "MSRValue": "0xFF70",
2588        "SampleAfterValue": "100000",
2589        "UMask": "0x1"
2590    },
2591    {
2592        "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
2593        "EventCode": "0xB7",
2594        "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
2595        "MSRIndex": "0x1A6",
2596        "MSRValue": "0x8070",
2597        "SampleAfterValue": "100000",
2598        "UMask": "0x1"
2599    },
2600    {
2601        "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
2602        "EventCode": "0xB7",
2603        "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
2604        "MSRIndex": "0x1A6",
2605        "MSRValue": "0x170",
2606        "SampleAfterValue": "100000",
2607        "UMask": "0x1"
2608    },
2609    {
2610        "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
2611        "EventCode": "0xB7",
2612        "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
2613        "MSRIndex": "0x1A6",
2614        "MSRValue": "0x270",
2615        "SampleAfterValue": "100000",
2616        "UMask": "0x1"
2617    },
2618    {
2619        "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
2620        "EventCode": "0xB7",
2621        "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
2622        "MSRIndex": "0x1A6",
2623        "MSRValue": "0x470",
2624        "SampleAfterValue": "100000",
2625        "UMask": "0x1"
2626    },
2627    {
2628        "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
2629        "EventCode": "0xB7",
2630        "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
2631        "MSRIndex": "0x1A6",
2632        "MSRValue": "0x770",
2633        "SampleAfterValue": "100000",
2634        "UMask": "0x1"
2635    },
2636    {
2637        "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
2638        "EventCode": "0xB7",
2639        "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
2640        "MSRIndex": "0x1A6",
2641        "MSRValue": "0x4770",
2642        "SampleAfterValue": "100000",
2643        "UMask": "0x1"
2644    },
2645    {
2646        "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
2647        "EventCode": "0xB7",
2648        "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
2649        "MSRIndex": "0x1A6",
2650        "MSRValue": "0x1870",
2651        "SampleAfterValue": "100000",
2652        "UMask": "0x1"
2653    },
2654    {
2655        "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
2656        "EventCode": "0xB7",
2657        "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
2658        "MSRIndex": "0x1A6",
2659        "MSRValue": "0x3870",
2660        "SampleAfterValue": "100000",
2661        "UMask": "0x1"
2662    },
2663    {
2664        "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
2665        "EventCode": "0xB7",
2666        "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
2667        "MSRIndex": "0x1A6",
2668        "MSRValue": "0x1070",
2669        "SampleAfterValue": "100000",
2670        "UMask": "0x1"
2671    },
2672    {
2673        "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
2674        "EventCode": "0xB7",
2675        "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
2676        "MSRIndex": "0x1A6",
2677        "MSRValue": "0x870",
2678        "SampleAfterValue": "100000",
2679        "UMask": "0x1"
2680    },
2681    {
2682        "BriefDescription": "Super Queue LRU hints sent to LLC",
2683        "EventCode": "0xF4",
2684        "EventName": "SQ_MISC.LRU_HINTS",
2685        "SampleAfterValue": "2000000",
2686        "UMask": "0x4"
2687    },
2688    {
2689        "BriefDescription": "Super Queue lock splits across a cache line",
2690        "EventCode": "0xF4",
2691        "EventName": "SQ_MISC.SPLIT_LOCK",
2692        "SampleAfterValue": "2000000",
2693        "UMask": "0x10"
2694    },
2695    {
2696        "BriefDescription": "Loads delayed with at-Retirement block code",
2697        "EventCode": "0x6",
2698        "EventName": "STORE_BLOCKS.AT_RET",
2699        "SampleAfterValue": "200000",
2700        "UMask": "0x4"
2701    },
2702    {
2703        "BriefDescription": "Cacheable loads delayed with L1D block code",
2704        "EventCode": "0x6",
2705        "EventName": "STORE_BLOCKS.L1D_BLOCK",
2706        "SampleAfterValue": "200000",
2707        "UMask": "0x8"
2708    }
2709]
2710