1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 52 "Counter": "0,1", 53 "EventCode": "0x52", 54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1D hardware prefetch misses", 60 "Counter": "0,1", 61 "EventCode": "0x4E", 62 "EventName": "L1D_PREFETCH.MISS", 63 "SampleAfterValue": "200000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1D hardware prefetch requests", 68 "Counter": "0,1", 69 "EventCode": "0x4E", 70 "EventName": "L1D_PREFETCH.REQUESTS", 71 "SampleAfterValue": "200000", 72 "UMask": "0x1" 73 }, 74 { 75 "BriefDescription": "L1D hardware prefetch requests triggered", 76 "Counter": "0,1", 77 "EventCode": "0x4E", 78 "EventName": "L1D_PREFETCH.TRIGGERS", 79 "SampleAfterValue": "200000", 80 "UMask": "0x4" 81 }, 82 { 83 "BriefDescription": "L1 writebacks to L2 in E state", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x28", 86 "EventName": "L1D_WB_L2.E_STATE", 87 "SampleAfterValue": "100000", 88 "UMask": "0x4" 89 }, 90 { 91 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 92 "Counter": "0,1,2,3", 93 "EventCode": "0x28", 94 "EventName": "L1D_WB_L2.I_STATE", 95 "SampleAfterValue": "100000", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "All L1 writebacks to L2", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x28", 102 "EventName": "L1D_WB_L2.MESI", 103 "SampleAfterValue": "100000", 104 "UMask": "0xf" 105 }, 106 { 107 "BriefDescription": "L1 writebacks to L2 in M state", 108 "Counter": "0,1,2,3", 109 "EventCode": "0x28", 110 "EventName": "L1D_WB_L2.M_STATE", 111 "SampleAfterValue": "100000", 112 "UMask": "0x8" 113 }, 114 { 115 "BriefDescription": "L1 writebacks to L2 in S state", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x28", 118 "EventName": "L1D_WB_L2.S_STATE", 119 "SampleAfterValue": "100000", 120 "UMask": "0x2" 121 }, 122 { 123 "BriefDescription": "All L2 data requests", 124 "Counter": "0,1,2,3", 125 "EventCode": "0x26", 126 "EventName": "L2_DATA_RQSTS.ANY", 127 "SampleAfterValue": "200000", 128 "UMask": "0xff" 129 }, 130 { 131 "BriefDescription": "L2 data demand loads in E state", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x26", 134 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 135 "SampleAfterValue": "200000", 136 "UMask": "0x4" 137 }, 138 { 139 "BriefDescription": "L2 data demand loads in I state (misses)", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x26", 142 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 143 "SampleAfterValue": "200000", 144 "UMask": "0x1" 145 }, 146 { 147 "BriefDescription": "L2 data demand requests", 148 "Counter": "0,1,2,3", 149 "EventCode": "0x26", 150 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 151 "SampleAfterValue": "200000", 152 "UMask": "0xf" 153 }, 154 { 155 "BriefDescription": "L2 data demand loads in M state", 156 "Counter": "0,1,2,3", 157 "EventCode": "0x26", 158 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 159 "SampleAfterValue": "200000", 160 "UMask": "0x8" 161 }, 162 { 163 "BriefDescription": "L2 data demand loads in S state", 164 "Counter": "0,1,2,3", 165 "EventCode": "0x26", 166 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 167 "SampleAfterValue": "200000", 168 "UMask": "0x2" 169 }, 170 { 171 "BriefDescription": "L2 data prefetches in E state", 172 "Counter": "0,1,2,3", 173 "EventCode": "0x26", 174 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 175 "SampleAfterValue": "200000", 176 "UMask": "0x40" 177 }, 178 { 179 "BriefDescription": "L2 data prefetches in the I state (misses)", 180 "Counter": "0,1,2,3", 181 "EventCode": "0x26", 182 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 183 "SampleAfterValue": "200000", 184 "UMask": "0x10" 185 }, 186 { 187 "BriefDescription": "All L2 data prefetches", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x26", 190 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 191 "SampleAfterValue": "200000", 192 "UMask": "0xf0" 193 }, 194 { 195 "BriefDescription": "L2 data prefetches in M state", 196 "Counter": "0,1,2,3", 197 "EventCode": "0x26", 198 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 199 "SampleAfterValue": "200000", 200 "UMask": "0x80" 201 }, 202 { 203 "BriefDescription": "L2 data prefetches in the S state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x26", 206 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 207 "SampleAfterValue": "200000", 208 "UMask": "0x20" 209 }, 210 { 211 "BriefDescription": "L2 lines alloacated", 212 "Counter": "0,1,2,3", 213 "EventCode": "0xF1", 214 "EventName": "L2_LINES_IN.ANY", 215 "SampleAfterValue": "100000", 216 "UMask": "0x7" 217 }, 218 { 219 "BriefDescription": "L2 lines allocated in the E state", 220 "Counter": "0,1,2,3", 221 "EventCode": "0xF1", 222 "EventName": "L2_LINES_IN.E_STATE", 223 "SampleAfterValue": "100000", 224 "UMask": "0x4" 225 }, 226 { 227 "BriefDescription": "L2 lines allocated in the S state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0xF1", 230 "EventName": "L2_LINES_IN.S_STATE", 231 "SampleAfterValue": "100000", 232 "UMask": "0x2" 233 }, 234 { 235 "BriefDescription": "L2 lines evicted", 236 "Counter": "0,1,2,3", 237 "EventCode": "0xF2", 238 "EventName": "L2_LINES_OUT.ANY", 239 "SampleAfterValue": "100000", 240 "UMask": "0xf" 241 }, 242 { 243 "BriefDescription": "L2 lines evicted by a demand request", 244 "Counter": "0,1,2,3", 245 "EventCode": "0xF2", 246 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 247 "SampleAfterValue": "100000", 248 "UMask": "0x1" 249 }, 250 { 251 "BriefDescription": "L2 modified lines evicted by a demand request", 252 "Counter": "0,1,2,3", 253 "EventCode": "0xF2", 254 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 255 "SampleAfterValue": "100000", 256 "UMask": "0x2" 257 }, 258 { 259 "BriefDescription": "L2 lines evicted by a prefetch request", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xF2", 262 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 263 "SampleAfterValue": "100000", 264 "UMask": "0x4" 265 }, 266 { 267 "BriefDescription": "L2 modified lines evicted by a prefetch request", 268 "Counter": "0,1,2,3", 269 "EventCode": "0xF2", 270 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 271 "SampleAfterValue": "100000", 272 "UMask": "0x8" 273 }, 274 { 275 "BriefDescription": "L2 instruction fetches", 276 "Counter": "0,1,2,3", 277 "EventCode": "0x24", 278 "EventName": "L2_RQSTS.IFETCHES", 279 "SampleAfterValue": "200000", 280 "UMask": "0x30" 281 }, 282 { 283 "BriefDescription": "L2 instruction fetch hits", 284 "Counter": "0,1,2,3", 285 "EventCode": "0x24", 286 "EventName": "L2_RQSTS.IFETCH_HIT", 287 "SampleAfterValue": "200000", 288 "UMask": "0x10" 289 }, 290 { 291 "BriefDescription": "L2 instruction fetch misses", 292 "Counter": "0,1,2,3", 293 "EventCode": "0x24", 294 "EventName": "L2_RQSTS.IFETCH_MISS", 295 "SampleAfterValue": "200000", 296 "UMask": "0x20" 297 }, 298 { 299 "BriefDescription": "L2 load hits", 300 "Counter": "0,1,2,3", 301 "EventCode": "0x24", 302 "EventName": "L2_RQSTS.LD_HIT", 303 "SampleAfterValue": "200000", 304 "UMask": "0x1" 305 }, 306 { 307 "BriefDescription": "L2 load misses", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x24", 310 "EventName": "L2_RQSTS.LD_MISS", 311 "SampleAfterValue": "200000", 312 "UMask": "0x2" 313 }, 314 { 315 "BriefDescription": "L2 requests", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x24", 318 "EventName": "L2_RQSTS.LOADS", 319 "SampleAfterValue": "200000", 320 "UMask": "0x3" 321 }, 322 { 323 "BriefDescription": "All L2 misses", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x24", 326 "EventName": "L2_RQSTS.MISS", 327 "SampleAfterValue": "200000", 328 "UMask": "0xaa" 329 }, 330 { 331 "BriefDescription": "All L2 prefetches", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x24", 334 "EventName": "L2_RQSTS.PREFETCHES", 335 "SampleAfterValue": "200000", 336 "UMask": "0xc0" 337 }, 338 { 339 "BriefDescription": "L2 prefetch hits", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x24", 342 "EventName": "L2_RQSTS.PREFETCH_HIT", 343 "SampleAfterValue": "200000", 344 "UMask": "0x40" 345 }, 346 { 347 "BriefDescription": "L2 prefetch misses", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x24", 350 "EventName": "L2_RQSTS.PREFETCH_MISS", 351 "SampleAfterValue": "200000", 352 "UMask": "0x80" 353 }, 354 { 355 "BriefDescription": "All L2 requests", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x24", 358 "EventName": "L2_RQSTS.REFERENCES", 359 "SampleAfterValue": "200000", 360 "UMask": "0xff" 361 }, 362 { 363 "BriefDescription": "L2 RFO requests", 364 "Counter": "0,1,2,3", 365 "EventCode": "0x24", 366 "EventName": "L2_RQSTS.RFOS", 367 "SampleAfterValue": "200000", 368 "UMask": "0xc" 369 }, 370 { 371 "BriefDescription": "L2 RFO hits", 372 "Counter": "0,1,2,3", 373 "EventCode": "0x24", 374 "EventName": "L2_RQSTS.RFO_HIT", 375 "SampleAfterValue": "200000", 376 "UMask": "0x4" 377 }, 378 { 379 "BriefDescription": "L2 RFO misses", 380 "Counter": "0,1,2,3", 381 "EventCode": "0x24", 382 "EventName": "L2_RQSTS.RFO_MISS", 383 "SampleAfterValue": "200000", 384 "UMask": "0x8" 385 }, 386 { 387 "BriefDescription": "All L2 transactions", 388 "Counter": "0,1,2,3", 389 "EventCode": "0xF0", 390 "EventName": "L2_TRANSACTIONS.ANY", 391 "SampleAfterValue": "200000", 392 "UMask": "0x80" 393 }, 394 { 395 "BriefDescription": "L2 fill transactions", 396 "Counter": "0,1,2,3", 397 "EventCode": "0xF0", 398 "EventName": "L2_TRANSACTIONS.FILL", 399 "SampleAfterValue": "200000", 400 "UMask": "0x20" 401 }, 402 { 403 "BriefDescription": "L2 instruction fetch transactions", 404 "Counter": "0,1,2,3", 405 "EventCode": "0xF0", 406 "EventName": "L2_TRANSACTIONS.IFETCH", 407 "SampleAfterValue": "200000", 408 "UMask": "0x4" 409 }, 410 { 411 "BriefDescription": "L1D writeback to L2 transactions", 412 "Counter": "0,1,2,3", 413 "EventCode": "0xF0", 414 "EventName": "L2_TRANSACTIONS.L1D_WB", 415 "SampleAfterValue": "200000", 416 "UMask": "0x10" 417 }, 418 { 419 "BriefDescription": "L2 Load transactions", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xF0", 422 "EventName": "L2_TRANSACTIONS.LOAD", 423 "SampleAfterValue": "200000", 424 "UMask": "0x1" 425 }, 426 { 427 "BriefDescription": "L2 prefetch transactions", 428 "Counter": "0,1,2,3", 429 "EventCode": "0xF0", 430 "EventName": "L2_TRANSACTIONS.PREFETCH", 431 "SampleAfterValue": "200000", 432 "UMask": "0x8" 433 }, 434 { 435 "BriefDescription": "L2 RFO transactions", 436 "Counter": "0,1,2,3", 437 "EventCode": "0xF0", 438 "EventName": "L2_TRANSACTIONS.RFO", 439 "SampleAfterValue": "200000", 440 "UMask": "0x2" 441 }, 442 { 443 "BriefDescription": "L2 writeback to LLC transactions", 444 "Counter": "0,1,2,3", 445 "EventCode": "0xF0", 446 "EventName": "L2_TRANSACTIONS.WB", 447 "SampleAfterValue": "200000", 448 "UMask": "0x40" 449 }, 450 { 451 "BriefDescription": "L2 demand lock RFOs in E state", 452 "Counter": "0,1,2,3", 453 "EventCode": "0x27", 454 "EventName": "L2_WRITE.LOCK.E_STATE", 455 "SampleAfterValue": "100000", 456 "UMask": "0x40" 457 }, 458 { 459 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 460 "Counter": "0,1,2,3", 461 "EventCode": "0x27", 462 "EventName": "L2_WRITE.LOCK.HIT", 463 "SampleAfterValue": "100000", 464 "UMask": "0xe0" 465 }, 466 { 467 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 468 "Counter": "0,1,2,3", 469 "EventCode": "0x27", 470 "EventName": "L2_WRITE.LOCK.I_STATE", 471 "SampleAfterValue": "100000", 472 "UMask": "0x10" 473 }, 474 { 475 "BriefDescription": "All demand L2 lock RFOs", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x27", 478 "EventName": "L2_WRITE.LOCK.MESI", 479 "SampleAfterValue": "100000", 480 "UMask": "0xf0" 481 }, 482 { 483 "BriefDescription": "L2 demand lock RFOs in M state", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x27", 486 "EventName": "L2_WRITE.LOCK.M_STATE", 487 "SampleAfterValue": "100000", 488 "UMask": "0x80" 489 }, 490 { 491 "BriefDescription": "L2 demand lock RFOs in S state", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x27", 494 "EventName": "L2_WRITE.LOCK.S_STATE", 495 "SampleAfterValue": "100000", 496 "UMask": "0x20" 497 }, 498 { 499 "BriefDescription": "All L2 demand store RFOs that hit the cache", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x27", 502 "EventName": "L2_WRITE.RFO.HIT", 503 "SampleAfterValue": "100000", 504 "UMask": "0xe" 505 }, 506 { 507 "BriefDescription": "L2 demand store RFOs in I state (misses)", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x27", 510 "EventName": "L2_WRITE.RFO.I_STATE", 511 "SampleAfterValue": "100000", 512 "UMask": "0x1" 513 }, 514 { 515 "BriefDescription": "All L2 demand store RFOs", 516 "Counter": "0,1,2,3", 517 "EventCode": "0x27", 518 "EventName": "L2_WRITE.RFO.MESI", 519 "SampleAfterValue": "100000", 520 "UMask": "0xf" 521 }, 522 { 523 "BriefDescription": "L2 demand store RFOs in M state", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x27", 526 "EventName": "L2_WRITE.RFO.M_STATE", 527 "SampleAfterValue": "100000", 528 "UMask": "0x8" 529 }, 530 { 531 "BriefDescription": "L2 demand store RFOs in S state", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x27", 534 "EventName": "L2_WRITE.RFO.S_STATE", 535 "SampleAfterValue": "100000", 536 "UMask": "0x2" 537 }, 538 { 539 "BriefDescription": "Longest latency cache miss", 540 "Counter": "0,1,2,3", 541 "EventCode": "0x2E", 542 "EventName": "LONGEST_LAT_CACHE.MISS", 543 "SampleAfterValue": "100000", 544 "UMask": "0x41" 545 }, 546 { 547 "BriefDescription": "Longest latency cache reference", 548 "Counter": "0,1,2,3", 549 "EventCode": "0x2E", 550 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 551 "SampleAfterValue": "200000", 552 "UMask": "0x4f" 553 }, 554 { 555 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 556 "Counter": "3", 557 "EventCode": "0xB", 558 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 559 "MSRIndex": "0x3F6", 560 "MSRValue": "0x0", 561 "PEBS": "2", 562 "SampleAfterValue": "2000000", 563 "UMask": "0x10" 564 }, 565 { 566 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 567 "Counter": "3", 568 "EventCode": "0xB", 569 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 570 "MSRIndex": "0x3F6", 571 "MSRValue": "0x400", 572 "PEBS": "2", 573 "SampleAfterValue": "100", 574 "UMask": "0x10" 575 }, 576 { 577 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 578 "Counter": "3", 579 "EventCode": "0xB", 580 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 581 "MSRIndex": "0x3F6", 582 "MSRValue": "0x80", 583 "PEBS": "2", 584 "SampleAfterValue": "1000", 585 "UMask": "0x10" 586 }, 587 { 588 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 589 "Counter": "3", 590 "EventCode": "0xB", 591 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 592 "MSRIndex": "0x3F6", 593 "MSRValue": "0x10", 594 "PEBS": "2", 595 "SampleAfterValue": "10000", 596 "UMask": "0x10" 597 }, 598 { 599 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 600 "Counter": "3", 601 "EventCode": "0xB", 602 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 603 "MSRIndex": "0x3F6", 604 "MSRValue": "0x4000", 605 "PEBS": "2", 606 "SampleAfterValue": "5", 607 "UMask": "0x10" 608 }, 609 { 610 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 611 "Counter": "3", 612 "EventCode": "0xB", 613 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 614 "MSRIndex": "0x3F6", 615 "MSRValue": "0x800", 616 "PEBS": "2", 617 "SampleAfterValue": "50", 618 "UMask": "0x10" 619 }, 620 { 621 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 622 "Counter": "3", 623 "EventCode": "0xB", 624 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 625 "MSRIndex": "0x3F6", 626 "MSRValue": "0x100", 627 "PEBS": "2", 628 "SampleAfterValue": "500", 629 "UMask": "0x10" 630 }, 631 { 632 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 633 "Counter": "3", 634 "EventCode": "0xB", 635 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 636 "MSRIndex": "0x3F6", 637 "MSRValue": "0x20", 638 "PEBS": "2", 639 "SampleAfterValue": "5000", 640 "UMask": "0x10" 641 }, 642 { 643 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 644 "Counter": "3", 645 "EventCode": "0xB", 646 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 647 "MSRIndex": "0x3F6", 648 "MSRValue": "0x8000", 649 "PEBS": "2", 650 "SampleAfterValue": "3", 651 "UMask": "0x10" 652 }, 653 { 654 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 655 "Counter": "3", 656 "EventCode": "0xB", 657 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 658 "MSRIndex": "0x3F6", 659 "MSRValue": "0x4", 660 "PEBS": "2", 661 "SampleAfterValue": "50000", 662 "UMask": "0x10" 663 }, 664 { 665 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 666 "Counter": "3", 667 "EventCode": "0xB", 668 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 669 "MSRIndex": "0x3F6", 670 "MSRValue": "0x1000", 671 "PEBS": "2", 672 "SampleAfterValue": "20", 673 "UMask": "0x10" 674 }, 675 { 676 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 677 "Counter": "3", 678 "EventCode": "0xB", 679 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 680 "MSRIndex": "0x3F6", 681 "MSRValue": "0x200", 682 "PEBS": "2", 683 "SampleAfterValue": "200", 684 "UMask": "0x10" 685 }, 686 { 687 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 688 "Counter": "3", 689 "EventCode": "0xB", 690 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 691 "MSRIndex": "0x3F6", 692 "MSRValue": "0x40", 693 "PEBS": "2", 694 "SampleAfterValue": "2000", 695 "UMask": "0x10" 696 }, 697 { 698 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 699 "Counter": "3", 700 "EventCode": "0xB", 701 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 702 "MSRIndex": "0x3F6", 703 "MSRValue": "0x8", 704 "PEBS": "2", 705 "SampleAfterValue": "20000", 706 "UMask": "0x10" 707 }, 708 { 709 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 710 "Counter": "3", 711 "EventCode": "0xB", 712 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 713 "MSRIndex": "0x3F6", 714 "MSRValue": "0x2000", 715 "PEBS": "2", 716 "SampleAfterValue": "10", 717 "UMask": "0x10" 718 }, 719 { 720 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 721 "Counter": "0,1,2,3", 722 "EventCode": "0xB", 723 "EventName": "MEM_INST_RETIRED.LOADS", 724 "PEBS": "1", 725 "SampleAfterValue": "2000000", 726 "UMask": "0x1" 727 }, 728 { 729 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 730 "Counter": "0,1,2,3", 731 "EventCode": "0xB", 732 "EventName": "MEM_INST_RETIRED.STORES", 733 "PEBS": "1", 734 "SampleAfterValue": "2000000", 735 "UMask": "0x2" 736 }, 737 { 738 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 739 "Counter": "0,1,2,3", 740 "EventCode": "0xCB", 741 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 742 "PEBS": "1", 743 "SampleAfterValue": "200000", 744 "UMask": "0x40" 745 }, 746 { 747 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 748 "Counter": "0,1,2,3", 749 "EventCode": "0xCB", 750 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 751 "PEBS": "1", 752 "SampleAfterValue": "2000000", 753 "UMask": "0x1" 754 }, 755 { 756 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 757 "Counter": "0,1,2,3", 758 "EventCode": "0xCB", 759 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 760 "PEBS": "1", 761 "SampleAfterValue": "200000", 762 "UMask": "0x2" 763 }, 764 { 765 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 766 "Counter": "0,1,2,3", 767 "EventCode": "0xCB", 768 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 769 "PEBS": "1", 770 "SampleAfterValue": "10000", 771 "UMask": "0x10" 772 }, 773 { 774 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 775 "Counter": "0,1,2,3", 776 "EventCode": "0xCB", 777 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 778 "PEBS": "1", 779 "SampleAfterValue": "40000", 780 "UMask": "0x4" 781 }, 782 { 783 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 784 "Counter": "0,1,2,3", 785 "EventCode": "0xCB", 786 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 787 "PEBS": "1", 788 "SampleAfterValue": "40000", 789 "UMask": "0x8" 790 }, 791 { 792 "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)", 793 "Counter": "0,1,2,3", 794 "EventCode": "0xF", 795 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 796 "PEBS": "1", 797 "SampleAfterValue": "20000", 798 "UMask": "0x8" 799 }, 800 { 801 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", 802 "Counter": "0,1,2,3", 803 "EventCode": "0xF", 804 "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", 805 "PEBS": "1", 806 "SampleAfterValue": "40000", 807 "UMask": "0x2" 808 }, 809 { 810 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", 811 "Counter": "0,1,2,3", 812 "EventCode": "0xF", 813 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", 814 "PEBS": "1", 815 "SampleAfterValue": "10000", 816 "UMask": "0x20" 817 }, 818 { 819 "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)", 820 "Counter": "0,1,2,3", 821 "EventCode": "0xF", 822 "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM", 823 "PEBS": "1", 824 "SampleAfterValue": "40000", 825 "UMask": "0x4" 826 }, 827 { 828 "BriefDescription": "Load instructions retired IO (Precise Event)", 829 "Counter": "0,1,2,3", 830 "EventCode": "0xF", 831 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", 832 "PEBS": "1", 833 "SampleAfterValue": "4000", 834 "UMask": "0x80" 835 }, 836 { 837 "BriefDescription": "All offcore requests", 838 "Counter": "0,1,2,3", 839 "EventCode": "0xB0", 840 "EventName": "OFFCORE_REQUESTS.ANY", 841 "SampleAfterValue": "100000", 842 "UMask": "0x80" 843 }, 844 { 845 "BriefDescription": "Offcore read requests", 846 "Counter": "0,1,2,3", 847 "EventCode": "0xB0", 848 "EventName": "OFFCORE_REQUESTS.ANY.READ", 849 "SampleAfterValue": "100000", 850 "UMask": "0x8" 851 }, 852 { 853 "BriefDescription": "Offcore RFO requests", 854 "Counter": "0,1,2,3", 855 "EventCode": "0xB0", 856 "EventName": "OFFCORE_REQUESTS.ANY.RFO", 857 "SampleAfterValue": "100000", 858 "UMask": "0x10" 859 }, 860 { 861 "BriefDescription": "Offcore demand code read requests", 862 "Counter": "0,1,2,3", 863 "EventCode": "0xB0", 864 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", 865 "SampleAfterValue": "100000", 866 "UMask": "0x2" 867 }, 868 { 869 "BriefDescription": "Offcore demand data read requests", 870 "Counter": "0,1,2,3", 871 "EventCode": "0xB0", 872 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", 873 "SampleAfterValue": "100000", 874 "UMask": "0x1" 875 }, 876 { 877 "BriefDescription": "Offcore demand RFO requests", 878 "Counter": "0,1,2,3", 879 "EventCode": "0xB0", 880 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", 881 "SampleAfterValue": "100000", 882 "UMask": "0x4" 883 }, 884 { 885 "BriefDescription": "Offcore L1 data cache writebacks", 886 "Counter": "0,1,2,3", 887 "EventCode": "0xB0", 888 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 889 "SampleAfterValue": "100000", 890 "UMask": "0x40" 891 }, 892 { 893 "BriefDescription": "Outstanding offcore reads", 894 "EventCode": "0x60", 895 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", 896 "SampleAfterValue": "2000000", 897 "UMask": "0x8" 898 }, 899 { 900 "BriefDescription": "Cycles offcore reads busy", 901 "CounterMask": "1", 902 "EventCode": "0x60", 903 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", 904 "SampleAfterValue": "2000000", 905 "UMask": "0x8" 906 }, 907 { 908 "BriefDescription": "Outstanding offcore demand code reads", 909 "EventCode": "0x60", 910 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", 911 "SampleAfterValue": "2000000", 912 "UMask": "0x2" 913 }, 914 { 915 "BriefDescription": "Cycles offcore demand code read busy", 916 "CounterMask": "1", 917 "EventCode": "0x60", 918 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", 919 "SampleAfterValue": "2000000", 920 "UMask": "0x2" 921 }, 922 { 923 "BriefDescription": "Outstanding offcore demand data reads", 924 "EventCode": "0x60", 925 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", 926 "SampleAfterValue": "2000000", 927 "UMask": "0x1" 928 }, 929 { 930 "BriefDescription": "Cycles offcore demand data read busy", 931 "CounterMask": "1", 932 "EventCode": "0x60", 933 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", 934 "SampleAfterValue": "2000000", 935 "UMask": "0x1" 936 }, 937 { 938 "BriefDescription": "Outstanding offcore demand RFOs", 939 "EventCode": "0x60", 940 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", 941 "SampleAfterValue": "2000000", 942 "UMask": "0x4" 943 }, 944 { 945 "BriefDescription": "Cycles offcore demand RFOs busy", 946 "CounterMask": "1", 947 "EventCode": "0x60", 948 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", 949 "SampleAfterValue": "2000000", 950 "UMask": "0x4" 951 }, 952 { 953 "BriefDescription": "Offcore requests blocked due to Super Queue full", 954 "Counter": "0,1,2,3", 955 "EventCode": "0xB2", 956 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 957 "SampleAfterValue": "100000", 958 "UMask": "0x1" 959 }, 960 { 961 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 962 "Counter": "2", 963 "EventCode": "0xB7", 964 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 965 "MSRIndex": "0x1A6", 966 "MSRValue": "0x7F11", 967 "Offcore": "1", 968 "SampleAfterValue": "100000", 969 "UMask": "0x1" 970 }, 971 { 972 "BriefDescription": "All offcore data reads", 973 "Counter": "2", 974 "EventCode": "0xB7", 975 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 976 "MSRIndex": "0x1A6", 977 "MSRValue": "0xFF11", 978 "Offcore": "1", 979 "SampleAfterValue": "100000", 980 "UMask": "0x1" 981 }, 982 { 983 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 984 "Counter": "2", 985 "EventCode": "0xB7", 986 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 987 "MSRIndex": "0x1A6", 988 "MSRValue": "0x8011", 989 "Offcore": "1", 990 "SampleAfterValue": "100000", 991 "UMask": "0x1" 992 }, 993 { 994 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 995 "Counter": "2", 996 "EventCode": "0xB7", 997 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 998 "MSRIndex": "0x1A6", 999 "MSRValue": "0x111", 1000 "Offcore": "1", 1001 "SampleAfterValue": "100000", 1002 "UMask": "0x1" 1003 }, 1004 { 1005 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 1006 "Counter": "2", 1007 "EventCode": "0xB7", 1008 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1009 "MSRIndex": "0x1A6", 1010 "MSRValue": "0x211", 1011 "Offcore": "1", 1012 "SampleAfterValue": "100000", 1013 "UMask": "0x1" 1014 }, 1015 { 1016 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 1017 "Counter": "2", 1018 "EventCode": "0xB7", 1019 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1020 "MSRIndex": "0x1A6", 1021 "MSRValue": "0x411", 1022 "Offcore": "1", 1023 "SampleAfterValue": "100000", 1024 "UMask": "0x1" 1025 }, 1026 { 1027 "BriefDescription": "Offcore data reads satisfied by the LLC", 1028 "Counter": "2", 1029 "EventCode": "0xB7", 1030 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1031 "MSRIndex": "0x1A6", 1032 "MSRValue": "0x711", 1033 "Offcore": "1", 1034 "SampleAfterValue": "100000", 1035 "UMask": "0x1" 1036 }, 1037 { 1038 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 1039 "Counter": "2", 1040 "EventCode": "0xB7", 1041 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1042 "MSRIndex": "0x1A6", 1043 "MSRValue": "0x4711", 1044 "Offcore": "1", 1045 "SampleAfterValue": "100000", 1046 "UMask": "0x1" 1047 }, 1048 { 1049 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1050 "Counter": "2", 1051 "EventCode": "0xB7", 1052 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1053 "MSRIndex": "0x1A6", 1054 "MSRValue": "0x1811", 1055 "Offcore": "1", 1056 "SampleAfterValue": "100000", 1057 "UMask": "0x1" 1058 }, 1059 { 1060 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1061 "Counter": "2", 1062 "EventCode": "0xB7", 1063 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1064 "MSRIndex": "0x1A6", 1065 "MSRValue": "0x3811", 1066 "Offcore": "1", 1067 "SampleAfterValue": "100000", 1068 "UMask": "0x1" 1069 }, 1070 { 1071 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1072 "Counter": "2", 1073 "EventCode": "0xB7", 1074 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1075 "MSRIndex": "0x1A6", 1076 "MSRValue": "0x1011", 1077 "Offcore": "1", 1078 "SampleAfterValue": "100000", 1079 "UMask": "0x1" 1080 }, 1081 { 1082 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1083 "Counter": "2", 1084 "EventCode": "0xB7", 1085 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1086 "MSRIndex": "0x1A6", 1087 "MSRValue": "0x811", 1088 "Offcore": "1", 1089 "SampleAfterValue": "100000", 1090 "UMask": "0x1" 1091 }, 1092 { 1093 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1094 "Counter": "2", 1095 "EventCode": "0xB7", 1096 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1097 "MSRIndex": "0x1A6", 1098 "MSRValue": "0x7F44", 1099 "Offcore": "1", 1100 "SampleAfterValue": "100000", 1101 "UMask": "0x1" 1102 }, 1103 { 1104 "BriefDescription": "All offcore code reads", 1105 "Counter": "2", 1106 "EventCode": "0xB7", 1107 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1108 "MSRIndex": "0x1A6", 1109 "MSRValue": "0xFF44", 1110 "Offcore": "1", 1111 "SampleAfterValue": "100000", 1112 "UMask": "0x1" 1113 }, 1114 { 1115 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1116 "Counter": "2", 1117 "EventCode": "0xB7", 1118 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1119 "MSRIndex": "0x1A6", 1120 "MSRValue": "0x8044", 1121 "Offcore": "1", 1122 "SampleAfterValue": "100000", 1123 "UMask": "0x1" 1124 }, 1125 { 1126 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1127 "Counter": "2", 1128 "EventCode": "0xB7", 1129 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1130 "MSRIndex": "0x1A6", 1131 "MSRValue": "0x144", 1132 "Offcore": "1", 1133 "SampleAfterValue": "100000", 1134 "UMask": "0x1" 1135 }, 1136 { 1137 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1138 "Counter": "2", 1139 "EventCode": "0xB7", 1140 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1141 "MSRIndex": "0x1A6", 1142 "MSRValue": "0x244", 1143 "Offcore": "1", 1144 "SampleAfterValue": "100000", 1145 "UMask": "0x1" 1146 }, 1147 { 1148 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1149 "Counter": "2", 1150 "EventCode": "0xB7", 1151 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1152 "MSRIndex": "0x1A6", 1153 "MSRValue": "0x444", 1154 "Offcore": "1", 1155 "SampleAfterValue": "100000", 1156 "UMask": "0x1" 1157 }, 1158 { 1159 "BriefDescription": "Offcore code reads satisfied by the LLC", 1160 "Counter": "2", 1161 "EventCode": "0xB7", 1162 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1163 "MSRIndex": "0x1A6", 1164 "MSRValue": "0x744", 1165 "Offcore": "1", 1166 "SampleAfterValue": "100000", 1167 "UMask": "0x1" 1168 }, 1169 { 1170 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1171 "Counter": "2", 1172 "EventCode": "0xB7", 1173 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1174 "MSRIndex": "0x1A6", 1175 "MSRValue": "0x4744", 1176 "Offcore": "1", 1177 "SampleAfterValue": "100000", 1178 "UMask": "0x1" 1179 }, 1180 { 1181 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1182 "Counter": "2", 1183 "EventCode": "0xB7", 1184 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1185 "MSRIndex": "0x1A6", 1186 "MSRValue": "0x1844", 1187 "Offcore": "1", 1188 "SampleAfterValue": "100000", 1189 "UMask": "0x1" 1190 }, 1191 { 1192 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1193 "Counter": "2", 1194 "EventCode": "0xB7", 1195 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1196 "MSRIndex": "0x1A6", 1197 "MSRValue": "0x3844", 1198 "Offcore": "1", 1199 "SampleAfterValue": "100000", 1200 "UMask": "0x1" 1201 }, 1202 { 1203 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1204 "Counter": "2", 1205 "EventCode": "0xB7", 1206 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1207 "MSRIndex": "0x1A6", 1208 "MSRValue": "0x1044", 1209 "Offcore": "1", 1210 "SampleAfterValue": "100000", 1211 "UMask": "0x1" 1212 }, 1213 { 1214 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1215 "Counter": "2", 1216 "EventCode": "0xB7", 1217 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1218 "MSRIndex": "0x1A6", 1219 "MSRValue": "0x844", 1220 "Offcore": "1", 1221 "SampleAfterValue": "100000", 1222 "UMask": "0x1" 1223 }, 1224 { 1225 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1226 "Counter": "2", 1227 "EventCode": "0xB7", 1228 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1229 "MSRIndex": "0x1A6", 1230 "MSRValue": "0x7FFF", 1231 "Offcore": "1", 1232 "SampleAfterValue": "100000", 1233 "UMask": "0x1" 1234 }, 1235 { 1236 "BriefDescription": "All offcore requests", 1237 "Counter": "2", 1238 "EventCode": "0xB7", 1239 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1240 "MSRIndex": "0x1A6", 1241 "MSRValue": "0xFFFF", 1242 "Offcore": "1", 1243 "SampleAfterValue": "100000", 1244 "UMask": "0x1" 1245 }, 1246 { 1247 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1248 "Counter": "2", 1249 "EventCode": "0xB7", 1250 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1251 "MSRIndex": "0x1A6", 1252 "MSRValue": "0x80FF", 1253 "Offcore": "1", 1254 "SampleAfterValue": "100000", 1255 "UMask": "0x1" 1256 }, 1257 { 1258 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1259 "Counter": "2", 1260 "EventCode": "0xB7", 1261 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1262 "MSRIndex": "0x1A6", 1263 "MSRValue": "0x1FF", 1264 "Offcore": "1", 1265 "SampleAfterValue": "100000", 1266 "UMask": "0x1" 1267 }, 1268 { 1269 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1270 "Counter": "2", 1271 "EventCode": "0xB7", 1272 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1273 "MSRIndex": "0x1A6", 1274 "MSRValue": "0x2FF", 1275 "Offcore": "1", 1276 "SampleAfterValue": "100000", 1277 "UMask": "0x1" 1278 }, 1279 { 1280 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1281 "Counter": "2", 1282 "EventCode": "0xB7", 1283 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1284 "MSRIndex": "0x1A6", 1285 "MSRValue": "0x4FF", 1286 "Offcore": "1", 1287 "SampleAfterValue": "100000", 1288 "UMask": "0x1" 1289 }, 1290 { 1291 "BriefDescription": "Offcore requests satisfied by the LLC", 1292 "Counter": "2", 1293 "EventCode": "0xB7", 1294 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1295 "MSRIndex": "0x1A6", 1296 "MSRValue": "0x7FF", 1297 "Offcore": "1", 1298 "SampleAfterValue": "100000", 1299 "UMask": "0x1" 1300 }, 1301 { 1302 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1303 "Counter": "2", 1304 "EventCode": "0xB7", 1305 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1306 "MSRIndex": "0x1A6", 1307 "MSRValue": "0x47FF", 1308 "Offcore": "1", 1309 "SampleAfterValue": "100000", 1310 "UMask": "0x1" 1311 }, 1312 { 1313 "BriefDescription": "Offcore requests satisfied by a remote cache", 1314 "Counter": "2", 1315 "EventCode": "0xB7", 1316 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1317 "MSRIndex": "0x1A6", 1318 "MSRValue": "0x18FF", 1319 "Offcore": "1", 1320 "SampleAfterValue": "100000", 1321 "UMask": "0x1" 1322 }, 1323 { 1324 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1325 "Counter": "2", 1326 "EventCode": "0xB7", 1327 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1328 "MSRIndex": "0x1A6", 1329 "MSRValue": "0x38FF", 1330 "Offcore": "1", 1331 "SampleAfterValue": "100000", 1332 "UMask": "0x1" 1333 }, 1334 { 1335 "BriefDescription": "Offcore requests that HIT in a remote cache", 1336 "Counter": "2", 1337 "EventCode": "0xB7", 1338 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1339 "MSRIndex": "0x1A6", 1340 "MSRValue": "0x10FF", 1341 "Offcore": "1", 1342 "SampleAfterValue": "100000", 1343 "UMask": "0x1" 1344 }, 1345 { 1346 "BriefDescription": "Offcore requests that HITM in a remote cache", 1347 "Counter": "2", 1348 "EventCode": "0xB7", 1349 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1350 "MSRIndex": "0x1A6", 1351 "MSRValue": "0x8FF", 1352 "Offcore": "1", 1353 "SampleAfterValue": "100000", 1354 "UMask": "0x1" 1355 }, 1356 { 1357 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1358 "Counter": "2", 1359 "EventCode": "0xB7", 1360 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1361 "MSRIndex": "0x1A6", 1362 "MSRValue": "0x7F22", 1363 "Offcore": "1", 1364 "SampleAfterValue": "100000", 1365 "UMask": "0x1" 1366 }, 1367 { 1368 "BriefDescription": "All offcore RFO requests", 1369 "Counter": "2", 1370 "EventCode": "0xB7", 1371 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1372 "MSRIndex": "0x1A6", 1373 "MSRValue": "0xFF22", 1374 "Offcore": "1", 1375 "SampleAfterValue": "100000", 1376 "UMask": "0x1" 1377 }, 1378 { 1379 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1380 "Counter": "2", 1381 "EventCode": "0xB7", 1382 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1383 "MSRIndex": "0x1A6", 1384 "MSRValue": "0x8022", 1385 "Offcore": "1", 1386 "SampleAfterValue": "100000", 1387 "UMask": "0x1" 1388 }, 1389 { 1390 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1391 "Counter": "2", 1392 "EventCode": "0xB7", 1393 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1394 "MSRIndex": "0x1A6", 1395 "MSRValue": "0x122", 1396 "Offcore": "1", 1397 "SampleAfterValue": "100000", 1398 "UMask": "0x1" 1399 }, 1400 { 1401 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1402 "Counter": "2", 1403 "EventCode": "0xB7", 1404 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1405 "MSRIndex": "0x1A6", 1406 "MSRValue": "0x222", 1407 "Offcore": "1", 1408 "SampleAfterValue": "100000", 1409 "UMask": "0x1" 1410 }, 1411 { 1412 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1413 "Counter": "2", 1414 "EventCode": "0xB7", 1415 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1416 "MSRIndex": "0x1A6", 1417 "MSRValue": "0x422", 1418 "Offcore": "1", 1419 "SampleAfterValue": "100000", 1420 "UMask": "0x1" 1421 }, 1422 { 1423 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1424 "Counter": "2", 1425 "EventCode": "0xB7", 1426 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1427 "MSRIndex": "0x1A6", 1428 "MSRValue": "0x722", 1429 "Offcore": "1", 1430 "SampleAfterValue": "100000", 1431 "UMask": "0x1" 1432 }, 1433 { 1434 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1435 "Counter": "2", 1436 "EventCode": "0xB7", 1437 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1438 "MSRIndex": "0x1A6", 1439 "MSRValue": "0x4722", 1440 "Offcore": "1", 1441 "SampleAfterValue": "100000", 1442 "UMask": "0x1" 1443 }, 1444 { 1445 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1446 "Counter": "2", 1447 "EventCode": "0xB7", 1448 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1449 "MSRIndex": "0x1A6", 1450 "MSRValue": "0x1822", 1451 "Offcore": "1", 1452 "SampleAfterValue": "100000", 1453 "UMask": "0x1" 1454 }, 1455 { 1456 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1457 "Counter": "2", 1458 "EventCode": "0xB7", 1459 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1460 "MSRIndex": "0x1A6", 1461 "MSRValue": "0x3822", 1462 "Offcore": "1", 1463 "SampleAfterValue": "100000", 1464 "UMask": "0x1" 1465 }, 1466 { 1467 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1468 "Counter": "2", 1469 "EventCode": "0xB7", 1470 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1471 "MSRIndex": "0x1A6", 1472 "MSRValue": "0x1022", 1473 "Offcore": "1", 1474 "SampleAfterValue": "100000", 1475 "UMask": "0x1" 1476 }, 1477 { 1478 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1479 "Counter": "2", 1480 "EventCode": "0xB7", 1481 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1482 "MSRIndex": "0x1A6", 1483 "MSRValue": "0x822", 1484 "Offcore": "1", 1485 "SampleAfterValue": "100000", 1486 "UMask": "0x1" 1487 }, 1488 { 1489 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1490 "Counter": "2", 1491 "EventCode": "0xB7", 1492 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1493 "MSRIndex": "0x1A6", 1494 "MSRValue": "0x7F08", 1495 "Offcore": "1", 1496 "SampleAfterValue": "100000", 1497 "UMask": "0x1" 1498 }, 1499 { 1500 "BriefDescription": "All offcore writebacks", 1501 "Counter": "2", 1502 "EventCode": "0xB7", 1503 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1504 "MSRIndex": "0x1A6", 1505 "MSRValue": "0xFF08", 1506 "Offcore": "1", 1507 "SampleAfterValue": "100000", 1508 "UMask": "0x1" 1509 }, 1510 { 1511 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1512 "Counter": "2", 1513 "EventCode": "0xB7", 1514 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1515 "MSRIndex": "0x1A6", 1516 "MSRValue": "0x8008", 1517 "Offcore": "1", 1518 "SampleAfterValue": "100000", 1519 "UMask": "0x1" 1520 }, 1521 { 1522 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1523 "Counter": "2", 1524 "EventCode": "0xB7", 1525 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1526 "MSRIndex": "0x1A6", 1527 "MSRValue": "0x108", 1528 "Offcore": "1", 1529 "SampleAfterValue": "100000", 1530 "UMask": "0x1" 1531 }, 1532 { 1533 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1534 "Counter": "2", 1535 "EventCode": "0xB7", 1536 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1537 "MSRIndex": "0x1A6", 1538 "MSRValue": "0x408", 1539 "Offcore": "1", 1540 "SampleAfterValue": "100000", 1541 "UMask": "0x1" 1542 }, 1543 { 1544 "BriefDescription": "Offcore writebacks to the LLC", 1545 "Counter": "2", 1546 "EventCode": "0xB7", 1547 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1548 "MSRIndex": "0x1A6", 1549 "MSRValue": "0x708", 1550 "Offcore": "1", 1551 "SampleAfterValue": "100000", 1552 "UMask": "0x1" 1553 }, 1554 { 1555 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1556 "Counter": "2", 1557 "EventCode": "0xB7", 1558 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1559 "MSRIndex": "0x1A6", 1560 "MSRValue": "0x4708", 1561 "Offcore": "1", 1562 "SampleAfterValue": "100000", 1563 "UMask": "0x1" 1564 }, 1565 { 1566 "BriefDescription": "Offcore writebacks to a remote cache", 1567 "Counter": "2", 1568 "EventCode": "0xB7", 1569 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1570 "MSRIndex": "0x1A6", 1571 "MSRValue": "0x1808", 1572 "Offcore": "1", 1573 "SampleAfterValue": "100000", 1574 "UMask": "0x1" 1575 }, 1576 { 1577 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1578 "Counter": "2", 1579 "EventCode": "0xB7", 1580 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1581 "MSRIndex": "0x1A6", 1582 "MSRValue": "0x3808", 1583 "Offcore": "1", 1584 "SampleAfterValue": "100000", 1585 "UMask": "0x1" 1586 }, 1587 { 1588 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1589 "Counter": "2", 1590 "EventCode": "0xB7", 1591 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1592 "MSRIndex": "0x1A6", 1593 "MSRValue": "0x1008", 1594 "Offcore": "1", 1595 "SampleAfterValue": "100000", 1596 "UMask": "0x1" 1597 }, 1598 { 1599 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1600 "Counter": "2", 1601 "EventCode": "0xB7", 1602 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1603 "MSRIndex": "0x1A6", 1604 "MSRValue": "0x808", 1605 "Offcore": "1", 1606 "SampleAfterValue": "100000", 1607 "UMask": "0x1" 1608 }, 1609 { 1610 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1611 "Counter": "2", 1612 "EventCode": "0xB7", 1613 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1614 "MSRIndex": "0x1A6", 1615 "MSRValue": "0x7F77", 1616 "Offcore": "1", 1617 "SampleAfterValue": "100000", 1618 "UMask": "0x1" 1619 }, 1620 { 1621 "BriefDescription": "All offcore code or data read requests", 1622 "Counter": "2", 1623 "EventCode": "0xB7", 1624 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1625 "MSRIndex": "0x1A6", 1626 "MSRValue": "0xFF77", 1627 "Offcore": "1", 1628 "SampleAfterValue": "100000", 1629 "UMask": "0x1" 1630 }, 1631 { 1632 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1633 "Counter": "2", 1634 "EventCode": "0xB7", 1635 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1636 "MSRIndex": "0x1A6", 1637 "MSRValue": "0x8077", 1638 "Offcore": "1", 1639 "SampleAfterValue": "100000", 1640 "UMask": "0x1" 1641 }, 1642 { 1643 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1644 "Counter": "2", 1645 "EventCode": "0xB7", 1646 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1647 "MSRIndex": "0x1A6", 1648 "MSRValue": "0x177", 1649 "Offcore": "1", 1650 "SampleAfterValue": "100000", 1651 "UMask": "0x1" 1652 }, 1653 { 1654 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1655 "Counter": "2", 1656 "EventCode": "0xB7", 1657 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1658 "MSRIndex": "0x1A6", 1659 "MSRValue": "0x277", 1660 "Offcore": "1", 1661 "SampleAfterValue": "100000", 1662 "UMask": "0x1" 1663 }, 1664 { 1665 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1666 "Counter": "2", 1667 "EventCode": "0xB7", 1668 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1669 "MSRIndex": "0x1A6", 1670 "MSRValue": "0x477", 1671 "Offcore": "1", 1672 "SampleAfterValue": "100000", 1673 "UMask": "0x1" 1674 }, 1675 { 1676 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1677 "Counter": "2", 1678 "EventCode": "0xB7", 1679 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1680 "MSRIndex": "0x1A6", 1681 "MSRValue": "0x777", 1682 "Offcore": "1", 1683 "SampleAfterValue": "100000", 1684 "UMask": "0x1" 1685 }, 1686 { 1687 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1688 "Counter": "2", 1689 "EventCode": "0xB7", 1690 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1691 "MSRIndex": "0x1A6", 1692 "MSRValue": "0x4777", 1693 "Offcore": "1", 1694 "SampleAfterValue": "100000", 1695 "UMask": "0x1" 1696 }, 1697 { 1698 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1699 "Counter": "2", 1700 "EventCode": "0xB7", 1701 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1702 "MSRIndex": "0x1A6", 1703 "MSRValue": "0x1877", 1704 "Offcore": "1", 1705 "SampleAfterValue": "100000", 1706 "UMask": "0x1" 1707 }, 1708 { 1709 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1710 "Counter": "2", 1711 "EventCode": "0xB7", 1712 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1713 "MSRIndex": "0x1A6", 1714 "MSRValue": "0x3877", 1715 "Offcore": "1", 1716 "SampleAfterValue": "100000", 1717 "UMask": "0x1" 1718 }, 1719 { 1720 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1721 "Counter": "2", 1722 "EventCode": "0xB7", 1723 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1724 "MSRIndex": "0x1A6", 1725 "MSRValue": "0x1077", 1726 "Offcore": "1", 1727 "SampleAfterValue": "100000", 1728 "UMask": "0x1" 1729 }, 1730 { 1731 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1732 "Counter": "2", 1733 "EventCode": "0xB7", 1734 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1735 "MSRIndex": "0x1A6", 1736 "MSRValue": "0x877", 1737 "Offcore": "1", 1738 "SampleAfterValue": "100000", 1739 "UMask": "0x1" 1740 }, 1741 { 1742 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1743 "Counter": "2", 1744 "EventCode": "0xB7", 1745 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1746 "MSRIndex": "0x1A6", 1747 "MSRValue": "0x7F33", 1748 "Offcore": "1", 1749 "SampleAfterValue": "100000", 1750 "UMask": "0x1" 1751 }, 1752 { 1753 "BriefDescription": "Offcore request = all data, response = any location", 1754 "Counter": "2", 1755 "EventCode": "0xB7", 1756 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1757 "MSRIndex": "0x1A6", 1758 "MSRValue": "0xFF33", 1759 "Offcore": "1", 1760 "SampleAfterValue": "100000", 1761 "UMask": "0x1" 1762 }, 1763 { 1764 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", 1765 "Counter": "2", 1766 "EventCode": "0xB7", 1767 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1768 "MSRIndex": "0x1A6", 1769 "MSRValue": "0x8033", 1770 "Offcore": "1", 1771 "SampleAfterValue": "100000", 1772 "UMask": "0x1" 1773 }, 1774 { 1775 "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", 1776 "Counter": "2", 1777 "EventCode": "0xB7", 1778 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1779 "MSRIndex": "0x1A6", 1780 "MSRValue": "0x133", 1781 "Offcore": "1", 1782 "SampleAfterValue": "100000", 1783 "UMask": "0x1" 1784 }, 1785 { 1786 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", 1787 "Counter": "2", 1788 "EventCode": "0xB7", 1789 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1790 "MSRIndex": "0x1A6", 1791 "MSRValue": "0x233", 1792 "Offcore": "1", 1793 "SampleAfterValue": "100000", 1794 "UMask": "0x1" 1795 }, 1796 { 1797 "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", 1798 "Counter": "2", 1799 "EventCode": "0xB7", 1800 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1801 "MSRIndex": "0x1A6", 1802 "MSRValue": "0x433", 1803 "Offcore": "1", 1804 "SampleAfterValue": "100000", 1805 "UMask": "0x1" 1806 }, 1807 { 1808 "BriefDescription": "Offcore request = all data, response = local cache", 1809 "Counter": "2", 1810 "EventCode": "0xB7", 1811 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1812 "MSRIndex": "0x1A6", 1813 "MSRValue": "0x733", 1814 "Offcore": "1", 1815 "SampleAfterValue": "100000", 1816 "UMask": "0x1" 1817 }, 1818 { 1819 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1820 "Counter": "2", 1821 "EventCode": "0xB7", 1822 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1823 "MSRIndex": "0x1A6", 1824 "MSRValue": "0x4733", 1825 "Offcore": "1", 1826 "SampleAfterValue": "100000", 1827 "UMask": "0x1" 1828 }, 1829 { 1830 "BriefDescription": "Offcore request = all data, response = remote cache", 1831 "Counter": "2", 1832 "EventCode": "0xB7", 1833 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1834 "MSRIndex": "0x1A6", 1835 "MSRValue": "0x1833", 1836 "Offcore": "1", 1837 "SampleAfterValue": "100000", 1838 "UMask": "0x1" 1839 }, 1840 { 1841 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1842 "Counter": "2", 1843 "EventCode": "0xB7", 1844 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1845 "MSRIndex": "0x1A6", 1846 "MSRValue": "0x3833", 1847 "Offcore": "1", 1848 "SampleAfterValue": "100000", 1849 "UMask": "0x1" 1850 }, 1851 { 1852 "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache", 1853 "Counter": "2", 1854 "EventCode": "0xB7", 1855 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1856 "MSRIndex": "0x1A6", 1857 "MSRValue": "0x1033", 1858 "Offcore": "1", 1859 "SampleAfterValue": "100000", 1860 "UMask": "0x1" 1861 }, 1862 { 1863 "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", 1864 "Counter": "2", 1865 "EventCode": "0xB7", 1866 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1867 "MSRIndex": "0x1A6", 1868 "MSRValue": "0x833", 1869 "Offcore": "1", 1870 "SampleAfterValue": "100000", 1871 "UMask": "0x1" 1872 }, 1873 { 1874 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1875 "Counter": "2", 1876 "EventCode": "0xB7", 1877 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1878 "MSRIndex": "0x1A6", 1879 "MSRValue": "0x7F03", 1880 "Offcore": "1", 1881 "SampleAfterValue": "100000", 1882 "UMask": "0x1" 1883 }, 1884 { 1885 "BriefDescription": "All offcore demand data requests", 1886 "Counter": "2", 1887 "EventCode": "0xB7", 1888 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1889 "MSRIndex": "0x1A6", 1890 "MSRValue": "0xFF03", 1891 "Offcore": "1", 1892 "SampleAfterValue": "100000", 1893 "UMask": "0x1" 1894 }, 1895 { 1896 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1897 "Counter": "2", 1898 "EventCode": "0xB7", 1899 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1900 "MSRIndex": "0x1A6", 1901 "MSRValue": "0x8003", 1902 "Offcore": "1", 1903 "SampleAfterValue": "100000", 1904 "UMask": "0x1" 1905 }, 1906 { 1907 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1908 "Counter": "2", 1909 "EventCode": "0xB7", 1910 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1911 "MSRIndex": "0x1A6", 1912 "MSRValue": "0x103", 1913 "Offcore": "1", 1914 "SampleAfterValue": "100000", 1915 "UMask": "0x1" 1916 }, 1917 { 1918 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1919 "Counter": "2", 1920 "EventCode": "0xB7", 1921 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1922 "MSRIndex": "0x1A6", 1923 "MSRValue": "0x203", 1924 "Offcore": "1", 1925 "SampleAfterValue": "100000", 1926 "UMask": "0x1" 1927 }, 1928 { 1929 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1930 "Counter": "2", 1931 "EventCode": "0xB7", 1932 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1933 "MSRIndex": "0x1A6", 1934 "MSRValue": "0x403", 1935 "Offcore": "1", 1936 "SampleAfterValue": "100000", 1937 "UMask": "0x1" 1938 }, 1939 { 1940 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1941 "Counter": "2", 1942 "EventCode": "0xB7", 1943 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1944 "MSRIndex": "0x1A6", 1945 "MSRValue": "0x703", 1946 "Offcore": "1", 1947 "SampleAfterValue": "100000", 1948 "UMask": "0x1" 1949 }, 1950 { 1951 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1952 "Counter": "2", 1953 "EventCode": "0xB7", 1954 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1955 "MSRIndex": "0x1A6", 1956 "MSRValue": "0x4703", 1957 "Offcore": "1", 1958 "SampleAfterValue": "100000", 1959 "UMask": "0x1" 1960 }, 1961 { 1962 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1963 "Counter": "2", 1964 "EventCode": "0xB7", 1965 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1966 "MSRIndex": "0x1A6", 1967 "MSRValue": "0x1803", 1968 "Offcore": "1", 1969 "SampleAfterValue": "100000", 1970 "UMask": "0x1" 1971 }, 1972 { 1973 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1974 "Counter": "2", 1975 "EventCode": "0xB7", 1976 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1977 "MSRIndex": "0x1A6", 1978 "MSRValue": "0x3803", 1979 "Offcore": "1", 1980 "SampleAfterValue": "100000", 1981 "UMask": "0x1" 1982 }, 1983 { 1984 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1985 "Counter": "2", 1986 "EventCode": "0xB7", 1987 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1988 "MSRIndex": "0x1A6", 1989 "MSRValue": "0x1003", 1990 "Offcore": "1", 1991 "SampleAfterValue": "100000", 1992 "UMask": "0x1" 1993 }, 1994 { 1995 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1996 "Counter": "2", 1997 "EventCode": "0xB7", 1998 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1999 "MSRIndex": "0x1A6", 2000 "MSRValue": "0x803", 2001 "Offcore": "1", 2002 "SampleAfterValue": "100000", 2003 "UMask": "0x1" 2004 }, 2005 { 2006 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 2007 "Counter": "2", 2008 "EventCode": "0xB7", 2009 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 2010 "MSRIndex": "0x1A6", 2011 "MSRValue": "0x7F01", 2012 "Offcore": "1", 2013 "SampleAfterValue": "100000", 2014 "UMask": "0x1" 2015 }, 2016 { 2017 "BriefDescription": "All offcore demand data reads", 2018 "Counter": "2", 2019 "EventCode": "0xB7", 2020 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 2021 "MSRIndex": "0x1A6", 2022 "MSRValue": "0xFF01", 2023 "Offcore": "1", 2024 "SampleAfterValue": "100000", 2025 "UMask": "0x1" 2026 }, 2027 { 2028 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 2029 "Counter": "2", 2030 "EventCode": "0xB7", 2031 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 2032 "MSRIndex": "0x1A6", 2033 "MSRValue": "0x8001", 2034 "Offcore": "1", 2035 "SampleAfterValue": "100000", 2036 "UMask": "0x1" 2037 }, 2038 { 2039 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 2040 "Counter": "2", 2041 "EventCode": "0xB7", 2042 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2043 "MSRIndex": "0x1A6", 2044 "MSRValue": "0x101", 2045 "Offcore": "1", 2046 "SampleAfterValue": "100000", 2047 "UMask": "0x1" 2048 }, 2049 { 2050 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 2051 "Counter": "2", 2052 "EventCode": "0xB7", 2053 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2054 "MSRIndex": "0x1A6", 2055 "MSRValue": "0x201", 2056 "Offcore": "1", 2057 "SampleAfterValue": "100000", 2058 "UMask": "0x1" 2059 }, 2060 { 2061 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 2062 "Counter": "2", 2063 "EventCode": "0xB7", 2064 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2065 "MSRIndex": "0x1A6", 2066 "MSRValue": "0x401", 2067 "Offcore": "1", 2068 "SampleAfterValue": "100000", 2069 "UMask": "0x1" 2070 }, 2071 { 2072 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 2073 "Counter": "2", 2074 "EventCode": "0xB7", 2075 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 2076 "MSRIndex": "0x1A6", 2077 "MSRValue": "0x701", 2078 "Offcore": "1", 2079 "SampleAfterValue": "100000", 2080 "UMask": "0x1" 2081 }, 2082 { 2083 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 2084 "Counter": "2", 2085 "EventCode": "0xB7", 2086 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 2087 "MSRIndex": "0x1A6", 2088 "MSRValue": "0x4701", 2089 "Offcore": "1", 2090 "SampleAfterValue": "100000", 2091 "UMask": "0x1" 2092 }, 2093 { 2094 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 2095 "Counter": "2", 2096 "EventCode": "0xB7", 2097 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 2098 "MSRIndex": "0x1A6", 2099 "MSRValue": "0x1801", 2100 "Offcore": "1", 2101 "SampleAfterValue": "100000", 2102 "UMask": "0x1" 2103 }, 2104 { 2105 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 2106 "Counter": "2", 2107 "EventCode": "0xB7", 2108 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 2109 "MSRIndex": "0x1A6", 2110 "MSRValue": "0x3801", 2111 "Offcore": "1", 2112 "SampleAfterValue": "100000", 2113 "UMask": "0x1" 2114 }, 2115 { 2116 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 2117 "Counter": "2", 2118 "EventCode": "0xB7", 2119 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 2120 "MSRIndex": "0x1A6", 2121 "MSRValue": "0x1001", 2122 "Offcore": "1", 2123 "SampleAfterValue": "100000", 2124 "UMask": "0x1" 2125 }, 2126 { 2127 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 2128 "Counter": "2", 2129 "EventCode": "0xB7", 2130 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 2131 "MSRIndex": "0x1A6", 2132 "MSRValue": "0x801", 2133 "Offcore": "1", 2134 "SampleAfterValue": "100000", 2135 "UMask": "0x1" 2136 }, 2137 { 2138 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 2139 "Counter": "2", 2140 "EventCode": "0xB7", 2141 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2142 "MSRIndex": "0x1A6", 2143 "MSRValue": "0x7F04", 2144 "Offcore": "1", 2145 "SampleAfterValue": "100000", 2146 "UMask": "0x1" 2147 }, 2148 { 2149 "BriefDescription": "All offcore demand code reads", 2150 "Counter": "2", 2151 "EventCode": "0xB7", 2152 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2153 "MSRIndex": "0x1A6", 2154 "MSRValue": "0xFF04", 2155 "Offcore": "1", 2156 "SampleAfterValue": "100000", 2157 "UMask": "0x1" 2158 }, 2159 { 2160 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2161 "Counter": "2", 2162 "EventCode": "0xB7", 2163 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2164 "MSRIndex": "0x1A6", 2165 "MSRValue": "0x8004", 2166 "Offcore": "1", 2167 "SampleAfterValue": "100000", 2168 "UMask": "0x1" 2169 }, 2170 { 2171 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2172 "Counter": "2", 2173 "EventCode": "0xB7", 2174 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2175 "MSRIndex": "0x1A6", 2176 "MSRValue": "0x104", 2177 "Offcore": "1", 2178 "SampleAfterValue": "100000", 2179 "UMask": "0x1" 2180 }, 2181 { 2182 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2183 "Counter": "2", 2184 "EventCode": "0xB7", 2185 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2186 "MSRIndex": "0x1A6", 2187 "MSRValue": "0x204", 2188 "Offcore": "1", 2189 "SampleAfterValue": "100000", 2190 "UMask": "0x1" 2191 }, 2192 { 2193 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2194 "Counter": "2", 2195 "EventCode": "0xB7", 2196 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2197 "MSRIndex": "0x1A6", 2198 "MSRValue": "0x404", 2199 "Offcore": "1", 2200 "SampleAfterValue": "100000", 2201 "UMask": "0x1" 2202 }, 2203 { 2204 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2205 "Counter": "2", 2206 "EventCode": "0xB7", 2207 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2208 "MSRIndex": "0x1A6", 2209 "MSRValue": "0x704", 2210 "Offcore": "1", 2211 "SampleAfterValue": "100000", 2212 "UMask": "0x1" 2213 }, 2214 { 2215 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2216 "Counter": "2", 2217 "EventCode": "0xB7", 2218 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2219 "MSRIndex": "0x1A6", 2220 "MSRValue": "0x4704", 2221 "Offcore": "1", 2222 "SampleAfterValue": "100000", 2223 "UMask": "0x1" 2224 }, 2225 { 2226 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2227 "Counter": "2", 2228 "EventCode": "0xB7", 2229 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2230 "MSRIndex": "0x1A6", 2231 "MSRValue": "0x1804", 2232 "Offcore": "1", 2233 "SampleAfterValue": "100000", 2234 "UMask": "0x1" 2235 }, 2236 { 2237 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2238 "Counter": "2", 2239 "EventCode": "0xB7", 2240 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2241 "MSRIndex": "0x1A6", 2242 "MSRValue": "0x3804", 2243 "Offcore": "1", 2244 "SampleAfterValue": "100000", 2245 "UMask": "0x1" 2246 }, 2247 { 2248 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2249 "Counter": "2", 2250 "EventCode": "0xB7", 2251 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2252 "MSRIndex": "0x1A6", 2253 "MSRValue": "0x1004", 2254 "Offcore": "1", 2255 "SampleAfterValue": "100000", 2256 "UMask": "0x1" 2257 }, 2258 { 2259 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2260 "Counter": "2", 2261 "EventCode": "0xB7", 2262 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2263 "MSRIndex": "0x1A6", 2264 "MSRValue": "0x804", 2265 "Offcore": "1", 2266 "SampleAfterValue": "100000", 2267 "UMask": "0x1" 2268 }, 2269 { 2270 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2271 "Counter": "2", 2272 "EventCode": "0xB7", 2273 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2274 "MSRIndex": "0x1A6", 2275 "MSRValue": "0x7F02", 2276 "Offcore": "1", 2277 "SampleAfterValue": "100000", 2278 "UMask": "0x1" 2279 }, 2280 { 2281 "BriefDescription": "All offcore demand RFO requests", 2282 "Counter": "2", 2283 "EventCode": "0xB7", 2284 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2285 "MSRIndex": "0x1A6", 2286 "MSRValue": "0xFF02", 2287 "Offcore": "1", 2288 "SampleAfterValue": "100000", 2289 "UMask": "0x1" 2290 }, 2291 { 2292 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2293 "Counter": "2", 2294 "EventCode": "0xB7", 2295 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2296 "MSRIndex": "0x1A6", 2297 "MSRValue": "0x8002", 2298 "Offcore": "1", 2299 "SampleAfterValue": "100000", 2300 "UMask": "0x1" 2301 }, 2302 { 2303 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2304 "Counter": "2", 2305 "EventCode": "0xB7", 2306 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2307 "MSRIndex": "0x1A6", 2308 "MSRValue": "0x102", 2309 "Offcore": "1", 2310 "SampleAfterValue": "100000", 2311 "UMask": "0x1" 2312 }, 2313 { 2314 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2315 "Counter": "2", 2316 "EventCode": "0xB7", 2317 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2318 "MSRIndex": "0x1A6", 2319 "MSRValue": "0x202", 2320 "Offcore": "1", 2321 "SampleAfterValue": "100000", 2322 "UMask": "0x1" 2323 }, 2324 { 2325 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2326 "Counter": "2", 2327 "EventCode": "0xB7", 2328 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2329 "MSRIndex": "0x1A6", 2330 "MSRValue": "0x402", 2331 "Offcore": "1", 2332 "SampleAfterValue": "100000", 2333 "UMask": "0x1" 2334 }, 2335 { 2336 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2337 "Counter": "2", 2338 "EventCode": "0xB7", 2339 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2340 "MSRIndex": "0x1A6", 2341 "MSRValue": "0x702", 2342 "Offcore": "1", 2343 "SampleAfterValue": "100000", 2344 "UMask": "0x1" 2345 }, 2346 { 2347 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2348 "Counter": "2", 2349 "EventCode": "0xB7", 2350 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2351 "MSRIndex": "0x1A6", 2352 "MSRValue": "0x4702", 2353 "Offcore": "1", 2354 "SampleAfterValue": "100000", 2355 "UMask": "0x1" 2356 }, 2357 { 2358 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2359 "Counter": "2", 2360 "EventCode": "0xB7", 2361 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2362 "MSRIndex": "0x1A6", 2363 "MSRValue": "0x1802", 2364 "Offcore": "1", 2365 "SampleAfterValue": "100000", 2366 "UMask": "0x1" 2367 }, 2368 { 2369 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2370 "Counter": "2", 2371 "EventCode": "0xB7", 2372 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2373 "MSRIndex": "0x1A6", 2374 "MSRValue": "0x3802", 2375 "Offcore": "1", 2376 "SampleAfterValue": "100000", 2377 "UMask": "0x1" 2378 }, 2379 { 2380 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2381 "Counter": "2", 2382 "EventCode": "0xB7", 2383 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2384 "MSRIndex": "0x1A6", 2385 "MSRValue": "0x1002", 2386 "Offcore": "1", 2387 "SampleAfterValue": "100000", 2388 "UMask": "0x1" 2389 }, 2390 { 2391 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2392 "Counter": "2", 2393 "EventCode": "0xB7", 2394 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2395 "MSRIndex": "0x1A6", 2396 "MSRValue": "0x802", 2397 "Offcore": "1", 2398 "SampleAfterValue": "100000", 2399 "UMask": "0x1" 2400 }, 2401 { 2402 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2403 "Counter": "2", 2404 "EventCode": "0xB7", 2405 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2406 "MSRIndex": "0x1A6", 2407 "MSRValue": "0x7F80", 2408 "Offcore": "1", 2409 "SampleAfterValue": "100000", 2410 "UMask": "0x1" 2411 }, 2412 { 2413 "BriefDescription": "All offcore other requests", 2414 "Counter": "2", 2415 "EventCode": "0xB7", 2416 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2417 "MSRIndex": "0x1A6", 2418 "MSRValue": "0xFF80", 2419 "Offcore": "1", 2420 "SampleAfterValue": "100000", 2421 "UMask": "0x1" 2422 }, 2423 { 2424 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2425 "Counter": "2", 2426 "EventCode": "0xB7", 2427 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2428 "MSRIndex": "0x1A6", 2429 "MSRValue": "0x8080", 2430 "Offcore": "1", 2431 "SampleAfterValue": "100000", 2432 "UMask": "0x1" 2433 }, 2434 { 2435 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2436 "Counter": "2", 2437 "EventCode": "0xB7", 2438 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2439 "MSRIndex": "0x1A6", 2440 "MSRValue": "0x180", 2441 "Offcore": "1", 2442 "SampleAfterValue": "100000", 2443 "UMask": "0x1" 2444 }, 2445 { 2446 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2447 "Counter": "2", 2448 "EventCode": "0xB7", 2449 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2450 "MSRIndex": "0x1A6", 2451 "MSRValue": "0x280", 2452 "Offcore": "1", 2453 "SampleAfterValue": "100000", 2454 "UMask": "0x1" 2455 }, 2456 { 2457 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2458 "Counter": "2", 2459 "EventCode": "0xB7", 2460 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2461 "MSRIndex": "0x1A6", 2462 "MSRValue": "0x480", 2463 "Offcore": "1", 2464 "SampleAfterValue": "100000", 2465 "UMask": "0x1" 2466 }, 2467 { 2468 "BriefDescription": "Offcore other requests satisfied by the LLC", 2469 "Counter": "2", 2470 "EventCode": "0xB7", 2471 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2472 "MSRIndex": "0x1A6", 2473 "MSRValue": "0x780", 2474 "Offcore": "1", 2475 "SampleAfterValue": "100000", 2476 "UMask": "0x1" 2477 }, 2478 { 2479 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2480 "Counter": "2", 2481 "EventCode": "0xB7", 2482 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2483 "MSRIndex": "0x1A6", 2484 "MSRValue": "0x4780", 2485 "Offcore": "1", 2486 "SampleAfterValue": "100000", 2487 "UMask": "0x1" 2488 }, 2489 { 2490 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2491 "Counter": "2", 2492 "EventCode": "0xB7", 2493 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2494 "MSRIndex": "0x1A6", 2495 "MSRValue": "0x1880", 2496 "Offcore": "1", 2497 "SampleAfterValue": "100000", 2498 "UMask": "0x1" 2499 }, 2500 { 2501 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2502 "Counter": "2", 2503 "EventCode": "0xB7", 2504 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2505 "MSRIndex": "0x1A6", 2506 "MSRValue": "0x3880", 2507 "Offcore": "1", 2508 "SampleAfterValue": "100000", 2509 "UMask": "0x1" 2510 }, 2511 { 2512 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2513 "Counter": "2", 2514 "EventCode": "0xB7", 2515 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2516 "MSRIndex": "0x1A6", 2517 "MSRValue": "0x1080", 2518 "Offcore": "1", 2519 "SampleAfterValue": "100000", 2520 "UMask": "0x1" 2521 }, 2522 { 2523 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2524 "Counter": "2", 2525 "EventCode": "0xB7", 2526 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2527 "MSRIndex": "0x1A6", 2528 "MSRValue": "0x880", 2529 "Offcore": "1", 2530 "SampleAfterValue": "100000", 2531 "UMask": "0x1" 2532 }, 2533 { 2534 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2535 "Counter": "2", 2536 "EventCode": "0xB7", 2537 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2538 "MSRIndex": "0x1A6", 2539 "MSRValue": "0x7F30", 2540 "Offcore": "1", 2541 "SampleAfterValue": "100000", 2542 "UMask": "0x1" 2543 }, 2544 { 2545 "BriefDescription": "All offcore prefetch data requests", 2546 "Counter": "2", 2547 "EventCode": "0xB7", 2548 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2549 "MSRIndex": "0x1A6", 2550 "MSRValue": "0xFF30", 2551 "Offcore": "1", 2552 "SampleAfterValue": "100000", 2553 "UMask": "0x1" 2554 }, 2555 { 2556 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2557 "Counter": "2", 2558 "EventCode": "0xB7", 2559 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2560 "MSRIndex": "0x1A6", 2561 "MSRValue": "0x8030", 2562 "Offcore": "1", 2563 "SampleAfterValue": "100000", 2564 "UMask": "0x1" 2565 }, 2566 { 2567 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2568 "Counter": "2", 2569 "EventCode": "0xB7", 2570 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2571 "MSRIndex": "0x1A6", 2572 "MSRValue": "0x130", 2573 "Offcore": "1", 2574 "SampleAfterValue": "100000", 2575 "UMask": "0x1" 2576 }, 2577 { 2578 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2579 "Counter": "2", 2580 "EventCode": "0xB7", 2581 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2582 "MSRIndex": "0x1A6", 2583 "MSRValue": "0x230", 2584 "Offcore": "1", 2585 "SampleAfterValue": "100000", 2586 "UMask": "0x1" 2587 }, 2588 { 2589 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2590 "Counter": "2", 2591 "EventCode": "0xB7", 2592 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2593 "MSRIndex": "0x1A6", 2594 "MSRValue": "0x430", 2595 "Offcore": "1", 2596 "SampleAfterValue": "100000", 2597 "UMask": "0x1" 2598 }, 2599 { 2600 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2601 "Counter": "2", 2602 "EventCode": "0xB7", 2603 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2604 "MSRIndex": "0x1A6", 2605 "MSRValue": "0x730", 2606 "Offcore": "1", 2607 "SampleAfterValue": "100000", 2608 "UMask": "0x1" 2609 }, 2610 { 2611 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2612 "Counter": "2", 2613 "EventCode": "0xB7", 2614 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2615 "MSRIndex": "0x1A6", 2616 "MSRValue": "0x4730", 2617 "Offcore": "1", 2618 "SampleAfterValue": "100000", 2619 "UMask": "0x1" 2620 }, 2621 { 2622 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2623 "Counter": "2", 2624 "EventCode": "0xB7", 2625 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2626 "MSRIndex": "0x1A6", 2627 "MSRValue": "0x1830", 2628 "Offcore": "1", 2629 "SampleAfterValue": "100000", 2630 "UMask": "0x1" 2631 }, 2632 { 2633 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2634 "Counter": "2", 2635 "EventCode": "0xB7", 2636 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2637 "MSRIndex": "0x1A6", 2638 "MSRValue": "0x3830", 2639 "Offcore": "1", 2640 "SampleAfterValue": "100000", 2641 "UMask": "0x1" 2642 }, 2643 { 2644 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2645 "Counter": "2", 2646 "EventCode": "0xB7", 2647 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2648 "MSRIndex": "0x1A6", 2649 "MSRValue": "0x1030", 2650 "Offcore": "1", 2651 "SampleAfterValue": "100000", 2652 "UMask": "0x1" 2653 }, 2654 { 2655 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2656 "Counter": "2", 2657 "EventCode": "0xB7", 2658 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2659 "MSRIndex": "0x1A6", 2660 "MSRValue": "0x830", 2661 "Offcore": "1", 2662 "SampleAfterValue": "100000", 2663 "UMask": "0x1" 2664 }, 2665 { 2666 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2667 "Counter": "2", 2668 "EventCode": "0xB7", 2669 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2670 "MSRIndex": "0x1A6", 2671 "MSRValue": "0x7F10", 2672 "Offcore": "1", 2673 "SampleAfterValue": "100000", 2674 "UMask": "0x1" 2675 }, 2676 { 2677 "BriefDescription": "All offcore prefetch data reads", 2678 "Counter": "2", 2679 "EventCode": "0xB7", 2680 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2681 "MSRIndex": "0x1A6", 2682 "MSRValue": "0xFF10", 2683 "Offcore": "1", 2684 "SampleAfterValue": "100000", 2685 "UMask": "0x1" 2686 }, 2687 { 2688 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2689 "Counter": "2", 2690 "EventCode": "0xB7", 2691 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2692 "MSRIndex": "0x1A6", 2693 "MSRValue": "0x8010", 2694 "Offcore": "1", 2695 "SampleAfterValue": "100000", 2696 "UMask": "0x1" 2697 }, 2698 { 2699 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2700 "Counter": "2", 2701 "EventCode": "0xB7", 2702 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2703 "MSRIndex": "0x1A6", 2704 "MSRValue": "0x110", 2705 "Offcore": "1", 2706 "SampleAfterValue": "100000", 2707 "UMask": "0x1" 2708 }, 2709 { 2710 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2711 "Counter": "2", 2712 "EventCode": "0xB7", 2713 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2714 "MSRIndex": "0x1A6", 2715 "MSRValue": "0x210", 2716 "Offcore": "1", 2717 "SampleAfterValue": "100000", 2718 "UMask": "0x1" 2719 }, 2720 { 2721 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2722 "Counter": "2", 2723 "EventCode": "0xB7", 2724 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2725 "MSRIndex": "0x1A6", 2726 "MSRValue": "0x410", 2727 "Offcore": "1", 2728 "SampleAfterValue": "100000", 2729 "UMask": "0x1" 2730 }, 2731 { 2732 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2733 "Counter": "2", 2734 "EventCode": "0xB7", 2735 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2736 "MSRIndex": "0x1A6", 2737 "MSRValue": "0x710", 2738 "Offcore": "1", 2739 "SampleAfterValue": "100000", 2740 "UMask": "0x1" 2741 }, 2742 { 2743 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2744 "Counter": "2", 2745 "EventCode": "0xB7", 2746 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2747 "MSRIndex": "0x1A6", 2748 "MSRValue": "0x4710", 2749 "Offcore": "1", 2750 "SampleAfterValue": "100000", 2751 "UMask": "0x1" 2752 }, 2753 { 2754 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2755 "Counter": "2", 2756 "EventCode": "0xB7", 2757 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2758 "MSRIndex": "0x1A6", 2759 "MSRValue": "0x1810", 2760 "Offcore": "1", 2761 "SampleAfterValue": "100000", 2762 "UMask": "0x1" 2763 }, 2764 { 2765 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2766 "Counter": "2", 2767 "EventCode": "0xB7", 2768 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2769 "MSRIndex": "0x1A6", 2770 "MSRValue": "0x3810", 2771 "Offcore": "1", 2772 "SampleAfterValue": "100000", 2773 "UMask": "0x1" 2774 }, 2775 { 2776 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2777 "Counter": "2", 2778 "EventCode": "0xB7", 2779 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2780 "MSRIndex": "0x1A6", 2781 "MSRValue": "0x1010", 2782 "Offcore": "1", 2783 "SampleAfterValue": "100000", 2784 "UMask": "0x1" 2785 }, 2786 { 2787 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2788 "Counter": "2", 2789 "EventCode": "0xB7", 2790 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2791 "MSRIndex": "0x1A6", 2792 "MSRValue": "0x810", 2793 "Offcore": "1", 2794 "SampleAfterValue": "100000", 2795 "UMask": "0x1" 2796 }, 2797 { 2798 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2799 "Counter": "2", 2800 "EventCode": "0xB7", 2801 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2802 "MSRIndex": "0x1A6", 2803 "MSRValue": "0x7F40", 2804 "Offcore": "1", 2805 "SampleAfterValue": "100000", 2806 "UMask": "0x1" 2807 }, 2808 { 2809 "BriefDescription": "All offcore prefetch code reads", 2810 "Counter": "2", 2811 "EventCode": "0xB7", 2812 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2813 "MSRIndex": "0x1A6", 2814 "MSRValue": "0xFF40", 2815 "Offcore": "1", 2816 "SampleAfterValue": "100000", 2817 "UMask": "0x1" 2818 }, 2819 { 2820 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2821 "Counter": "2", 2822 "EventCode": "0xB7", 2823 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2824 "MSRIndex": "0x1A6", 2825 "MSRValue": "0x8040", 2826 "Offcore": "1", 2827 "SampleAfterValue": "100000", 2828 "UMask": "0x1" 2829 }, 2830 { 2831 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2832 "Counter": "2", 2833 "EventCode": "0xB7", 2834 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2835 "MSRIndex": "0x1A6", 2836 "MSRValue": "0x140", 2837 "Offcore": "1", 2838 "SampleAfterValue": "100000", 2839 "UMask": "0x1" 2840 }, 2841 { 2842 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2843 "Counter": "2", 2844 "EventCode": "0xB7", 2845 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2846 "MSRIndex": "0x1A6", 2847 "MSRValue": "0x240", 2848 "Offcore": "1", 2849 "SampleAfterValue": "100000", 2850 "UMask": "0x1" 2851 }, 2852 { 2853 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2854 "Counter": "2", 2855 "EventCode": "0xB7", 2856 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2857 "MSRIndex": "0x1A6", 2858 "MSRValue": "0x440", 2859 "Offcore": "1", 2860 "SampleAfterValue": "100000", 2861 "UMask": "0x1" 2862 }, 2863 { 2864 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2865 "Counter": "2", 2866 "EventCode": "0xB7", 2867 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2868 "MSRIndex": "0x1A6", 2869 "MSRValue": "0x740", 2870 "Offcore": "1", 2871 "SampleAfterValue": "100000", 2872 "UMask": "0x1" 2873 }, 2874 { 2875 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2876 "Counter": "2", 2877 "EventCode": "0xB7", 2878 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2879 "MSRIndex": "0x1A6", 2880 "MSRValue": "0x4740", 2881 "Offcore": "1", 2882 "SampleAfterValue": "100000", 2883 "UMask": "0x1" 2884 }, 2885 { 2886 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2887 "Counter": "2", 2888 "EventCode": "0xB7", 2889 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2890 "MSRIndex": "0x1A6", 2891 "MSRValue": "0x1840", 2892 "Offcore": "1", 2893 "SampleAfterValue": "100000", 2894 "UMask": "0x1" 2895 }, 2896 { 2897 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2898 "Counter": "2", 2899 "EventCode": "0xB7", 2900 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2901 "MSRIndex": "0x1A6", 2902 "MSRValue": "0x3840", 2903 "Offcore": "1", 2904 "SampleAfterValue": "100000", 2905 "UMask": "0x1" 2906 }, 2907 { 2908 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2909 "Counter": "2", 2910 "EventCode": "0xB7", 2911 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2912 "MSRIndex": "0x1A6", 2913 "MSRValue": "0x1040", 2914 "Offcore": "1", 2915 "SampleAfterValue": "100000", 2916 "UMask": "0x1" 2917 }, 2918 { 2919 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2920 "Counter": "2", 2921 "EventCode": "0xB7", 2922 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2923 "MSRIndex": "0x1A6", 2924 "MSRValue": "0x840", 2925 "Offcore": "1", 2926 "SampleAfterValue": "100000", 2927 "UMask": "0x1" 2928 }, 2929 { 2930 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2931 "Counter": "2", 2932 "EventCode": "0xB7", 2933 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2934 "MSRIndex": "0x1A6", 2935 "MSRValue": "0x7F20", 2936 "Offcore": "1", 2937 "SampleAfterValue": "100000", 2938 "UMask": "0x1" 2939 }, 2940 { 2941 "BriefDescription": "All offcore prefetch RFO requests", 2942 "Counter": "2", 2943 "EventCode": "0xB7", 2944 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2945 "MSRIndex": "0x1A6", 2946 "MSRValue": "0xFF20", 2947 "Offcore": "1", 2948 "SampleAfterValue": "100000", 2949 "UMask": "0x1" 2950 }, 2951 { 2952 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2953 "Counter": "2", 2954 "EventCode": "0xB7", 2955 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2956 "MSRIndex": "0x1A6", 2957 "MSRValue": "0x8020", 2958 "Offcore": "1", 2959 "SampleAfterValue": "100000", 2960 "UMask": "0x1" 2961 }, 2962 { 2963 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2964 "Counter": "2", 2965 "EventCode": "0xB7", 2966 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2967 "MSRIndex": "0x1A6", 2968 "MSRValue": "0x120", 2969 "Offcore": "1", 2970 "SampleAfterValue": "100000", 2971 "UMask": "0x1" 2972 }, 2973 { 2974 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2975 "Counter": "2", 2976 "EventCode": "0xB7", 2977 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2978 "MSRIndex": "0x1A6", 2979 "MSRValue": "0x220", 2980 "Offcore": "1", 2981 "SampleAfterValue": "100000", 2982 "UMask": "0x1" 2983 }, 2984 { 2985 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2986 "Counter": "2", 2987 "EventCode": "0xB7", 2988 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2989 "MSRIndex": "0x1A6", 2990 "MSRValue": "0x420", 2991 "Offcore": "1", 2992 "SampleAfterValue": "100000", 2993 "UMask": "0x1" 2994 }, 2995 { 2996 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2997 "Counter": "2", 2998 "EventCode": "0xB7", 2999 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 3000 "MSRIndex": "0x1A6", 3001 "MSRValue": "0x720", 3002 "Offcore": "1", 3003 "SampleAfterValue": "100000", 3004 "UMask": "0x1" 3005 }, 3006 { 3007 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 3008 "Counter": "2", 3009 "EventCode": "0xB7", 3010 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 3011 "MSRIndex": "0x1A6", 3012 "MSRValue": "0x4720", 3013 "Offcore": "1", 3014 "SampleAfterValue": "100000", 3015 "UMask": "0x1" 3016 }, 3017 { 3018 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 3019 "Counter": "2", 3020 "EventCode": "0xB7", 3021 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 3022 "MSRIndex": "0x1A6", 3023 "MSRValue": "0x1820", 3024 "Offcore": "1", 3025 "SampleAfterValue": "100000", 3026 "UMask": "0x1" 3027 }, 3028 { 3029 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 3030 "Counter": "2", 3031 "EventCode": "0xB7", 3032 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 3033 "MSRIndex": "0x1A6", 3034 "MSRValue": "0x3820", 3035 "Offcore": "1", 3036 "SampleAfterValue": "100000", 3037 "UMask": "0x1" 3038 }, 3039 { 3040 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 3041 "Counter": "2", 3042 "EventCode": "0xB7", 3043 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 3044 "MSRIndex": "0x1A6", 3045 "MSRValue": "0x1020", 3046 "Offcore": "1", 3047 "SampleAfterValue": "100000", 3048 "UMask": "0x1" 3049 }, 3050 { 3051 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 3052 "Counter": "2", 3053 "EventCode": "0xB7", 3054 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 3055 "MSRIndex": "0x1A6", 3056 "MSRValue": "0x820", 3057 "Offcore": "1", 3058 "SampleAfterValue": "100000", 3059 "UMask": "0x1" 3060 }, 3061 { 3062 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 3063 "Counter": "2", 3064 "EventCode": "0xB7", 3065 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 3066 "MSRIndex": "0x1A6", 3067 "MSRValue": "0x7F70", 3068 "Offcore": "1", 3069 "SampleAfterValue": "100000", 3070 "UMask": "0x1" 3071 }, 3072 { 3073 "BriefDescription": "All offcore prefetch requests", 3074 "Counter": "2", 3075 "EventCode": "0xB7", 3076 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 3077 "MSRIndex": "0x1A6", 3078 "MSRValue": "0xFF70", 3079 "Offcore": "1", 3080 "SampleAfterValue": "100000", 3081 "UMask": "0x1" 3082 }, 3083 { 3084 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 3085 "Counter": "2", 3086 "EventCode": "0xB7", 3087 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 3088 "MSRIndex": "0x1A6", 3089 "MSRValue": "0x8070", 3090 "Offcore": "1", 3091 "SampleAfterValue": "100000", 3092 "UMask": "0x1" 3093 }, 3094 { 3095 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 3096 "Counter": "2", 3097 "EventCode": "0xB7", 3098 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 3099 "MSRIndex": "0x1A6", 3100 "MSRValue": "0x170", 3101 "Offcore": "1", 3102 "SampleAfterValue": "100000", 3103 "UMask": "0x1" 3104 }, 3105 { 3106 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 3107 "Counter": "2", 3108 "EventCode": "0xB7", 3109 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 3110 "MSRIndex": "0x1A6", 3111 "MSRValue": "0x270", 3112 "Offcore": "1", 3113 "SampleAfterValue": "100000", 3114 "UMask": "0x1" 3115 }, 3116 { 3117 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 3118 "Counter": "2", 3119 "EventCode": "0xB7", 3120 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 3121 "MSRIndex": "0x1A6", 3122 "MSRValue": "0x470", 3123 "Offcore": "1", 3124 "SampleAfterValue": "100000", 3125 "UMask": "0x1" 3126 }, 3127 { 3128 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 3129 "Counter": "2", 3130 "EventCode": "0xB7", 3131 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 3132 "MSRIndex": "0x1A6", 3133 "MSRValue": "0x770", 3134 "Offcore": "1", 3135 "SampleAfterValue": "100000", 3136 "UMask": "0x1" 3137 }, 3138 { 3139 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 3140 "Counter": "2", 3141 "EventCode": "0xB7", 3142 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 3143 "MSRIndex": "0x1A6", 3144 "MSRValue": "0x4770", 3145 "Offcore": "1", 3146 "SampleAfterValue": "100000", 3147 "UMask": "0x1" 3148 }, 3149 { 3150 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 3151 "Counter": "2", 3152 "EventCode": "0xB7", 3153 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 3154 "MSRIndex": "0x1A6", 3155 "MSRValue": "0x1870", 3156 "Offcore": "1", 3157 "SampleAfterValue": "100000", 3158 "UMask": "0x1" 3159 }, 3160 { 3161 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 3162 "Counter": "2", 3163 "EventCode": "0xB7", 3164 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 3165 "MSRIndex": "0x1A6", 3166 "MSRValue": "0x3870", 3167 "Offcore": "1", 3168 "SampleAfterValue": "100000", 3169 "UMask": "0x1" 3170 }, 3171 { 3172 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 3173 "Counter": "2", 3174 "EventCode": "0xB7", 3175 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 3176 "MSRIndex": "0x1A6", 3177 "MSRValue": "0x1070", 3178 "Offcore": "1", 3179 "SampleAfterValue": "100000", 3180 "UMask": "0x1" 3181 }, 3182 { 3183 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 3184 "Counter": "2", 3185 "EventCode": "0xB7", 3186 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 3187 "MSRIndex": "0x1A6", 3188 "MSRValue": "0x870", 3189 "Offcore": "1", 3190 "SampleAfterValue": "100000", 3191 "UMask": "0x1" 3192 }, 3193 { 3194 "BriefDescription": "Super Queue LRU hints sent to LLC", 3195 "Counter": "0,1,2,3", 3196 "EventCode": "0xF4", 3197 "EventName": "SQ_MISC.LRU_HINTS", 3198 "SampleAfterValue": "2000000", 3199 "UMask": "0x4" 3200 }, 3201 { 3202 "BriefDescription": "Super Queue lock splits across a cache line", 3203 "Counter": "0,1,2,3", 3204 "EventCode": "0xF4", 3205 "EventName": "SQ_MISC.SPLIT_LOCK", 3206 "SampleAfterValue": "2000000", 3207 "UMask": "0x10" 3208 }, 3209 { 3210 "BriefDescription": "Loads delayed with at-Retirement block code", 3211 "Counter": "0,1,2,3", 3212 "EventCode": "0x6", 3213 "EventName": "STORE_BLOCKS.AT_RET", 3214 "SampleAfterValue": "200000", 3215 "UMask": "0x4" 3216 }, 3217 { 3218 "BriefDescription": "Cacheable loads delayed with L1D block code", 3219 "Counter": "0,1,2,3", 3220 "EventCode": "0x6", 3221 "EventName": "STORE_BLOCKS.L1D_BLOCK", 3222 "SampleAfterValue": "200000", 3223 "UMask": "0x8" 3224 } 3225]