1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "EventCode": "0x63", 5 "EventName": "CACHE_LOCK_CYCLES.L1D", 6 "SampleAfterValue": "2000000", 7 "UMask": "0x2" 8 }, 9 { 10 "BriefDescription": "Cycles L1D and L2 locked", 11 "EventCode": "0x63", 12 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 13 "SampleAfterValue": "2000000", 14 "UMask": "0x1" 15 }, 16 { 17 "BriefDescription": "L1D cache lines replaced in M state", 18 "EventCode": "0x51", 19 "EventName": "L1D.M_EVICT", 20 "SampleAfterValue": "2000000", 21 "UMask": "0x4" 22 }, 23 { 24 "BriefDescription": "L1D cache lines allocated in the M state", 25 "EventCode": "0x51", 26 "EventName": "L1D.M_REPL", 27 "SampleAfterValue": "2000000", 28 "UMask": "0x2" 29 }, 30 { 31 "BriefDescription": "L1D snoop eviction of cache lines in M state", 32 "EventCode": "0x51", 33 "EventName": "L1D.M_SNOOP_EVICT", 34 "SampleAfterValue": "2000000", 35 "UMask": "0x8" 36 }, 37 { 38 "BriefDescription": "L1 data cache lines allocated", 39 "EventCode": "0x51", 40 "EventName": "L1D.REPL", 41 "SampleAfterValue": "2000000", 42 "UMask": "0x1" 43 }, 44 { 45 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 46 "EventCode": "0x52", 47 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 48 "SampleAfterValue": "2000000", 49 "UMask": "0x1" 50 }, 51 { 52 "BriefDescription": "L1D hardware prefetch misses", 53 "EventCode": "0x4E", 54 "EventName": "L1D_PREFETCH.MISS", 55 "SampleAfterValue": "200000", 56 "UMask": "0x2" 57 }, 58 { 59 "BriefDescription": "L1D hardware prefetch requests", 60 "EventCode": "0x4E", 61 "EventName": "L1D_PREFETCH.REQUESTS", 62 "SampleAfterValue": "200000", 63 "UMask": "0x1" 64 }, 65 { 66 "BriefDescription": "L1D hardware prefetch requests triggered", 67 "EventCode": "0x4E", 68 "EventName": "L1D_PREFETCH.TRIGGERS", 69 "SampleAfterValue": "200000", 70 "UMask": "0x4" 71 }, 72 { 73 "BriefDescription": "L1 writebacks to L2 in E state", 74 "EventCode": "0x28", 75 "EventName": "L1D_WB_L2.E_STATE", 76 "SampleAfterValue": "100000", 77 "UMask": "0x4" 78 }, 79 { 80 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 81 "EventCode": "0x28", 82 "EventName": "L1D_WB_L2.I_STATE", 83 "SampleAfterValue": "100000", 84 "UMask": "0x1" 85 }, 86 { 87 "BriefDescription": "All L1 writebacks to L2", 88 "EventCode": "0x28", 89 "EventName": "L1D_WB_L2.MESI", 90 "SampleAfterValue": "100000", 91 "UMask": "0xf" 92 }, 93 { 94 "BriefDescription": "L1 writebacks to L2 in M state", 95 "EventCode": "0x28", 96 "EventName": "L1D_WB_L2.M_STATE", 97 "SampleAfterValue": "100000", 98 "UMask": "0x8" 99 }, 100 { 101 "BriefDescription": "L1 writebacks to L2 in S state", 102 "EventCode": "0x28", 103 "EventName": "L1D_WB_L2.S_STATE", 104 "SampleAfterValue": "100000", 105 "UMask": "0x2" 106 }, 107 { 108 "BriefDescription": "All L2 data requests", 109 "EventCode": "0x26", 110 "EventName": "L2_DATA_RQSTS.ANY", 111 "SampleAfterValue": "200000", 112 "UMask": "0xff" 113 }, 114 { 115 "BriefDescription": "L2 data demand loads in E state", 116 "EventCode": "0x26", 117 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 118 "SampleAfterValue": "200000", 119 "UMask": "0x4" 120 }, 121 { 122 "BriefDescription": "L2 data demand loads in I state (misses)", 123 "EventCode": "0x26", 124 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 125 "SampleAfterValue": "200000", 126 "UMask": "0x1" 127 }, 128 { 129 "BriefDescription": "L2 data demand requests", 130 "EventCode": "0x26", 131 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 132 "SampleAfterValue": "200000", 133 "UMask": "0xf" 134 }, 135 { 136 "BriefDescription": "L2 data demand loads in M state", 137 "EventCode": "0x26", 138 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 139 "SampleAfterValue": "200000", 140 "UMask": "0x8" 141 }, 142 { 143 "BriefDescription": "L2 data demand loads in S state", 144 "EventCode": "0x26", 145 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 146 "SampleAfterValue": "200000", 147 "UMask": "0x2" 148 }, 149 { 150 "BriefDescription": "L2 data prefetches in E state", 151 "EventCode": "0x26", 152 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 153 "SampleAfterValue": "200000", 154 "UMask": "0x40" 155 }, 156 { 157 "BriefDescription": "L2 data prefetches in the I state (misses)", 158 "EventCode": "0x26", 159 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 160 "SampleAfterValue": "200000", 161 "UMask": "0x10" 162 }, 163 { 164 "BriefDescription": "All L2 data prefetches", 165 "EventCode": "0x26", 166 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 167 "SampleAfterValue": "200000", 168 "UMask": "0xf0" 169 }, 170 { 171 "BriefDescription": "L2 data prefetches in M state", 172 "EventCode": "0x26", 173 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 174 "SampleAfterValue": "200000", 175 "UMask": "0x80" 176 }, 177 { 178 "BriefDescription": "L2 data prefetches in the S state", 179 "EventCode": "0x26", 180 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 181 "SampleAfterValue": "200000", 182 "UMask": "0x20" 183 }, 184 { 185 "BriefDescription": "L2 lines alloacated", 186 "EventCode": "0xF1", 187 "EventName": "L2_LINES_IN.ANY", 188 "SampleAfterValue": "100000", 189 "UMask": "0x7" 190 }, 191 { 192 "BriefDescription": "L2 lines allocated in the E state", 193 "EventCode": "0xF1", 194 "EventName": "L2_LINES_IN.E_STATE", 195 "SampleAfterValue": "100000", 196 "UMask": "0x4" 197 }, 198 { 199 "BriefDescription": "L2 lines allocated in the S state", 200 "EventCode": "0xF1", 201 "EventName": "L2_LINES_IN.S_STATE", 202 "SampleAfterValue": "100000", 203 "UMask": "0x2" 204 }, 205 { 206 "BriefDescription": "L2 lines evicted", 207 "EventCode": "0xF2", 208 "EventName": "L2_LINES_OUT.ANY", 209 "SampleAfterValue": "100000", 210 "UMask": "0xf" 211 }, 212 { 213 "BriefDescription": "L2 lines evicted by a demand request", 214 "EventCode": "0xF2", 215 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 216 "SampleAfterValue": "100000", 217 "UMask": "0x1" 218 }, 219 { 220 "BriefDescription": "L2 modified lines evicted by a demand request", 221 "EventCode": "0xF2", 222 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 223 "SampleAfterValue": "100000", 224 "UMask": "0x2" 225 }, 226 { 227 "BriefDescription": "L2 lines evicted by a prefetch request", 228 "EventCode": "0xF2", 229 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 230 "SampleAfterValue": "100000", 231 "UMask": "0x4" 232 }, 233 { 234 "BriefDescription": "L2 modified lines evicted by a prefetch request", 235 "EventCode": "0xF2", 236 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 237 "SampleAfterValue": "100000", 238 "UMask": "0x8" 239 }, 240 { 241 "BriefDescription": "L2 instruction fetches", 242 "EventCode": "0x24", 243 "EventName": "L2_RQSTS.IFETCHES", 244 "SampleAfterValue": "200000", 245 "UMask": "0x30" 246 }, 247 { 248 "BriefDescription": "L2 instruction fetch hits", 249 "EventCode": "0x24", 250 "EventName": "L2_RQSTS.IFETCH_HIT", 251 "SampleAfterValue": "200000", 252 "UMask": "0x10" 253 }, 254 { 255 "BriefDescription": "L2 instruction fetch misses", 256 "EventCode": "0x24", 257 "EventName": "L2_RQSTS.IFETCH_MISS", 258 "SampleAfterValue": "200000", 259 "UMask": "0x20" 260 }, 261 { 262 "BriefDescription": "L2 load hits", 263 "EventCode": "0x24", 264 "EventName": "L2_RQSTS.LD_HIT", 265 "SampleAfterValue": "200000", 266 "UMask": "0x1" 267 }, 268 { 269 "BriefDescription": "L2 load misses", 270 "EventCode": "0x24", 271 "EventName": "L2_RQSTS.LD_MISS", 272 "SampleAfterValue": "200000", 273 "UMask": "0x2" 274 }, 275 { 276 "BriefDescription": "L2 requests", 277 "EventCode": "0x24", 278 "EventName": "L2_RQSTS.LOADS", 279 "SampleAfterValue": "200000", 280 "UMask": "0x3" 281 }, 282 { 283 "BriefDescription": "All L2 misses", 284 "EventCode": "0x24", 285 "EventName": "L2_RQSTS.MISS", 286 "SampleAfterValue": "200000", 287 "UMask": "0xaa" 288 }, 289 { 290 "BriefDescription": "All L2 prefetches", 291 "EventCode": "0x24", 292 "EventName": "L2_RQSTS.PREFETCHES", 293 "SampleAfterValue": "200000", 294 "UMask": "0xc0" 295 }, 296 { 297 "BriefDescription": "L2 prefetch hits", 298 "EventCode": "0x24", 299 "EventName": "L2_RQSTS.PREFETCH_HIT", 300 "SampleAfterValue": "200000", 301 "UMask": "0x40" 302 }, 303 { 304 "BriefDescription": "L2 prefetch misses", 305 "EventCode": "0x24", 306 "EventName": "L2_RQSTS.PREFETCH_MISS", 307 "SampleAfterValue": "200000", 308 "UMask": "0x80" 309 }, 310 { 311 "BriefDescription": "All L2 requests", 312 "EventCode": "0x24", 313 "EventName": "L2_RQSTS.REFERENCES", 314 "SampleAfterValue": "200000", 315 "UMask": "0xff" 316 }, 317 { 318 "BriefDescription": "L2 RFO requests", 319 "EventCode": "0x24", 320 "EventName": "L2_RQSTS.RFOS", 321 "SampleAfterValue": "200000", 322 "UMask": "0xc" 323 }, 324 { 325 "BriefDescription": "L2 RFO hits", 326 "EventCode": "0x24", 327 "EventName": "L2_RQSTS.RFO_HIT", 328 "SampleAfterValue": "200000", 329 "UMask": "0x4" 330 }, 331 { 332 "BriefDescription": "L2 RFO misses", 333 "EventCode": "0x24", 334 "EventName": "L2_RQSTS.RFO_MISS", 335 "SampleAfterValue": "200000", 336 "UMask": "0x8" 337 }, 338 { 339 "BriefDescription": "All L2 transactions", 340 "EventCode": "0xF0", 341 "EventName": "L2_TRANSACTIONS.ANY", 342 "SampleAfterValue": "200000", 343 "UMask": "0x80" 344 }, 345 { 346 "BriefDescription": "L2 fill transactions", 347 "EventCode": "0xF0", 348 "EventName": "L2_TRANSACTIONS.FILL", 349 "SampleAfterValue": "200000", 350 "UMask": "0x20" 351 }, 352 { 353 "BriefDescription": "L2 instruction fetch transactions", 354 "EventCode": "0xF0", 355 "EventName": "L2_TRANSACTIONS.IFETCH", 356 "SampleAfterValue": "200000", 357 "UMask": "0x4" 358 }, 359 { 360 "BriefDescription": "L1D writeback to L2 transactions", 361 "EventCode": "0xF0", 362 "EventName": "L2_TRANSACTIONS.L1D_WB", 363 "SampleAfterValue": "200000", 364 "UMask": "0x10" 365 }, 366 { 367 "BriefDescription": "L2 Load transactions", 368 "EventCode": "0xF0", 369 "EventName": "L2_TRANSACTIONS.LOAD", 370 "SampleAfterValue": "200000", 371 "UMask": "0x1" 372 }, 373 { 374 "BriefDescription": "L2 prefetch transactions", 375 "EventCode": "0xF0", 376 "EventName": "L2_TRANSACTIONS.PREFETCH", 377 "SampleAfterValue": "200000", 378 "UMask": "0x8" 379 }, 380 { 381 "BriefDescription": "L2 RFO transactions", 382 "EventCode": "0xF0", 383 "EventName": "L2_TRANSACTIONS.RFO", 384 "SampleAfterValue": "200000", 385 "UMask": "0x2" 386 }, 387 { 388 "BriefDescription": "L2 writeback to LLC transactions", 389 "EventCode": "0xF0", 390 "EventName": "L2_TRANSACTIONS.WB", 391 "SampleAfterValue": "200000", 392 "UMask": "0x40" 393 }, 394 { 395 "BriefDescription": "L2 demand lock RFOs in E state", 396 "EventCode": "0x27", 397 "EventName": "L2_WRITE.LOCK.E_STATE", 398 "SampleAfterValue": "100000", 399 "UMask": "0x40" 400 }, 401 { 402 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 403 "EventCode": "0x27", 404 "EventName": "L2_WRITE.LOCK.HIT", 405 "SampleAfterValue": "100000", 406 "UMask": "0xe0" 407 }, 408 { 409 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 410 "EventCode": "0x27", 411 "EventName": "L2_WRITE.LOCK.I_STATE", 412 "SampleAfterValue": "100000", 413 "UMask": "0x10" 414 }, 415 { 416 "BriefDescription": "All demand L2 lock RFOs", 417 "EventCode": "0x27", 418 "EventName": "L2_WRITE.LOCK.MESI", 419 "SampleAfterValue": "100000", 420 "UMask": "0xf0" 421 }, 422 { 423 "BriefDescription": "L2 demand lock RFOs in M state", 424 "EventCode": "0x27", 425 "EventName": "L2_WRITE.LOCK.M_STATE", 426 "SampleAfterValue": "100000", 427 "UMask": "0x80" 428 }, 429 { 430 "BriefDescription": "L2 demand lock RFOs in S state", 431 "EventCode": "0x27", 432 "EventName": "L2_WRITE.LOCK.S_STATE", 433 "SampleAfterValue": "100000", 434 "UMask": "0x20" 435 }, 436 { 437 "BriefDescription": "All L2 demand store RFOs that hit the cache", 438 "EventCode": "0x27", 439 "EventName": "L2_WRITE.RFO.HIT", 440 "SampleAfterValue": "100000", 441 "UMask": "0xe" 442 }, 443 { 444 "BriefDescription": "L2 demand store RFOs in I state (misses)", 445 "EventCode": "0x27", 446 "EventName": "L2_WRITE.RFO.I_STATE", 447 "SampleAfterValue": "100000", 448 "UMask": "0x1" 449 }, 450 { 451 "BriefDescription": "All L2 demand store RFOs", 452 "EventCode": "0x27", 453 "EventName": "L2_WRITE.RFO.MESI", 454 "SampleAfterValue": "100000", 455 "UMask": "0xf" 456 }, 457 { 458 "BriefDescription": "L2 demand store RFOs in M state", 459 "EventCode": "0x27", 460 "EventName": "L2_WRITE.RFO.M_STATE", 461 "SampleAfterValue": "100000", 462 "UMask": "0x8" 463 }, 464 { 465 "BriefDescription": "L2 demand store RFOs in S state", 466 "EventCode": "0x27", 467 "EventName": "L2_WRITE.RFO.S_STATE", 468 "SampleAfterValue": "100000", 469 "UMask": "0x2" 470 }, 471 { 472 "BriefDescription": "Longest latency cache miss", 473 "EventCode": "0x2E", 474 "EventName": "LONGEST_LAT_CACHE.MISS", 475 "SampleAfterValue": "100000", 476 "UMask": "0x41" 477 }, 478 { 479 "BriefDescription": "Longest latency cache reference", 480 "EventCode": "0x2E", 481 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 482 "SampleAfterValue": "200000", 483 "UMask": "0x4f" 484 }, 485 { 486 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 487 "EventCode": "0xB", 488 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 489 "MSRIndex": "0x3F6", 490 "PEBS": "2", 491 "SampleAfterValue": "2000000", 492 "UMask": "0x10" 493 }, 494 { 495 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 496 "EventCode": "0xB", 497 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 498 "MSRIndex": "0x3F6", 499 "MSRValue": "0x400", 500 "PEBS": "2", 501 "SampleAfterValue": "100", 502 "UMask": "0x10" 503 }, 504 { 505 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 506 "EventCode": "0xB", 507 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 508 "MSRIndex": "0x3F6", 509 "MSRValue": "0x80", 510 "PEBS": "2", 511 "SampleAfterValue": "1000", 512 "UMask": "0x10" 513 }, 514 { 515 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 516 "EventCode": "0xB", 517 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 518 "MSRIndex": "0x3F6", 519 "MSRValue": "0x10", 520 "PEBS": "2", 521 "SampleAfterValue": "10000", 522 "UMask": "0x10" 523 }, 524 { 525 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 526 "EventCode": "0xB", 527 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 528 "MSRIndex": "0x3F6", 529 "MSRValue": "0x4000", 530 "PEBS": "2", 531 "SampleAfterValue": "5", 532 "UMask": "0x10" 533 }, 534 { 535 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 536 "EventCode": "0xB", 537 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 538 "MSRIndex": "0x3F6", 539 "MSRValue": "0x800", 540 "PEBS": "2", 541 "SampleAfterValue": "50", 542 "UMask": "0x10" 543 }, 544 { 545 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 546 "EventCode": "0xB", 547 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 548 "MSRIndex": "0x3F6", 549 "MSRValue": "0x100", 550 "PEBS": "2", 551 "SampleAfterValue": "500", 552 "UMask": "0x10" 553 }, 554 { 555 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 556 "EventCode": "0xB", 557 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 558 "MSRIndex": "0x3F6", 559 "MSRValue": "0x20", 560 "PEBS": "2", 561 "SampleAfterValue": "5000", 562 "UMask": "0x10" 563 }, 564 { 565 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 566 "EventCode": "0xB", 567 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 568 "MSRIndex": "0x3F6", 569 "MSRValue": "0x8000", 570 "PEBS": "2", 571 "SampleAfterValue": "3", 572 "UMask": "0x10" 573 }, 574 { 575 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 576 "EventCode": "0xB", 577 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 578 "MSRIndex": "0x3F6", 579 "MSRValue": "0x4", 580 "PEBS": "2", 581 "SampleAfterValue": "50000", 582 "UMask": "0x10" 583 }, 584 { 585 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 586 "EventCode": "0xB", 587 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 588 "MSRIndex": "0x3F6", 589 "MSRValue": "0x1000", 590 "PEBS": "2", 591 "SampleAfterValue": "20", 592 "UMask": "0x10" 593 }, 594 { 595 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 596 "EventCode": "0xB", 597 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 598 "MSRIndex": "0x3F6", 599 "MSRValue": "0x200", 600 "PEBS": "2", 601 "SampleAfterValue": "200", 602 "UMask": "0x10" 603 }, 604 { 605 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 606 "EventCode": "0xB", 607 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 608 "MSRIndex": "0x3F6", 609 "MSRValue": "0x40", 610 "PEBS": "2", 611 "SampleAfterValue": "2000", 612 "UMask": "0x10" 613 }, 614 { 615 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 616 "EventCode": "0xB", 617 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 618 "MSRIndex": "0x3F6", 619 "MSRValue": "0x8", 620 "PEBS": "2", 621 "SampleAfterValue": "20000", 622 "UMask": "0x10" 623 }, 624 { 625 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 626 "EventCode": "0xB", 627 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 628 "MSRIndex": "0x3F6", 629 "MSRValue": "0x2000", 630 "PEBS": "2", 631 "SampleAfterValue": "10", 632 "UMask": "0x10" 633 }, 634 { 635 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 636 "EventCode": "0xB", 637 "EventName": "MEM_INST_RETIRED.LOADS", 638 "PEBS": "1", 639 "SampleAfterValue": "2000000", 640 "UMask": "0x1" 641 }, 642 { 643 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 644 "EventCode": "0xB", 645 "EventName": "MEM_INST_RETIRED.STORES", 646 "PEBS": "1", 647 "SampleAfterValue": "2000000", 648 "UMask": "0x2" 649 }, 650 { 651 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 652 "EventCode": "0xCB", 653 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 654 "PEBS": "1", 655 "SampleAfterValue": "200000", 656 "UMask": "0x40" 657 }, 658 { 659 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 660 "EventCode": "0xCB", 661 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 662 "PEBS": "1", 663 "SampleAfterValue": "2000000", 664 "UMask": "0x1" 665 }, 666 { 667 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 668 "EventCode": "0xCB", 669 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 670 "PEBS": "1", 671 "SampleAfterValue": "200000", 672 "UMask": "0x2" 673 }, 674 { 675 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 676 "EventCode": "0xCB", 677 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 678 "PEBS": "1", 679 "SampleAfterValue": "10000", 680 "UMask": "0x10" 681 }, 682 { 683 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 684 "EventCode": "0xCB", 685 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 686 "PEBS": "1", 687 "SampleAfterValue": "40000", 688 "UMask": "0x4" 689 }, 690 { 691 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 692 "EventCode": "0xCB", 693 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 694 "PEBS": "1", 695 "SampleAfterValue": "40000", 696 "UMask": "0x8" 697 }, 698 { 699 "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", 700 "EventCode": "0xF", 701 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", 702 "PEBS": "1", 703 "SampleAfterValue": "10000", 704 "UMask": "0x10" 705 }, 706 { 707 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", 708 "EventCode": "0xF", 709 "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", 710 "PEBS": "1", 711 "SampleAfterValue": "40000", 712 "UMask": "0x2" 713 }, 714 { 715 "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", 716 "EventCode": "0xF", 717 "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", 718 "PEBS": "1", 719 "SampleAfterValue": "20000", 720 "UMask": "0x8" 721 }, 722 { 723 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", 724 "EventCode": "0xF", 725 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", 726 "PEBS": "1", 727 "SampleAfterValue": "10000", 728 "UMask": "0x20" 729 }, 730 { 731 "BriefDescription": "Load instructions retired IO (Precise Event)", 732 "EventCode": "0xF", 733 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", 734 "PEBS": "1", 735 "SampleAfterValue": "4000", 736 "UMask": "0x80" 737 }, 738 { 739 "BriefDescription": "All offcore requests", 740 "EventCode": "0xB0", 741 "EventName": "OFFCORE_REQUESTS.ANY", 742 "SampleAfterValue": "100000", 743 "UMask": "0x80" 744 }, 745 { 746 "BriefDescription": "Offcore read requests", 747 "EventCode": "0xB0", 748 "EventName": "OFFCORE_REQUESTS.ANY.READ", 749 "SampleAfterValue": "100000", 750 "UMask": "0x8" 751 }, 752 { 753 "BriefDescription": "Offcore RFO requests", 754 "EventCode": "0xB0", 755 "EventName": "OFFCORE_REQUESTS.ANY.RFO", 756 "SampleAfterValue": "100000", 757 "UMask": "0x10" 758 }, 759 { 760 "BriefDescription": "Offcore demand code read requests", 761 "EventCode": "0xB0", 762 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", 763 "SampleAfterValue": "100000", 764 "UMask": "0x2" 765 }, 766 { 767 "BriefDescription": "Offcore demand data read requests", 768 "EventCode": "0xB0", 769 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", 770 "SampleAfterValue": "100000", 771 "UMask": "0x1" 772 }, 773 { 774 "BriefDescription": "Offcore demand RFO requests", 775 "EventCode": "0xB0", 776 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", 777 "SampleAfterValue": "100000", 778 "UMask": "0x4" 779 }, 780 { 781 "BriefDescription": "Offcore L1 data cache writebacks", 782 "EventCode": "0xB0", 783 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 784 "SampleAfterValue": "100000", 785 "UMask": "0x40" 786 }, 787 { 788 "BriefDescription": "Offcore uncached memory accesses", 789 "EventCode": "0xB0", 790 "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", 791 "SampleAfterValue": "100000", 792 "UMask": "0x20" 793 }, 794 { 795 "BriefDescription": "Outstanding offcore reads", 796 "EventCode": "0x60", 797 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", 798 "SampleAfterValue": "2000000", 799 "UMask": "0x8" 800 }, 801 { 802 "BriefDescription": "Cycles offcore reads busy", 803 "CounterMask": "1", 804 "EventCode": "0x60", 805 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", 806 "SampleAfterValue": "2000000", 807 "UMask": "0x8" 808 }, 809 { 810 "BriefDescription": "Outstanding offcore demand code reads", 811 "EventCode": "0x60", 812 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", 813 "SampleAfterValue": "2000000", 814 "UMask": "0x2" 815 }, 816 { 817 "BriefDescription": "Cycles offcore demand code read busy", 818 "CounterMask": "1", 819 "EventCode": "0x60", 820 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", 821 "SampleAfterValue": "2000000", 822 "UMask": "0x2" 823 }, 824 { 825 "BriefDescription": "Outstanding offcore demand data reads", 826 "EventCode": "0x60", 827 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", 828 "SampleAfterValue": "2000000", 829 "UMask": "0x1" 830 }, 831 { 832 "BriefDescription": "Cycles offcore demand data read busy", 833 "CounterMask": "1", 834 "EventCode": "0x60", 835 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", 836 "SampleAfterValue": "2000000", 837 "UMask": "0x1" 838 }, 839 { 840 "BriefDescription": "Outstanding offcore demand RFOs", 841 "EventCode": "0x60", 842 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", 843 "SampleAfterValue": "2000000", 844 "UMask": "0x4" 845 }, 846 { 847 "BriefDescription": "Cycles offcore demand RFOs busy", 848 "CounterMask": "1", 849 "EventCode": "0x60", 850 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", 851 "SampleAfterValue": "2000000", 852 "UMask": "0x4" 853 }, 854 { 855 "BriefDescription": "Offcore requests blocked due to Super Queue full", 856 "EventCode": "0xB2", 857 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 858 "SampleAfterValue": "100000", 859 "UMask": "0x1" 860 }, 861 { 862 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 863 "EventCode": "0xB7, 0xBB", 864 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 865 "MSRIndex": "0x1a6,0x1a7", 866 "MSRValue": "0x7F11", 867 "SampleAfterValue": "100000", 868 "UMask": "0x1" 869 }, 870 { 871 "BriefDescription": "All offcore data reads", 872 "EventCode": "0xB7, 0xBB", 873 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 874 "MSRIndex": "0x1a6,0x1a7", 875 "MSRValue": "0xFF11", 876 "SampleAfterValue": "100000", 877 "UMask": "0x1" 878 }, 879 { 880 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 881 "EventCode": "0xB7, 0xBB", 882 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 883 "MSRIndex": "0x1a6,0x1a7", 884 "MSRValue": "0x8011", 885 "SampleAfterValue": "100000", 886 "UMask": "0x1" 887 }, 888 { 889 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 890 "EventCode": "0xB7, 0xBB", 891 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 892 "MSRIndex": "0x1a6,0x1a7", 893 "MSRValue": "0x111", 894 "SampleAfterValue": "100000", 895 "UMask": "0x1" 896 }, 897 { 898 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 899 "EventCode": "0xB7, 0xBB", 900 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 901 "MSRIndex": "0x1a6,0x1a7", 902 "MSRValue": "0x211", 903 "SampleAfterValue": "100000", 904 "UMask": "0x1" 905 }, 906 { 907 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 908 "EventCode": "0xB7, 0xBB", 909 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 910 "MSRIndex": "0x1a6,0x1a7", 911 "MSRValue": "0x411", 912 "SampleAfterValue": "100000", 913 "UMask": "0x1" 914 }, 915 { 916 "BriefDescription": "Offcore data reads satisfied by the LLC", 917 "EventCode": "0xB7, 0xBB", 918 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 919 "MSRIndex": "0x1a6,0x1a7", 920 "MSRValue": "0x711", 921 "SampleAfterValue": "100000", 922 "UMask": "0x1" 923 }, 924 { 925 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 926 "EventCode": "0xB7, 0xBB", 927 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 928 "MSRIndex": "0x1a6,0x1a7", 929 "MSRValue": "0x2711", 930 "SampleAfterValue": "100000", 931 "UMask": "0x1" 932 }, 933 { 934 "BriefDescription": "Offcore data reads satisfied by a remote cache", 935 "EventCode": "0xB7, 0xBB", 936 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 937 "MSRIndex": "0x1a6,0x1a7", 938 "MSRValue": "0x1811", 939 "SampleAfterValue": "100000", 940 "UMask": "0x1" 941 }, 942 { 943 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 944 "EventCode": "0xB7, 0xBB", 945 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 946 "MSRIndex": "0x1a6,0x1a7", 947 "MSRValue": "0x5811", 948 "SampleAfterValue": "100000", 949 "UMask": "0x1" 950 }, 951 { 952 "BriefDescription": "Offcore data reads that HIT in a remote cache", 953 "EventCode": "0xB7, 0xBB", 954 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 955 "MSRIndex": "0x1a6,0x1a7", 956 "MSRValue": "0x1011", 957 "SampleAfterValue": "100000", 958 "UMask": "0x1" 959 }, 960 { 961 "BriefDescription": "Offcore data reads that HITM in a remote cache", 962 "EventCode": "0xB7, 0xBB", 963 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 964 "MSRIndex": "0x1a6,0x1a7", 965 "MSRValue": "0x811", 966 "SampleAfterValue": "100000", 967 "UMask": "0x1" 968 }, 969 { 970 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 971 "EventCode": "0xB7, 0xBB", 972 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 973 "MSRIndex": "0x1a6,0x1a7", 974 "MSRValue": "0x7F44", 975 "SampleAfterValue": "100000", 976 "UMask": "0x1" 977 }, 978 { 979 "BriefDescription": "All offcore code reads", 980 "EventCode": "0xB7, 0xBB", 981 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 982 "MSRIndex": "0x1a6,0x1a7", 983 "MSRValue": "0xFF44", 984 "SampleAfterValue": "100000", 985 "UMask": "0x1" 986 }, 987 { 988 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 989 "EventCode": "0xB7, 0xBB", 990 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 991 "MSRIndex": "0x1a6,0x1a7", 992 "MSRValue": "0x8044", 993 "SampleAfterValue": "100000", 994 "UMask": "0x1" 995 }, 996 { 997 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 998 "EventCode": "0xB7, 0xBB", 999 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1000 "MSRIndex": "0x1a6,0x1a7", 1001 "MSRValue": "0x144", 1002 "SampleAfterValue": "100000", 1003 "UMask": "0x1" 1004 }, 1005 { 1006 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1007 "EventCode": "0xB7, 0xBB", 1008 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1009 "MSRIndex": "0x1a6,0x1a7", 1010 "MSRValue": "0x244", 1011 "SampleAfterValue": "100000", 1012 "UMask": "0x1" 1013 }, 1014 { 1015 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1016 "EventCode": "0xB7, 0xBB", 1017 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1018 "MSRIndex": "0x1a6,0x1a7", 1019 "MSRValue": "0x444", 1020 "SampleAfterValue": "100000", 1021 "UMask": "0x1" 1022 }, 1023 { 1024 "BriefDescription": "Offcore code reads satisfied by the LLC", 1025 "EventCode": "0xB7, 0xBB", 1026 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1027 "MSRIndex": "0x1a6,0x1a7", 1028 "MSRValue": "0x744", 1029 "SampleAfterValue": "100000", 1030 "UMask": "0x1" 1031 }, 1032 { 1033 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1034 "EventCode": "0xB7, 0xBB", 1035 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1036 "MSRIndex": "0x1a6,0x1a7", 1037 "MSRValue": "0x2744", 1038 "SampleAfterValue": "100000", 1039 "UMask": "0x1" 1040 }, 1041 { 1042 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1043 "EventCode": "0xB7, 0xBB", 1044 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1045 "MSRIndex": "0x1a6,0x1a7", 1046 "MSRValue": "0x1844", 1047 "SampleAfterValue": "100000", 1048 "UMask": "0x1" 1049 }, 1050 { 1051 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1052 "EventCode": "0xB7, 0xBB", 1053 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1054 "MSRIndex": "0x1a6,0x1a7", 1055 "MSRValue": "0x5844", 1056 "SampleAfterValue": "100000", 1057 "UMask": "0x1" 1058 }, 1059 { 1060 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1061 "EventCode": "0xB7, 0xBB", 1062 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1063 "MSRIndex": "0x1a6,0x1a7", 1064 "MSRValue": "0x1044", 1065 "SampleAfterValue": "100000", 1066 "UMask": "0x1" 1067 }, 1068 { 1069 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1070 "EventCode": "0xB7, 0xBB", 1071 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1072 "MSRIndex": "0x1a6,0x1a7", 1073 "MSRValue": "0x844", 1074 "SampleAfterValue": "100000", 1075 "UMask": "0x1" 1076 }, 1077 { 1078 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1079 "EventCode": "0xB7, 0xBB", 1080 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1081 "MSRIndex": "0x1a6,0x1a7", 1082 "MSRValue": "0x7FFF", 1083 "SampleAfterValue": "100000", 1084 "UMask": "0x1" 1085 }, 1086 { 1087 "BriefDescription": "All offcore requests", 1088 "EventCode": "0xB7, 0xBB", 1089 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1090 "MSRIndex": "0x1a6,0x1a7", 1091 "MSRValue": "0xFFFF", 1092 "SampleAfterValue": "100000", 1093 "UMask": "0x1" 1094 }, 1095 { 1096 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1097 "EventCode": "0xB7, 0xBB", 1098 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1099 "MSRIndex": "0x1a6,0x1a7", 1100 "MSRValue": "0x80FF", 1101 "SampleAfterValue": "100000", 1102 "UMask": "0x1" 1103 }, 1104 { 1105 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1106 "EventCode": "0xB7, 0xBB", 1107 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1108 "MSRIndex": "0x1a6,0x1a7", 1109 "MSRValue": "0x1FF", 1110 "SampleAfterValue": "100000", 1111 "UMask": "0x1" 1112 }, 1113 { 1114 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1115 "EventCode": "0xB7, 0xBB", 1116 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1117 "MSRIndex": "0x1a6,0x1a7", 1118 "MSRValue": "0x2FF", 1119 "SampleAfterValue": "100000", 1120 "UMask": "0x1" 1121 }, 1122 { 1123 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1124 "EventCode": "0xB7, 0xBB", 1125 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1126 "MSRIndex": "0x1a6,0x1a7", 1127 "MSRValue": "0x4FF", 1128 "SampleAfterValue": "100000", 1129 "UMask": "0x1" 1130 }, 1131 { 1132 "BriefDescription": "Offcore requests satisfied by the LLC", 1133 "EventCode": "0xB7, 0xBB", 1134 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1135 "MSRIndex": "0x1a6,0x1a7", 1136 "MSRValue": "0x7FF", 1137 "SampleAfterValue": "100000", 1138 "UMask": "0x1" 1139 }, 1140 { 1141 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1142 "EventCode": "0xB7, 0xBB", 1143 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1144 "MSRIndex": "0x1a6,0x1a7", 1145 "MSRValue": "0x27FF", 1146 "SampleAfterValue": "100000", 1147 "UMask": "0x1" 1148 }, 1149 { 1150 "BriefDescription": "Offcore requests satisfied by a remote cache", 1151 "EventCode": "0xB7, 0xBB", 1152 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1153 "MSRIndex": "0x1a6,0x1a7", 1154 "MSRValue": "0x18FF", 1155 "SampleAfterValue": "100000", 1156 "UMask": "0x1" 1157 }, 1158 { 1159 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1160 "EventCode": "0xB7, 0xBB", 1161 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1162 "MSRIndex": "0x1a6,0x1a7", 1163 "MSRValue": "0x58FF", 1164 "SampleAfterValue": "100000", 1165 "UMask": "0x1" 1166 }, 1167 { 1168 "BriefDescription": "Offcore requests that HIT in a remote cache", 1169 "EventCode": "0xB7, 0xBB", 1170 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1171 "MSRIndex": "0x1a6,0x1a7", 1172 "MSRValue": "0x10FF", 1173 "SampleAfterValue": "100000", 1174 "UMask": "0x1" 1175 }, 1176 { 1177 "BriefDescription": "Offcore requests that HITM in a remote cache", 1178 "EventCode": "0xB7, 0xBB", 1179 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1180 "MSRIndex": "0x1a6,0x1a7", 1181 "MSRValue": "0x8FF", 1182 "SampleAfterValue": "100000", 1183 "UMask": "0x1" 1184 }, 1185 { 1186 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1187 "EventCode": "0xB7, 0xBB", 1188 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1189 "MSRIndex": "0x1a6,0x1a7", 1190 "MSRValue": "0x7F22", 1191 "SampleAfterValue": "100000", 1192 "UMask": "0x1" 1193 }, 1194 { 1195 "BriefDescription": "All offcore RFO requests", 1196 "EventCode": "0xB7, 0xBB", 1197 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1198 "MSRIndex": "0x1a6,0x1a7", 1199 "MSRValue": "0xFF22", 1200 "SampleAfterValue": "100000", 1201 "UMask": "0x1" 1202 }, 1203 { 1204 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1205 "EventCode": "0xB7, 0xBB", 1206 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1207 "MSRIndex": "0x1a6,0x1a7", 1208 "MSRValue": "0x8022", 1209 "SampleAfterValue": "100000", 1210 "UMask": "0x1" 1211 }, 1212 { 1213 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1214 "EventCode": "0xB7, 0xBB", 1215 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1216 "MSRIndex": "0x1a6,0x1a7", 1217 "MSRValue": "0x122", 1218 "SampleAfterValue": "100000", 1219 "UMask": "0x1" 1220 }, 1221 { 1222 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1223 "EventCode": "0xB7, 0xBB", 1224 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1225 "MSRIndex": "0x1a6,0x1a7", 1226 "MSRValue": "0x222", 1227 "SampleAfterValue": "100000", 1228 "UMask": "0x1" 1229 }, 1230 { 1231 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1232 "EventCode": "0xB7, 0xBB", 1233 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1234 "MSRIndex": "0x1a6,0x1a7", 1235 "MSRValue": "0x422", 1236 "SampleAfterValue": "100000", 1237 "UMask": "0x1" 1238 }, 1239 { 1240 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1241 "EventCode": "0xB7, 0xBB", 1242 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1243 "MSRIndex": "0x1a6,0x1a7", 1244 "MSRValue": "0x722", 1245 "SampleAfterValue": "100000", 1246 "UMask": "0x1" 1247 }, 1248 { 1249 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1250 "EventCode": "0xB7, 0xBB", 1251 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1252 "MSRIndex": "0x1a6,0x1a7", 1253 "MSRValue": "0x2722", 1254 "SampleAfterValue": "100000", 1255 "UMask": "0x1" 1256 }, 1257 { 1258 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1259 "EventCode": "0xB7, 0xBB", 1260 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1261 "MSRIndex": "0x1a6,0x1a7", 1262 "MSRValue": "0x1822", 1263 "SampleAfterValue": "100000", 1264 "UMask": "0x1" 1265 }, 1266 { 1267 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1268 "EventCode": "0xB7, 0xBB", 1269 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1270 "MSRIndex": "0x1a6,0x1a7", 1271 "MSRValue": "0x5822", 1272 "SampleAfterValue": "100000", 1273 "UMask": "0x1" 1274 }, 1275 { 1276 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1277 "EventCode": "0xB7, 0xBB", 1278 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1279 "MSRIndex": "0x1a6,0x1a7", 1280 "MSRValue": "0x1022", 1281 "SampleAfterValue": "100000", 1282 "UMask": "0x1" 1283 }, 1284 { 1285 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1286 "EventCode": "0xB7, 0xBB", 1287 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1288 "MSRIndex": "0x1a6,0x1a7", 1289 "MSRValue": "0x822", 1290 "SampleAfterValue": "100000", 1291 "UMask": "0x1" 1292 }, 1293 { 1294 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1295 "EventCode": "0xB7, 0xBB", 1296 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1297 "MSRIndex": "0x1a6,0x1a7", 1298 "MSRValue": "0x7F08", 1299 "SampleAfterValue": "100000", 1300 "UMask": "0x1" 1301 }, 1302 { 1303 "BriefDescription": "All offcore writebacks", 1304 "EventCode": "0xB7, 0xBB", 1305 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1306 "MSRIndex": "0x1a6,0x1a7", 1307 "MSRValue": "0xFF08", 1308 "SampleAfterValue": "100000", 1309 "UMask": "0x1" 1310 }, 1311 { 1312 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1313 "EventCode": "0xB7, 0xBB", 1314 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1315 "MSRIndex": "0x1a6,0x1a7", 1316 "MSRValue": "0x8008", 1317 "SampleAfterValue": "100000", 1318 "UMask": "0x1" 1319 }, 1320 { 1321 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1322 "EventCode": "0xB7, 0xBB", 1323 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1324 "MSRIndex": "0x1a6,0x1a7", 1325 "MSRValue": "0x108", 1326 "SampleAfterValue": "100000", 1327 "UMask": "0x1" 1328 }, 1329 { 1330 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1331 "EventCode": "0xB7, 0xBB", 1332 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1333 "MSRIndex": "0x1a6,0x1a7", 1334 "MSRValue": "0x408", 1335 "SampleAfterValue": "100000", 1336 "UMask": "0x1" 1337 }, 1338 { 1339 "BriefDescription": "Offcore writebacks to the LLC", 1340 "EventCode": "0xB7, 0xBB", 1341 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1342 "MSRIndex": "0x1a6,0x1a7", 1343 "MSRValue": "0x708", 1344 "SampleAfterValue": "100000", 1345 "UMask": "0x1" 1346 }, 1347 { 1348 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1349 "EventCode": "0xB7, 0xBB", 1350 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1351 "MSRIndex": "0x1a6,0x1a7", 1352 "MSRValue": "0x2708", 1353 "SampleAfterValue": "100000", 1354 "UMask": "0x1" 1355 }, 1356 { 1357 "BriefDescription": "Offcore writebacks to a remote cache", 1358 "EventCode": "0xB7, 0xBB", 1359 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1360 "MSRIndex": "0x1a6,0x1a7", 1361 "MSRValue": "0x1808", 1362 "SampleAfterValue": "100000", 1363 "UMask": "0x1" 1364 }, 1365 { 1366 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1367 "EventCode": "0xB7, 0xBB", 1368 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1369 "MSRIndex": "0x1a6,0x1a7", 1370 "MSRValue": "0x5808", 1371 "SampleAfterValue": "100000", 1372 "UMask": "0x1" 1373 }, 1374 { 1375 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1376 "EventCode": "0xB7, 0xBB", 1377 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1378 "MSRIndex": "0x1a6,0x1a7", 1379 "MSRValue": "0x1008", 1380 "SampleAfterValue": "100000", 1381 "UMask": "0x1" 1382 }, 1383 { 1384 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1385 "EventCode": "0xB7, 0xBB", 1386 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1387 "MSRIndex": "0x1a6,0x1a7", 1388 "MSRValue": "0x808", 1389 "SampleAfterValue": "100000", 1390 "UMask": "0x1" 1391 }, 1392 { 1393 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1394 "EventCode": "0xB7, 0xBB", 1395 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1396 "MSRIndex": "0x1a6,0x1a7", 1397 "MSRValue": "0x7F77", 1398 "SampleAfterValue": "100000", 1399 "UMask": "0x1" 1400 }, 1401 { 1402 "BriefDescription": "All offcore code or data read requests", 1403 "EventCode": "0xB7, 0xBB", 1404 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1405 "MSRIndex": "0x1a6,0x1a7", 1406 "MSRValue": "0xFF77", 1407 "SampleAfterValue": "100000", 1408 "UMask": "0x1" 1409 }, 1410 { 1411 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1412 "EventCode": "0xB7, 0xBB", 1413 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1414 "MSRIndex": "0x1a6,0x1a7", 1415 "MSRValue": "0x8077", 1416 "SampleAfterValue": "100000", 1417 "UMask": "0x1" 1418 }, 1419 { 1420 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1421 "EventCode": "0xB7, 0xBB", 1422 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1423 "MSRIndex": "0x1a6,0x1a7", 1424 "MSRValue": "0x177", 1425 "SampleAfterValue": "100000", 1426 "UMask": "0x1" 1427 }, 1428 { 1429 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1430 "EventCode": "0xB7, 0xBB", 1431 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1432 "MSRIndex": "0x1a6,0x1a7", 1433 "MSRValue": "0x277", 1434 "SampleAfterValue": "100000", 1435 "UMask": "0x1" 1436 }, 1437 { 1438 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1439 "EventCode": "0xB7, 0xBB", 1440 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1441 "MSRIndex": "0x1a6,0x1a7", 1442 "MSRValue": "0x477", 1443 "SampleAfterValue": "100000", 1444 "UMask": "0x1" 1445 }, 1446 { 1447 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1448 "EventCode": "0xB7, 0xBB", 1449 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1450 "MSRIndex": "0x1a6,0x1a7", 1451 "MSRValue": "0x777", 1452 "SampleAfterValue": "100000", 1453 "UMask": "0x1" 1454 }, 1455 { 1456 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1457 "EventCode": "0xB7, 0xBB", 1458 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1459 "MSRIndex": "0x1a6,0x1a7", 1460 "MSRValue": "0x2777", 1461 "SampleAfterValue": "100000", 1462 "UMask": "0x1" 1463 }, 1464 { 1465 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1466 "EventCode": "0xB7, 0xBB", 1467 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1468 "MSRIndex": "0x1a6,0x1a7", 1469 "MSRValue": "0x1877", 1470 "SampleAfterValue": "100000", 1471 "UMask": "0x1" 1472 }, 1473 { 1474 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1475 "EventCode": "0xB7, 0xBB", 1476 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1477 "MSRIndex": "0x1a6,0x1a7", 1478 "MSRValue": "0x5877", 1479 "SampleAfterValue": "100000", 1480 "UMask": "0x1" 1481 }, 1482 { 1483 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1484 "EventCode": "0xB7, 0xBB", 1485 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1486 "MSRIndex": "0x1a6,0x1a7", 1487 "MSRValue": "0x1077", 1488 "SampleAfterValue": "100000", 1489 "UMask": "0x1" 1490 }, 1491 { 1492 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1493 "EventCode": "0xB7, 0xBB", 1494 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1495 "MSRIndex": "0x1a6,0x1a7", 1496 "MSRValue": "0x877", 1497 "SampleAfterValue": "100000", 1498 "UMask": "0x1" 1499 }, 1500 { 1501 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1502 "EventCode": "0xB7, 0xBB", 1503 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1504 "MSRIndex": "0x1a6,0x1a7", 1505 "MSRValue": "0x7F33", 1506 "SampleAfterValue": "100000", 1507 "UMask": "0x1" 1508 }, 1509 { 1510 "BriefDescription": "Offcore request = all data, response = any location", 1511 "EventCode": "0xB7, 0xBB", 1512 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1513 "MSRIndex": "0x1a6,0x1a7", 1514 "MSRValue": "0xFF33", 1515 "SampleAfterValue": "100000", 1516 "UMask": "0x1" 1517 }, 1518 { 1519 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1520 "EventCode": "0xB7, 0xBB", 1521 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1522 "MSRIndex": "0x1a6,0x1a7", 1523 "MSRValue": "0x8033", 1524 "SampleAfterValue": "100000", 1525 "UMask": "0x1" 1526 }, 1527 { 1528 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1529 "EventCode": "0xB7, 0xBB", 1530 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1531 "MSRIndex": "0x1a6,0x1a7", 1532 "MSRValue": "0x133", 1533 "SampleAfterValue": "100000", 1534 "UMask": "0x1" 1535 }, 1536 { 1537 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1538 "EventCode": "0xB7, 0xBB", 1539 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1540 "MSRIndex": "0x1a6,0x1a7", 1541 "MSRValue": "0x233", 1542 "SampleAfterValue": "100000", 1543 "UMask": "0x1" 1544 }, 1545 { 1546 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1547 "EventCode": "0xB7, 0xBB", 1548 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1549 "MSRIndex": "0x1a6,0x1a7", 1550 "MSRValue": "0x433", 1551 "SampleAfterValue": "100000", 1552 "UMask": "0x1" 1553 }, 1554 { 1555 "BriefDescription": "Offcore request = all data, response = local cache", 1556 "EventCode": "0xB7, 0xBB", 1557 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1558 "MSRIndex": "0x1a6,0x1a7", 1559 "MSRValue": "0x733", 1560 "SampleAfterValue": "100000", 1561 "UMask": "0x1" 1562 }, 1563 { 1564 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1565 "EventCode": "0xB7, 0xBB", 1566 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1567 "MSRIndex": "0x1a6,0x1a7", 1568 "MSRValue": "0x2733", 1569 "SampleAfterValue": "100000", 1570 "UMask": "0x1" 1571 }, 1572 { 1573 "BriefDescription": "Offcore request = all data, response = remote cache", 1574 "EventCode": "0xB7, 0xBB", 1575 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1576 "MSRIndex": "0x1a6,0x1a7", 1577 "MSRValue": "0x1833", 1578 "SampleAfterValue": "100000", 1579 "UMask": "0x1" 1580 }, 1581 { 1582 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1583 "EventCode": "0xB7, 0xBB", 1584 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1585 "MSRIndex": "0x1a6,0x1a7", 1586 "MSRValue": "0x5833", 1587 "SampleAfterValue": "100000", 1588 "UMask": "0x1" 1589 }, 1590 { 1591 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1592 "EventCode": "0xB7, 0xBB", 1593 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1594 "MSRIndex": "0x1a6,0x1a7", 1595 "MSRValue": "0x1033", 1596 "SampleAfterValue": "100000", 1597 "UMask": "0x1" 1598 }, 1599 { 1600 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1601 "EventCode": "0xB7, 0xBB", 1602 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1603 "MSRIndex": "0x1a6,0x1a7", 1604 "MSRValue": "0x833", 1605 "SampleAfterValue": "100000", 1606 "UMask": "0x1" 1607 }, 1608 { 1609 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1610 "EventCode": "0xB7, 0xBB", 1611 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1612 "MSRIndex": "0x1a6,0x1a7", 1613 "MSRValue": "0x7F03", 1614 "SampleAfterValue": "100000", 1615 "UMask": "0x1" 1616 }, 1617 { 1618 "BriefDescription": "All offcore demand data requests", 1619 "EventCode": "0xB7, 0xBB", 1620 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1621 "MSRIndex": "0x1a6,0x1a7", 1622 "MSRValue": "0xFF03", 1623 "SampleAfterValue": "100000", 1624 "UMask": "0x1" 1625 }, 1626 { 1627 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1628 "EventCode": "0xB7, 0xBB", 1629 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1630 "MSRIndex": "0x1a6,0x1a7", 1631 "MSRValue": "0x8003", 1632 "SampleAfterValue": "100000", 1633 "UMask": "0x1" 1634 }, 1635 { 1636 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1637 "EventCode": "0xB7, 0xBB", 1638 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1639 "MSRIndex": "0x1a6,0x1a7", 1640 "MSRValue": "0x103", 1641 "SampleAfterValue": "100000", 1642 "UMask": "0x1" 1643 }, 1644 { 1645 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1646 "EventCode": "0xB7, 0xBB", 1647 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1648 "MSRIndex": "0x1a6,0x1a7", 1649 "MSRValue": "0x203", 1650 "SampleAfterValue": "100000", 1651 "UMask": "0x1" 1652 }, 1653 { 1654 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1655 "EventCode": "0xB7, 0xBB", 1656 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1657 "MSRIndex": "0x1a6,0x1a7", 1658 "MSRValue": "0x403", 1659 "SampleAfterValue": "100000", 1660 "UMask": "0x1" 1661 }, 1662 { 1663 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1664 "EventCode": "0xB7, 0xBB", 1665 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1666 "MSRIndex": "0x1a6,0x1a7", 1667 "MSRValue": "0x703", 1668 "SampleAfterValue": "100000", 1669 "UMask": "0x1" 1670 }, 1671 { 1672 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1673 "EventCode": "0xB7, 0xBB", 1674 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1675 "MSRIndex": "0x1a6,0x1a7", 1676 "MSRValue": "0x2703", 1677 "SampleAfterValue": "100000", 1678 "UMask": "0x1" 1679 }, 1680 { 1681 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1682 "EventCode": "0xB7, 0xBB", 1683 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1684 "MSRIndex": "0x1a6,0x1a7", 1685 "MSRValue": "0x1803", 1686 "SampleAfterValue": "100000", 1687 "UMask": "0x1" 1688 }, 1689 { 1690 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1691 "EventCode": "0xB7, 0xBB", 1692 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1693 "MSRIndex": "0x1a6,0x1a7", 1694 "MSRValue": "0x5803", 1695 "SampleAfterValue": "100000", 1696 "UMask": "0x1" 1697 }, 1698 { 1699 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1700 "EventCode": "0xB7, 0xBB", 1701 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1702 "MSRIndex": "0x1a6,0x1a7", 1703 "MSRValue": "0x1003", 1704 "SampleAfterValue": "100000", 1705 "UMask": "0x1" 1706 }, 1707 { 1708 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1709 "EventCode": "0xB7, 0xBB", 1710 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1711 "MSRIndex": "0x1a6,0x1a7", 1712 "MSRValue": "0x803", 1713 "SampleAfterValue": "100000", 1714 "UMask": "0x1" 1715 }, 1716 { 1717 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1718 "EventCode": "0xB7, 0xBB", 1719 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1720 "MSRIndex": "0x1a6,0x1a7", 1721 "MSRValue": "0x7F01", 1722 "SampleAfterValue": "100000", 1723 "UMask": "0x1" 1724 }, 1725 { 1726 "BriefDescription": "All offcore demand data reads", 1727 "EventCode": "0xB7, 0xBB", 1728 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1729 "MSRIndex": "0x1a6,0x1a7", 1730 "MSRValue": "0xFF01", 1731 "SampleAfterValue": "100000", 1732 "UMask": "0x1" 1733 }, 1734 { 1735 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1736 "EventCode": "0xB7, 0xBB", 1737 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1738 "MSRIndex": "0x1a6,0x1a7", 1739 "MSRValue": "0x8001", 1740 "SampleAfterValue": "100000", 1741 "UMask": "0x1" 1742 }, 1743 { 1744 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1745 "EventCode": "0xB7, 0xBB", 1746 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1747 "MSRIndex": "0x1a6,0x1a7", 1748 "MSRValue": "0x101", 1749 "SampleAfterValue": "100000", 1750 "UMask": "0x1" 1751 }, 1752 { 1753 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1754 "EventCode": "0xB7, 0xBB", 1755 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1756 "MSRIndex": "0x1a6,0x1a7", 1757 "MSRValue": "0x201", 1758 "SampleAfterValue": "100000", 1759 "UMask": "0x1" 1760 }, 1761 { 1762 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 1763 "EventCode": "0xB7, 0xBB", 1764 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1765 "MSRIndex": "0x1a6,0x1a7", 1766 "MSRValue": "0x401", 1767 "SampleAfterValue": "100000", 1768 "UMask": "0x1" 1769 }, 1770 { 1771 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 1772 "EventCode": "0xB7, 0xBB", 1773 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1774 "MSRIndex": "0x1a6,0x1a7", 1775 "MSRValue": "0x701", 1776 "SampleAfterValue": "100000", 1777 "UMask": "0x1" 1778 }, 1779 { 1780 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 1781 "EventCode": "0xB7, 0xBB", 1782 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 1783 "MSRIndex": "0x1a6,0x1a7", 1784 "MSRValue": "0x2701", 1785 "SampleAfterValue": "100000", 1786 "UMask": "0x1" 1787 }, 1788 { 1789 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 1790 "EventCode": "0xB7, 0xBB", 1791 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 1792 "MSRIndex": "0x1a6,0x1a7", 1793 "MSRValue": "0x1801", 1794 "SampleAfterValue": "100000", 1795 "UMask": "0x1" 1796 }, 1797 { 1798 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 1799 "EventCode": "0xB7, 0xBB", 1800 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 1801 "MSRIndex": "0x1a6,0x1a7", 1802 "MSRValue": "0x5801", 1803 "SampleAfterValue": "100000", 1804 "UMask": "0x1" 1805 }, 1806 { 1807 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 1808 "EventCode": "0xB7, 0xBB", 1809 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 1810 "MSRIndex": "0x1a6,0x1a7", 1811 "MSRValue": "0x1001", 1812 "SampleAfterValue": "100000", 1813 "UMask": "0x1" 1814 }, 1815 { 1816 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 1817 "EventCode": "0xB7, 0xBB", 1818 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 1819 "MSRIndex": "0x1a6,0x1a7", 1820 "MSRValue": "0x801", 1821 "SampleAfterValue": "100000", 1822 "UMask": "0x1" 1823 }, 1824 { 1825 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 1826 "EventCode": "0xB7, 0xBB", 1827 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 1828 "MSRIndex": "0x1a6,0x1a7", 1829 "MSRValue": "0x7F04", 1830 "SampleAfterValue": "100000", 1831 "UMask": "0x1" 1832 }, 1833 { 1834 "BriefDescription": "All offcore demand code reads", 1835 "EventCode": "0xB7, 0xBB", 1836 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 1837 "MSRIndex": "0x1a6,0x1a7", 1838 "MSRValue": "0xFF04", 1839 "SampleAfterValue": "100000", 1840 "UMask": "0x1" 1841 }, 1842 { 1843 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 1844 "EventCode": "0xB7, 0xBB", 1845 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 1846 "MSRIndex": "0x1a6,0x1a7", 1847 "MSRValue": "0x8004", 1848 "SampleAfterValue": "100000", 1849 "UMask": "0x1" 1850 }, 1851 { 1852 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 1853 "EventCode": "0xB7, 0xBB", 1854 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 1855 "MSRIndex": "0x1a6,0x1a7", 1856 "MSRValue": "0x104", 1857 "SampleAfterValue": "100000", 1858 "UMask": "0x1" 1859 }, 1860 { 1861 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 1862 "EventCode": "0xB7, 0xBB", 1863 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1864 "MSRIndex": "0x1a6,0x1a7", 1865 "MSRValue": "0x204", 1866 "SampleAfterValue": "100000", 1867 "UMask": "0x1" 1868 }, 1869 { 1870 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 1871 "EventCode": "0xB7, 0xBB", 1872 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1873 "MSRIndex": "0x1a6,0x1a7", 1874 "MSRValue": "0x404", 1875 "SampleAfterValue": "100000", 1876 "UMask": "0x1" 1877 }, 1878 { 1879 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 1880 "EventCode": "0xB7, 0xBB", 1881 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 1882 "MSRIndex": "0x1a6,0x1a7", 1883 "MSRValue": "0x704", 1884 "SampleAfterValue": "100000", 1885 "UMask": "0x1" 1886 }, 1887 { 1888 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 1889 "EventCode": "0xB7, 0xBB", 1890 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 1891 "MSRIndex": "0x1a6,0x1a7", 1892 "MSRValue": "0x2704", 1893 "SampleAfterValue": "100000", 1894 "UMask": "0x1" 1895 }, 1896 { 1897 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 1898 "EventCode": "0xB7, 0xBB", 1899 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 1900 "MSRIndex": "0x1a6,0x1a7", 1901 "MSRValue": "0x1804", 1902 "SampleAfterValue": "100000", 1903 "UMask": "0x1" 1904 }, 1905 { 1906 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 1907 "EventCode": "0xB7, 0xBB", 1908 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 1909 "MSRIndex": "0x1a6,0x1a7", 1910 "MSRValue": "0x5804", 1911 "SampleAfterValue": "100000", 1912 "UMask": "0x1" 1913 }, 1914 { 1915 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 1916 "EventCode": "0xB7, 0xBB", 1917 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 1918 "MSRIndex": "0x1a6,0x1a7", 1919 "MSRValue": "0x1004", 1920 "SampleAfterValue": "100000", 1921 "UMask": "0x1" 1922 }, 1923 { 1924 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 1925 "EventCode": "0xB7, 0xBB", 1926 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 1927 "MSRIndex": "0x1a6,0x1a7", 1928 "MSRValue": "0x804", 1929 "SampleAfterValue": "100000", 1930 "UMask": "0x1" 1931 }, 1932 { 1933 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 1934 "EventCode": "0xB7, 0xBB", 1935 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 1936 "MSRIndex": "0x1a6,0x1a7", 1937 "MSRValue": "0x7F02", 1938 "SampleAfterValue": "100000", 1939 "UMask": "0x1" 1940 }, 1941 { 1942 "BriefDescription": "All offcore demand RFO requests", 1943 "EventCode": "0xB7, 0xBB", 1944 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 1945 "MSRIndex": "0x1a6,0x1a7", 1946 "MSRValue": "0xFF02", 1947 "SampleAfterValue": "100000", 1948 "UMask": "0x1" 1949 }, 1950 { 1951 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 1952 "EventCode": "0xB7, 0xBB", 1953 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 1954 "MSRIndex": "0x1a6,0x1a7", 1955 "MSRValue": "0x8002", 1956 "SampleAfterValue": "100000", 1957 "UMask": "0x1" 1958 }, 1959 { 1960 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 1961 "EventCode": "0xB7, 0xBB", 1962 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 1963 "MSRIndex": "0x1a6,0x1a7", 1964 "MSRValue": "0x102", 1965 "SampleAfterValue": "100000", 1966 "UMask": "0x1" 1967 }, 1968 { 1969 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 1970 "EventCode": "0xB7, 0xBB", 1971 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 1972 "MSRIndex": "0x1a6,0x1a7", 1973 "MSRValue": "0x202", 1974 "SampleAfterValue": "100000", 1975 "UMask": "0x1" 1976 }, 1977 { 1978 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 1979 "EventCode": "0xB7, 0xBB", 1980 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 1981 "MSRIndex": "0x1a6,0x1a7", 1982 "MSRValue": "0x402", 1983 "SampleAfterValue": "100000", 1984 "UMask": "0x1" 1985 }, 1986 { 1987 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 1988 "EventCode": "0xB7, 0xBB", 1989 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 1990 "MSRIndex": "0x1a6,0x1a7", 1991 "MSRValue": "0x702", 1992 "SampleAfterValue": "100000", 1993 "UMask": "0x1" 1994 }, 1995 { 1996 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 1997 "EventCode": "0xB7, 0xBB", 1998 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 1999 "MSRIndex": "0x1a6,0x1a7", 2000 "MSRValue": "0x2702", 2001 "SampleAfterValue": "100000", 2002 "UMask": "0x1" 2003 }, 2004 { 2005 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2006 "EventCode": "0xB7, 0xBB", 2007 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2008 "MSRIndex": "0x1a6,0x1a7", 2009 "MSRValue": "0x1802", 2010 "SampleAfterValue": "100000", 2011 "UMask": "0x1" 2012 }, 2013 { 2014 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2015 "EventCode": "0xB7, 0xBB", 2016 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2017 "MSRIndex": "0x1a6,0x1a7", 2018 "MSRValue": "0x5802", 2019 "SampleAfterValue": "100000", 2020 "UMask": "0x1" 2021 }, 2022 { 2023 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2024 "EventCode": "0xB7, 0xBB", 2025 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2026 "MSRIndex": "0x1a6,0x1a7", 2027 "MSRValue": "0x1002", 2028 "SampleAfterValue": "100000", 2029 "UMask": "0x1" 2030 }, 2031 { 2032 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2033 "EventCode": "0xB7, 0xBB", 2034 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2035 "MSRIndex": "0x1a6,0x1a7", 2036 "MSRValue": "0x802", 2037 "SampleAfterValue": "100000", 2038 "UMask": "0x1" 2039 }, 2040 { 2041 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2042 "EventCode": "0xB7, 0xBB", 2043 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2044 "MSRIndex": "0x1a6,0x1a7", 2045 "MSRValue": "0x7F80", 2046 "SampleAfterValue": "100000", 2047 "UMask": "0x1" 2048 }, 2049 { 2050 "BriefDescription": "All offcore other requests", 2051 "EventCode": "0xB7, 0xBB", 2052 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2053 "MSRIndex": "0x1a6,0x1a7", 2054 "MSRValue": "0xFF80", 2055 "SampleAfterValue": "100000", 2056 "UMask": "0x1" 2057 }, 2058 { 2059 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2060 "EventCode": "0xB7, 0xBB", 2061 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2062 "MSRIndex": "0x1a6,0x1a7", 2063 "MSRValue": "0x8080", 2064 "SampleAfterValue": "100000", 2065 "UMask": "0x1" 2066 }, 2067 { 2068 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2069 "EventCode": "0xB7, 0xBB", 2070 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2071 "MSRIndex": "0x1a6,0x1a7", 2072 "MSRValue": "0x180", 2073 "SampleAfterValue": "100000", 2074 "UMask": "0x1" 2075 }, 2076 { 2077 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2078 "EventCode": "0xB7, 0xBB", 2079 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2080 "MSRIndex": "0x1a6,0x1a7", 2081 "MSRValue": "0x280", 2082 "SampleAfterValue": "100000", 2083 "UMask": "0x1" 2084 }, 2085 { 2086 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2087 "EventCode": "0xB7, 0xBB", 2088 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2089 "MSRIndex": "0x1a6,0x1a7", 2090 "MSRValue": "0x480", 2091 "SampleAfterValue": "100000", 2092 "UMask": "0x1" 2093 }, 2094 { 2095 "BriefDescription": "Offcore other requests satisfied by the LLC", 2096 "EventCode": "0xB7, 0xBB", 2097 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2098 "MSRIndex": "0x1a6,0x1a7", 2099 "MSRValue": "0x780", 2100 "SampleAfterValue": "100000", 2101 "UMask": "0x1" 2102 }, 2103 { 2104 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2105 "EventCode": "0xB7, 0xBB", 2106 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2107 "MSRIndex": "0x1a6,0x1a7", 2108 "MSRValue": "0x2780", 2109 "SampleAfterValue": "100000", 2110 "UMask": "0x1" 2111 }, 2112 { 2113 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2114 "EventCode": "0xB7, 0xBB", 2115 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2116 "MSRIndex": "0x1a6,0x1a7", 2117 "MSRValue": "0x1880", 2118 "SampleAfterValue": "100000", 2119 "UMask": "0x1" 2120 }, 2121 { 2122 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2123 "EventCode": "0xB7, 0xBB", 2124 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2125 "MSRIndex": "0x1a6,0x1a7", 2126 "MSRValue": "0x5880", 2127 "SampleAfterValue": "100000", 2128 "UMask": "0x1" 2129 }, 2130 { 2131 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2132 "EventCode": "0xB7, 0xBB", 2133 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2134 "MSRIndex": "0x1a6,0x1a7", 2135 "MSRValue": "0x1080", 2136 "SampleAfterValue": "100000", 2137 "UMask": "0x1" 2138 }, 2139 { 2140 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2141 "EventCode": "0xB7, 0xBB", 2142 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2143 "MSRIndex": "0x1a6,0x1a7", 2144 "MSRValue": "0x880", 2145 "SampleAfterValue": "100000", 2146 "UMask": "0x1" 2147 }, 2148 { 2149 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2150 "EventCode": "0xB7, 0xBB", 2151 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2152 "MSRIndex": "0x1a6,0x1a7", 2153 "MSRValue": "0x7F50", 2154 "SampleAfterValue": "100000", 2155 "UMask": "0x1" 2156 }, 2157 { 2158 "BriefDescription": "All offcore prefetch data requests", 2159 "EventCode": "0xB7, 0xBB", 2160 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2161 "MSRIndex": "0x1a6,0x1a7", 2162 "MSRValue": "0xFF50", 2163 "SampleAfterValue": "100000", 2164 "UMask": "0x1" 2165 }, 2166 { 2167 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2168 "EventCode": "0xB7, 0xBB", 2169 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2170 "MSRIndex": "0x1a6,0x1a7", 2171 "MSRValue": "0x8050", 2172 "SampleAfterValue": "100000", 2173 "UMask": "0x1" 2174 }, 2175 { 2176 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2177 "EventCode": "0xB7, 0xBB", 2178 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2179 "MSRIndex": "0x1a6,0x1a7", 2180 "MSRValue": "0x150", 2181 "SampleAfterValue": "100000", 2182 "UMask": "0x1" 2183 }, 2184 { 2185 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2186 "EventCode": "0xB7, 0xBB", 2187 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2188 "MSRIndex": "0x1a6,0x1a7", 2189 "MSRValue": "0x250", 2190 "SampleAfterValue": "100000", 2191 "UMask": "0x1" 2192 }, 2193 { 2194 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2195 "EventCode": "0xB7, 0xBB", 2196 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2197 "MSRIndex": "0x1a6,0x1a7", 2198 "MSRValue": "0x450", 2199 "SampleAfterValue": "100000", 2200 "UMask": "0x1" 2201 }, 2202 { 2203 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2204 "EventCode": "0xB7, 0xBB", 2205 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2206 "MSRIndex": "0x1a6,0x1a7", 2207 "MSRValue": "0x750", 2208 "SampleAfterValue": "100000", 2209 "UMask": "0x1" 2210 }, 2211 { 2212 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2213 "EventCode": "0xB7, 0xBB", 2214 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2215 "MSRIndex": "0x1a6,0x1a7", 2216 "MSRValue": "0x2750", 2217 "SampleAfterValue": "100000", 2218 "UMask": "0x1" 2219 }, 2220 { 2221 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2222 "EventCode": "0xB7, 0xBB", 2223 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2224 "MSRIndex": "0x1a6,0x1a7", 2225 "MSRValue": "0x1850", 2226 "SampleAfterValue": "100000", 2227 "UMask": "0x1" 2228 }, 2229 { 2230 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2231 "EventCode": "0xB7, 0xBB", 2232 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2233 "MSRIndex": "0x1a6,0x1a7", 2234 "MSRValue": "0x5850", 2235 "SampleAfterValue": "100000", 2236 "UMask": "0x1" 2237 }, 2238 { 2239 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2240 "EventCode": "0xB7, 0xBB", 2241 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2242 "MSRIndex": "0x1a6,0x1a7", 2243 "MSRValue": "0x1050", 2244 "SampleAfterValue": "100000", 2245 "UMask": "0x1" 2246 }, 2247 { 2248 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2249 "EventCode": "0xB7, 0xBB", 2250 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2251 "MSRIndex": "0x1a6,0x1a7", 2252 "MSRValue": "0x850", 2253 "SampleAfterValue": "100000", 2254 "UMask": "0x1" 2255 }, 2256 { 2257 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2258 "EventCode": "0xB7, 0xBB", 2259 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2260 "MSRIndex": "0x1a6,0x1a7", 2261 "MSRValue": "0x7F10", 2262 "SampleAfterValue": "100000", 2263 "UMask": "0x1" 2264 }, 2265 { 2266 "BriefDescription": "All offcore prefetch data reads", 2267 "EventCode": "0xB7, 0xBB", 2268 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2269 "MSRIndex": "0x1a6,0x1a7", 2270 "MSRValue": "0xFF10", 2271 "SampleAfterValue": "100000", 2272 "UMask": "0x1" 2273 }, 2274 { 2275 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2276 "EventCode": "0xB7, 0xBB", 2277 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2278 "MSRIndex": "0x1a6,0x1a7", 2279 "MSRValue": "0x8010", 2280 "SampleAfterValue": "100000", 2281 "UMask": "0x1" 2282 }, 2283 { 2284 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2285 "EventCode": "0xB7, 0xBB", 2286 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2287 "MSRIndex": "0x1a6,0x1a7", 2288 "MSRValue": "0x110", 2289 "SampleAfterValue": "100000", 2290 "UMask": "0x1" 2291 }, 2292 { 2293 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2294 "EventCode": "0xB7, 0xBB", 2295 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2296 "MSRIndex": "0x1a6,0x1a7", 2297 "MSRValue": "0x210", 2298 "SampleAfterValue": "100000", 2299 "UMask": "0x1" 2300 }, 2301 { 2302 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2303 "EventCode": "0xB7, 0xBB", 2304 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2305 "MSRIndex": "0x1a6,0x1a7", 2306 "MSRValue": "0x410", 2307 "SampleAfterValue": "100000", 2308 "UMask": "0x1" 2309 }, 2310 { 2311 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2312 "EventCode": "0xB7, 0xBB", 2313 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2314 "MSRIndex": "0x1a6,0x1a7", 2315 "MSRValue": "0x710", 2316 "SampleAfterValue": "100000", 2317 "UMask": "0x1" 2318 }, 2319 { 2320 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2321 "EventCode": "0xB7, 0xBB", 2322 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2323 "MSRIndex": "0x1a6,0x1a7", 2324 "MSRValue": "0x2710", 2325 "SampleAfterValue": "100000", 2326 "UMask": "0x1" 2327 }, 2328 { 2329 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2330 "EventCode": "0xB7, 0xBB", 2331 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2332 "MSRIndex": "0x1a6,0x1a7", 2333 "MSRValue": "0x1810", 2334 "SampleAfterValue": "100000", 2335 "UMask": "0x1" 2336 }, 2337 { 2338 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2339 "EventCode": "0xB7, 0xBB", 2340 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2341 "MSRIndex": "0x1a6,0x1a7", 2342 "MSRValue": "0x5810", 2343 "SampleAfterValue": "100000", 2344 "UMask": "0x1" 2345 }, 2346 { 2347 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2348 "EventCode": "0xB7, 0xBB", 2349 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2350 "MSRIndex": "0x1a6,0x1a7", 2351 "MSRValue": "0x1010", 2352 "SampleAfterValue": "100000", 2353 "UMask": "0x1" 2354 }, 2355 { 2356 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2357 "EventCode": "0xB7, 0xBB", 2358 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2359 "MSRIndex": "0x1a6,0x1a7", 2360 "MSRValue": "0x810", 2361 "SampleAfterValue": "100000", 2362 "UMask": "0x1" 2363 }, 2364 { 2365 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2366 "EventCode": "0xB7, 0xBB", 2367 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2368 "MSRIndex": "0x1a6,0x1a7", 2369 "MSRValue": "0x7F40", 2370 "SampleAfterValue": "100000", 2371 "UMask": "0x1" 2372 }, 2373 { 2374 "BriefDescription": "All offcore prefetch code reads", 2375 "EventCode": "0xB7, 0xBB", 2376 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2377 "MSRIndex": "0x1a6,0x1a7", 2378 "MSRValue": "0xFF40", 2379 "SampleAfterValue": "100000", 2380 "UMask": "0x1" 2381 }, 2382 { 2383 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2384 "EventCode": "0xB7, 0xBB", 2385 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2386 "MSRIndex": "0x1a6,0x1a7", 2387 "MSRValue": "0x8040", 2388 "SampleAfterValue": "100000", 2389 "UMask": "0x1" 2390 }, 2391 { 2392 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2393 "EventCode": "0xB7, 0xBB", 2394 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2395 "MSRIndex": "0x1a6,0x1a7", 2396 "MSRValue": "0x140", 2397 "SampleAfterValue": "100000", 2398 "UMask": "0x1" 2399 }, 2400 { 2401 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2402 "EventCode": "0xB7, 0xBB", 2403 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2404 "MSRIndex": "0x1a6,0x1a7", 2405 "MSRValue": "0x240", 2406 "SampleAfterValue": "100000", 2407 "UMask": "0x1" 2408 }, 2409 { 2410 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2411 "EventCode": "0xB7, 0xBB", 2412 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2413 "MSRIndex": "0x1a6,0x1a7", 2414 "MSRValue": "0x440", 2415 "SampleAfterValue": "100000", 2416 "UMask": "0x1" 2417 }, 2418 { 2419 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2420 "EventCode": "0xB7, 0xBB", 2421 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2422 "MSRIndex": "0x1a6,0x1a7", 2423 "MSRValue": "0x740", 2424 "SampleAfterValue": "100000", 2425 "UMask": "0x1" 2426 }, 2427 { 2428 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2429 "EventCode": "0xB7, 0xBB", 2430 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2431 "MSRIndex": "0x1a6,0x1a7", 2432 "MSRValue": "0x2740", 2433 "SampleAfterValue": "100000", 2434 "UMask": "0x1" 2435 }, 2436 { 2437 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2438 "EventCode": "0xB7, 0xBB", 2439 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2440 "MSRIndex": "0x1a6,0x1a7", 2441 "MSRValue": "0x1840", 2442 "SampleAfterValue": "100000", 2443 "UMask": "0x1" 2444 }, 2445 { 2446 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2447 "EventCode": "0xB7, 0xBB", 2448 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2449 "MSRIndex": "0x1a6,0x1a7", 2450 "MSRValue": "0x5840", 2451 "SampleAfterValue": "100000", 2452 "UMask": "0x1" 2453 }, 2454 { 2455 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2456 "EventCode": "0xB7, 0xBB", 2457 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2458 "MSRIndex": "0x1a6,0x1a7", 2459 "MSRValue": "0x1040", 2460 "SampleAfterValue": "100000", 2461 "UMask": "0x1" 2462 }, 2463 { 2464 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2465 "EventCode": "0xB7, 0xBB", 2466 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2467 "MSRIndex": "0x1a6,0x1a7", 2468 "MSRValue": "0x840", 2469 "SampleAfterValue": "100000", 2470 "UMask": "0x1" 2471 }, 2472 { 2473 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2474 "EventCode": "0xB7, 0xBB", 2475 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2476 "MSRIndex": "0x1a6,0x1a7", 2477 "MSRValue": "0x7F20", 2478 "SampleAfterValue": "100000", 2479 "UMask": "0x1" 2480 }, 2481 { 2482 "BriefDescription": "All offcore prefetch RFO requests", 2483 "EventCode": "0xB7, 0xBB", 2484 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2485 "MSRIndex": "0x1a6,0x1a7", 2486 "MSRValue": "0xFF20", 2487 "SampleAfterValue": "100000", 2488 "UMask": "0x1" 2489 }, 2490 { 2491 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2492 "EventCode": "0xB7, 0xBB", 2493 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2494 "MSRIndex": "0x1a6,0x1a7", 2495 "MSRValue": "0x8020", 2496 "SampleAfterValue": "100000", 2497 "UMask": "0x1" 2498 }, 2499 { 2500 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2501 "EventCode": "0xB7, 0xBB", 2502 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2503 "MSRIndex": "0x1a6,0x1a7", 2504 "MSRValue": "0x120", 2505 "SampleAfterValue": "100000", 2506 "UMask": "0x1" 2507 }, 2508 { 2509 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2510 "EventCode": "0xB7, 0xBB", 2511 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2512 "MSRIndex": "0x1a6,0x1a7", 2513 "MSRValue": "0x220", 2514 "SampleAfterValue": "100000", 2515 "UMask": "0x1" 2516 }, 2517 { 2518 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2519 "EventCode": "0xB7, 0xBB", 2520 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2521 "MSRIndex": "0x1a6,0x1a7", 2522 "MSRValue": "0x420", 2523 "SampleAfterValue": "100000", 2524 "UMask": "0x1" 2525 }, 2526 { 2527 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2528 "EventCode": "0xB7, 0xBB", 2529 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2530 "MSRIndex": "0x1a6,0x1a7", 2531 "MSRValue": "0x720", 2532 "SampleAfterValue": "100000", 2533 "UMask": "0x1" 2534 }, 2535 { 2536 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2537 "EventCode": "0xB7, 0xBB", 2538 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2539 "MSRIndex": "0x1a6,0x1a7", 2540 "MSRValue": "0x2720", 2541 "SampleAfterValue": "100000", 2542 "UMask": "0x1" 2543 }, 2544 { 2545 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2546 "EventCode": "0xB7, 0xBB", 2547 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2548 "MSRIndex": "0x1a6,0x1a7", 2549 "MSRValue": "0x1820", 2550 "SampleAfterValue": "100000", 2551 "UMask": "0x1" 2552 }, 2553 { 2554 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2555 "EventCode": "0xB7, 0xBB", 2556 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2557 "MSRIndex": "0x1a6,0x1a7", 2558 "MSRValue": "0x5820", 2559 "SampleAfterValue": "100000", 2560 "UMask": "0x1" 2561 }, 2562 { 2563 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2564 "EventCode": "0xB7, 0xBB", 2565 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2566 "MSRIndex": "0x1a6,0x1a7", 2567 "MSRValue": "0x1020", 2568 "SampleAfterValue": "100000", 2569 "UMask": "0x1" 2570 }, 2571 { 2572 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2573 "EventCode": "0xB7, 0xBB", 2574 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2575 "MSRIndex": "0x1a6,0x1a7", 2576 "MSRValue": "0x820", 2577 "SampleAfterValue": "100000", 2578 "UMask": "0x1" 2579 }, 2580 { 2581 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2582 "EventCode": "0xB7, 0xBB", 2583 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2584 "MSRIndex": "0x1a6,0x1a7", 2585 "MSRValue": "0x7F70", 2586 "SampleAfterValue": "100000", 2587 "UMask": "0x1" 2588 }, 2589 { 2590 "BriefDescription": "All offcore prefetch requests", 2591 "EventCode": "0xB7, 0xBB", 2592 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2593 "MSRIndex": "0x1a6,0x1a7", 2594 "MSRValue": "0xFF70", 2595 "SampleAfterValue": "100000", 2596 "UMask": "0x1" 2597 }, 2598 { 2599 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2600 "EventCode": "0xB7, 0xBB", 2601 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2602 "MSRIndex": "0x1a6,0x1a7", 2603 "MSRValue": "0x8070", 2604 "SampleAfterValue": "100000", 2605 "UMask": "0x1" 2606 }, 2607 { 2608 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2609 "EventCode": "0xB7, 0xBB", 2610 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2611 "MSRIndex": "0x1a6,0x1a7", 2612 "MSRValue": "0x170", 2613 "SampleAfterValue": "100000", 2614 "UMask": "0x1" 2615 }, 2616 { 2617 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2618 "EventCode": "0xB7, 0xBB", 2619 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2620 "MSRIndex": "0x1a6,0x1a7", 2621 "MSRValue": "0x270", 2622 "SampleAfterValue": "100000", 2623 "UMask": "0x1" 2624 }, 2625 { 2626 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2627 "EventCode": "0xB7, 0xBB", 2628 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2629 "MSRIndex": "0x1a6,0x1a7", 2630 "MSRValue": "0x470", 2631 "SampleAfterValue": "100000", 2632 "UMask": "0x1" 2633 }, 2634 { 2635 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2636 "EventCode": "0xB7, 0xBB", 2637 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2638 "MSRIndex": "0x1a6,0x1a7", 2639 "MSRValue": "0x770", 2640 "SampleAfterValue": "100000", 2641 "UMask": "0x1" 2642 }, 2643 { 2644 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2645 "EventCode": "0xB7, 0xBB", 2646 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2647 "MSRIndex": "0x1a6,0x1a7", 2648 "MSRValue": "0x2770", 2649 "SampleAfterValue": "100000", 2650 "UMask": "0x1" 2651 }, 2652 { 2653 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2654 "EventCode": "0xB7, 0xBB", 2655 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 2656 "MSRIndex": "0x1a6,0x1a7", 2657 "MSRValue": "0x1870", 2658 "SampleAfterValue": "100000", 2659 "UMask": "0x1" 2660 }, 2661 { 2662 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 2663 "EventCode": "0xB7, 0xBB", 2664 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 2665 "MSRIndex": "0x1a6,0x1a7", 2666 "MSRValue": "0x5870", 2667 "SampleAfterValue": "100000", 2668 "UMask": "0x1" 2669 }, 2670 { 2671 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 2672 "EventCode": "0xB7, 0xBB", 2673 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 2674 "MSRIndex": "0x1a6,0x1a7", 2675 "MSRValue": "0x1070", 2676 "SampleAfterValue": "100000", 2677 "UMask": "0x1" 2678 }, 2679 { 2680 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 2681 "EventCode": "0xB7, 0xBB", 2682 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 2683 "MSRIndex": "0x1a6,0x1a7", 2684 "MSRValue": "0x870", 2685 "SampleAfterValue": "100000", 2686 "UMask": "0x1" 2687 }, 2688 { 2689 "BriefDescription": "Super Queue LRU hints sent to LLC", 2690 "EventCode": "0xF4", 2691 "EventName": "SQ_MISC.LRU_HINTS", 2692 "SampleAfterValue": "2000000", 2693 "UMask": "0x4" 2694 }, 2695 { 2696 "BriefDescription": "Super Queue lock splits across a cache line", 2697 "EventCode": "0xF4", 2698 "EventName": "SQ_MISC.SPLIT_LOCK", 2699 "SampleAfterValue": "2000000", 2700 "UMask": "0x10" 2701 }, 2702 { 2703 "BriefDescription": "Loads delayed with at-Retirement block code", 2704 "EventCode": "0x6", 2705 "EventName": "STORE_BLOCKS.AT_RET", 2706 "SampleAfterValue": "200000", 2707 "UMask": "0x4" 2708 }, 2709 { 2710 "BriefDescription": "Cacheable loads delayed with L1D block code", 2711 "EventCode": "0x6", 2712 "EventName": "STORE_BLOCKS.L1D_BLOCK", 2713 "SampleAfterValue": "200000", 2714 "UMask": "0x8" 2715 } 2716] 2717