1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 52 "Counter": "0,1", 53 "EventCode": "0x52", 54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1D hardware prefetch misses", 60 "Counter": "0,1", 61 "EventCode": "0x4E", 62 "EventName": "L1D_PREFETCH.MISS", 63 "SampleAfterValue": "200000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1D hardware prefetch requests", 68 "Counter": "0,1", 69 "EventCode": "0x4E", 70 "EventName": "L1D_PREFETCH.REQUESTS", 71 "SampleAfterValue": "200000", 72 "UMask": "0x1" 73 }, 74 { 75 "BriefDescription": "L1D hardware prefetch requests triggered", 76 "Counter": "0,1", 77 "EventCode": "0x4E", 78 "EventName": "L1D_PREFETCH.TRIGGERS", 79 "SampleAfterValue": "200000", 80 "UMask": "0x4" 81 }, 82 { 83 "BriefDescription": "L1 writebacks to L2 in E state", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x28", 86 "EventName": "L1D_WB_L2.E_STATE", 87 "SampleAfterValue": "100000", 88 "UMask": "0x4" 89 }, 90 { 91 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 92 "Counter": "0,1,2,3", 93 "EventCode": "0x28", 94 "EventName": "L1D_WB_L2.I_STATE", 95 "SampleAfterValue": "100000", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "All L1 writebacks to L2", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x28", 102 "EventName": "L1D_WB_L2.MESI", 103 "SampleAfterValue": "100000", 104 "UMask": "0xf" 105 }, 106 { 107 "BriefDescription": "L1 writebacks to L2 in M state", 108 "Counter": "0,1,2,3", 109 "EventCode": "0x28", 110 "EventName": "L1D_WB_L2.M_STATE", 111 "SampleAfterValue": "100000", 112 "UMask": "0x8" 113 }, 114 { 115 "BriefDescription": "L1 writebacks to L2 in S state", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x28", 118 "EventName": "L1D_WB_L2.S_STATE", 119 "SampleAfterValue": "100000", 120 "UMask": "0x2" 121 }, 122 { 123 "BriefDescription": "All L2 data requests", 124 "Counter": "0,1,2,3", 125 "EventCode": "0x26", 126 "EventName": "L2_DATA_RQSTS.ANY", 127 "SampleAfterValue": "200000", 128 "UMask": "0xff" 129 }, 130 { 131 "BriefDescription": "L2 data demand loads in E state", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x26", 134 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 135 "SampleAfterValue": "200000", 136 "UMask": "0x4" 137 }, 138 { 139 "BriefDescription": "L2 data demand loads in I state (misses)", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x26", 142 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 143 "SampleAfterValue": "200000", 144 "UMask": "0x1" 145 }, 146 { 147 "BriefDescription": "L2 data demand requests", 148 "Counter": "0,1,2,3", 149 "EventCode": "0x26", 150 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 151 "SampleAfterValue": "200000", 152 "UMask": "0xf" 153 }, 154 { 155 "BriefDescription": "L2 data demand loads in M state", 156 "Counter": "0,1,2,3", 157 "EventCode": "0x26", 158 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 159 "SampleAfterValue": "200000", 160 "UMask": "0x8" 161 }, 162 { 163 "BriefDescription": "L2 data demand loads in S state", 164 "Counter": "0,1,2,3", 165 "EventCode": "0x26", 166 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 167 "SampleAfterValue": "200000", 168 "UMask": "0x2" 169 }, 170 { 171 "BriefDescription": "L2 data prefetches in E state", 172 "Counter": "0,1,2,3", 173 "EventCode": "0x26", 174 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 175 "SampleAfterValue": "200000", 176 "UMask": "0x40" 177 }, 178 { 179 "BriefDescription": "L2 data prefetches in the I state (misses)", 180 "Counter": "0,1,2,3", 181 "EventCode": "0x26", 182 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 183 "SampleAfterValue": "200000", 184 "UMask": "0x10" 185 }, 186 { 187 "BriefDescription": "All L2 data prefetches", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x26", 190 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 191 "SampleAfterValue": "200000", 192 "UMask": "0xf0" 193 }, 194 { 195 "BriefDescription": "L2 data prefetches in M state", 196 "Counter": "0,1,2,3", 197 "EventCode": "0x26", 198 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 199 "SampleAfterValue": "200000", 200 "UMask": "0x80" 201 }, 202 { 203 "BriefDescription": "L2 data prefetches in the S state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x26", 206 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 207 "SampleAfterValue": "200000", 208 "UMask": "0x20" 209 }, 210 { 211 "BriefDescription": "L2 lines alloacated", 212 "Counter": "0,1,2,3", 213 "EventCode": "0xF1", 214 "EventName": "L2_LINES_IN.ANY", 215 "SampleAfterValue": "100000", 216 "UMask": "0x7" 217 }, 218 { 219 "BriefDescription": "L2 lines allocated in the E state", 220 "Counter": "0,1,2,3", 221 "EventCode": "0xF1", 222 "EventName": "L2_LINES_IN.E_STATE", 223 "SampleAfterValue": "100000", 224 "UMask": "0x4" 225 }, 226 { 227 "BriefDescription": "L2 lines allocated in the S state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0xF1", 230 "EventName": "L2_LINES_IN.S_STATE", 231 "SampleAfterValue": "100000", 232 "UMask": "0x2" 233 }, 234 { 235 "BriefDescription": "L2 lines evicted", 236 "Counter": "0,1,2,3", 237 "EventCode": "0xF2", 238 "EventName": "L2_LINES_OUT.ANY", 239 "SampleAfterValue": "100000", 240 "UMask": "0xf" 241 }, 242 { 243 "BriefDescription": "L2 lines evicted by a demand request", 244 "Counter": "0,1,2,3", 245 "EventCode": "0xF2", 246 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 247 "SampleAfterValue": "100000", 248 "UMask": "0x1" 249 }, 250 { 251 "BriefDescription": "L2 modified lines evicted by a demand request", 252 "Counter": "0,1,2,3", 253 "EventCode": "0xF2", 254 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 255 "SampleAfterValue": "100000", 256 "UMask": "0x2" 257 }, 258 { 259 "BriefDescription": "L2 lines evicted by a prefetch request", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xF2", 262 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 263 "SampleAfterValue": "100000", 264 "UMask": "0x4" 265 }, 266 { 267 "BriefDescription": "L2 modified lines evicted by a prefetch request", 268 "Counter": "0,1,2,3", 269 "EventCode": "0xF2", 270 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 271 "SampleAfterValue": "100000", 272 "UMask": "0x8" 273 }, 274 { 275 "BriefDescription": "L2 instruction fetches", 276 "Counter": "0,1,2,3", 277 "EventCode": "0x24", 278 "EventName": "L2_RQSTS.IFETCHES", 279 "SampleAfterValue": "200000", 280 "UMask": "0x30" 281 }, 282 { 283 "BriefDescription": "L2 instruction fetch hits", 284 "Counter": "0,1,2,3", 285 "EventCode": "0x24", 286 "EventName": "L2_RQSTS.IFETCH_HIT", 287 "SampleAfterValue": "200000", 288 "UMask": "0x10" 289 }, 290 { 291 "BriefDescription": "L2 instruction fetch misses", 292 "Counter": "0,1,2,3", 293 "EventCode": "0x24", 294 "EventName": "L2_RQSTS.IFETCH_MISS", 295 "SampleAfterValue": "200000", 296 "UMask": "0x20" 297 }, 298 { 299 "BriefDescription": "L2 load hits", 300 "Counter": "0,1,2,3", 301 "EventCode": "0x24", 302 "EventName": "L2_RQSTS.LD_HIT", 303 "SampleAfterValue": "200000", 304 "UMask": "0x1" 305 }, 306 { 307 "BriefDescription": "L2 load misses", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x24", 310 "EventName": "L2_RQSTS.LD_MISS", 311 "SampleAfterValue": "200000", 312 "UMask": "0x2" 313 }, 314 { 315 "BriefDescription": "L2 requests", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x24", 318 "EventName": "L2_RQSTS.LOADS", 319 "SampleAfterValue": "200000", 320 "UMask": "0x3" 321 }, 322 { 323 "BriefDescription": "All L2 misses", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x24", 326 "EventName": "L2_RQSTS.MISS", 327 "SampleAfterValue": "200000", 328 "UMask": "0xaa" 329 }, 330 { 331 "BriefDescription": "All L2 prefetches", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x24", 334 "EventName": "L2_RQSTS.PREFETCHES", 335 "SampleAfterValue": "200000", 336 "UMask": "0xc0" 337 }, 338 { 339 "BriefDescription": "L2 prefetch hits", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x24", 342 "EventName": "L2_RQSTS.PREFETCH_HIT", 343 "SampleAfterValue": "200000", 344 "UMask": "0x40" 345 }, 346 { 347 "BriefDescription": "L2 prefetch misses", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x24", 350 "EventName": "L2_RQSTS.PREFETCH_MISS", 351 "SampleAfterValue": "200000", 352 "UMask": "0x80" 353 }, 354 { 355 "BriefDescription": "All L2 requests", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x24", 358 "EventName": "L2_RQSTS.REFERENCES", 359 "SampleAfterValue": "200000", 360 "UMask": "0xff" 361 }, 362 { 363 "BriefDescription": "L2 RFO requests", 364 "Counter": "0,1,2,3", 365 "EventCode": "0x24", 366 "EventName": "L2_RQSTS.RFOS", 367 "SampleAfterValue": "200000", 368 "UMask": "0xc" 369 }, 370 { 371 "BriefDescription": "L2 RFO hits", 372 "Counter": "0,1,2,3", 373 "EventCode": "0x24", 374 "EventName": "L2_RQSTS.RFO_HIT", 375 "SampleAfterValue": "200000", 376 "UMask": "0x4" 377 }, 378 { 379 "BriefDescription": "L2 RFO misses", 380 "Counter": "0,1,2,3", 381 "EventCode": "0x24", 382 "EventName": "L2_RQSTS.RFO_MISS", 383 "SampleAfterValue": "200000", 384 "UMask": "0x8" 385 }, 386 { 387 "BriefDescription": "All L2 transactions", 388 "Counter": "0,1,2,3", 389 "EventCode": "0xF0", 390 "EventName": "L2_TRANSACTIONS.ANY", 391 "SampleAfterValue": "200000", 392 "UMask": "0x80" 393 }, 394 { 395 "BriefDescription": "L2 fill transactions", 396 "Counter": "0,1,2,3", 397 "EventCode": "0xF0", 398 "EventName": "L2_TRANSACTIONS.FILL", 399 "SampleAfterValue": "200000", 400 "UMask": "0x20" 401 }, 402 { 403 "BriefDescription": "L2 instruction fetch transactions", 404 "Counter": "0,1,2,3", 405 "EventCode": "0xF0", 406 "EventName": "L2_TRANSACTIONS.IFETCH", 407 "SampleAfterValue": "200000", 408 "UMask": "0x4" 409 }, 410 { 411 "BriefDescription": "L1D writeback to L2 transactions", 412 "Counter": "0,1,2,3", 413 "EventCode": "0xF0", 414 "EventName": "L2_TRANSACTIONS.L1D_WB", 415 "SampleAfterValue": "200000", 416 "UMask": "0x10" 417 }, 418 { 419 "BriefDescription": "L2 Load transactions", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xF0", 422 "EventName": "L2_TRANSACTIONS.LOAD", 423 "SampleAfterValue": "200000", 424 "UMask": "0x1" 425 }, 426 { 427 "BriefDescription": "L2 prefetch transactions", 428 "Counter": "0,1,2,3", 429 "EventCode": "0xF0", 430 "EventName": "L2_TRANSACTIONS.PREFETCH", 431 "SampleAfterValue": "200000", 432 "UMask": "0x8" 433 }, 434 { 435 "BriefDescription": "L2 RFO transactions", 436 "Counter": "0,1,2,3", 437 "EventCode": "0xF0", 438 "EventName": "L2_TRANSACTIONS.RFO", 439 "SampleAfterValue": "200000", 440 "UMask": "0x2" 441 }, 442 { 443 "BriefDescription": "L2 writeback to LLC transactions", 444 "Counter": "0,1,2,3", 445 "EventCode": "0xF0", 446 "EventName": "L2_TRANSACTIONS.WB", 447 "SampleAfterValue": "200000", 448 "UMask": "0x40" 449 }, 450 { 451 "BriefDescription": "L2 demand lock RFOs in E state", 452 "Counter": "0,1,2,3", 453 "EventCode": "0x27", 454 "EventName": "L2_WRITE.LOCK.E_STATE", 455 "SampleAfterValue": "100000", 456 "UMask": "0x40" 457 }, 458 { 459 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 460 "Counter": "0,1,2,3", 461 "EventCode": "0x27", 462 "EventName": "L2_WRITE.LOCK.HIT", 463 "SampleAfterValue": "100000", 464 "UMask": "0xe0" 465 }, 466 { 467 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 468 "Counter": "0,1,2,3", 469 "EventCode": "0x27", 470 "EventName": "L2_WRITE.LOCK.I_STATE", 471 "SampleAfterValue": "100000", 472 "UMask": "0x10" 473 }, 474 { 475 "BriefDescription": "All demand L2 lock RFOs", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x27", 478 "EventName": "L2_WRITE.LOCK.MESI", 479 "SampleAfterValue": "100000", 480 "UMask": "0xf0" 481 }, 482 { 483 "BriefDescription": "L2 demand lock RFOs in M state", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x27", 486 "EventName": "L2_WRITE.LOCK.M_STATE", 487 "SampleAfterValue": "100000", 488 "UMask": "0x80" 489 }, 490 { 491 "BriefDescription": "L2 demand lock RFOs in S state", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x27", 494 "EventName": "L2_WRITE.LOCK.S_STATE", 495 "SampleAfterValue": "100000", 496 "UMask": "0x20" 497 }, 498 { 499 "BriefDescription": "All L2 demand store RFOs that hit the cache", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x27", 502 "EventName": "L2_WRITE.RFO.HIT", 503 "SampleAfterValue": "100000", 504 "UMask": "0xe" 505 }, 506 { 507 "BriefDescription": "L2 demand store RFOs in I state (misses)", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x27", 510 "EventName": "L2_WRITE.RFO.I_STATE", 511 "SampleAfterValue": "100000", 512 "UMask": "0x1" 513 }, 514 { 515 "BriefDescription": "All L2 demand store RFOs", 516 "Counter": "0,1,2,3", 517 "EventCode": "0x27", 518 "EventName": "L2_WRITE.RFO.MESI", 519 "SampleAfterValue": "100000", 520 "UMask": "0xf" 521 }, 522 { 523 "BriefDescription": "L2 demand store RFOs in M state", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x27", 526 "EventName": "L2_WRITE.RFO.M_STATE", 527 "SampleAfterValue": "100000", 528 "UMask": "0x8" 529 }, 530 { 531 "BriefDescription": "L2 demand store RFOs in S state", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x27", 534 "EventName": "L2_WRITE.RFO.S_STATE", 535 "SampleAfterValue": "100000", 536 "UMask": "0x2" 537 }, 538 { 539 "BriefDescription": "Longest latency cache miss", 540 "Counter": "0,1,2,3", 541 "EventCode": "0x2E", 542 "EventName": "LONGEST_LAT_CACHE.MISS", 543 "SampleAfterValue": "100000", 544 "UMask": "0x41" 545 }, 546 { 547 "BriefDescription": "Longest latency cache reference", 548 "Counter": "0,1,2,3", 549 "EventCode": "0x2E", 550 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 551 "SampleAfterValue": "200000", 552 "UMask": "0x4f" 553 }, 554 { 555 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 556 "Counter": "3", 557 "EventCode": "0xB", 558 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 559 "MSRIndex": "0x3F6", 560 "MSRValue": "0x0", 561 "PEBS": "2", 562 "SampleAfterValue": "2000000", 563 "UMask": "0x10" 564 }, 565 { 566 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 567 "Counter": "3", 568 "EventCode": "0xB", 569 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 570 "MSRIndex": "0x3F6", 571 "MSRValue": "0x400", 572 "PEBS": "2", 573 "SampleAfterValue": "100", 574 "UMask": "0x10" 575 }, 576 { 577 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 578 "Counter": "3", 579 "EventCode": "0xB", 580 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 581 "MSRIndex": "0x3F6", 582 "MSRValue": "0x80", 583 "PEBS": "2", 584 "SampleAfterValue": "1000", 585 "UMask": "0x10" 586 }, 587 { 588 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 589 "Counter": "3", 590 "EventCode": "0xB", 591 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 592 "MSRIndex": "0x3F6", 593 "MSRValue": "0x10", 594 "PEBS": "2", 595 "SampleAfterValue": "10000", 596 "UMask": "0x10" 597 }, 598 { 599 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 600 "Counter": "3", 601 "EventCode": "0xB", 602 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 603 "MSRIndex": "0x3F6", 604 "MSRValue": "0x4000", 605 "PEBS": "2", 606 "SampleAfterValue": "5", 607 "UMask": "0x10" 608 }, 609 { 610 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 611 "Counter": "3", 612 "EventCode": "0xB", 613 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 614 "MSRIndex": "0x3F6", 615 "MSRValue": "0x800", 616 "PEBS": "2", 617 "SampleAfterValue": "50", 618 "UMask": "0x10" 619 }, 620 { 621 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 622 "Counter": "3", 623 "EventCode": "0xB", 624 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 625 "MSRIndex": "0x3F6", 626 "MSRValue": "0x100", 627 "PEBS": "2", 628 "SampleAfterValue": "500", 629 "UMask": "0x10" 630 }, 631 { 632 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 633 "Counter": "3", 634 "EventCode": "0xB", 635 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 636 "MSRIndex": "0x3F6", 637 "MSRValue": "0x20", 638 "PEBS": "2", 639 "SampleAfterValue": "5000", 640 "UMask": "0x10" 641 }, 642 { 643 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 644 "Counter": "3", 645 "EventCode": "0xB", 646 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 647 "MSRIndex": "0x3F6", 648 "MSRValue": "0x8000", 649 "PEBS": "2", 650 "SampleAfterValue": "3", 651 "UMask": "0x10" 652 }, 653 { 654 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 655 "Counter": "3", 656 "EventCode": "0xB", 657 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 658 "MSRIndex": "0x3F6", 659 "MSRValue": "0x4", 660 "PEBS": "2", 661 "SampleAfterValue": "50000", 662 "UMask": "0x10" 663 }, 664 { 665 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 666 "Counter": "3", 667 "EventCode": "0xB", 668 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 669 "MSRIndex": "0x3F6", 670 "MSRValue": "0x1000", 671 "PEBS": "2", 672 "SampleAfterValue": "20", 673 "UMask": "0x10" 674 }, 675 { 676 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 677 "Counter": "3", 678 "EventCode": "0xB", 679 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 680 "MSRIndex": "0x3F6", 681 "MSRValue": "0x200", 682 "PEBS": "2", 683 "SampleAfterValue": "200", 684 "UMask": "0x10" 685 }, 686 { 687 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 688 "Counter": "3", 689 "EventCode": "0xB", 690 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 691 "MSRIndex": "0x3F6", 692 "MSRValue": "0x40", 693 "PEBS": "2", 694 "SampleAfterValue": "2000", 695 "UMask": "0x10" 696 }, 697 { 698 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 699 "Counter": "3", 700 "EventCode": "0xB", 701 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 702 "MSRIndex": "0x3F6", 703 "MSRValue": "0x8", 704 "PEBS": "2", 705 "SampleAfterValue": "20000", 706 "UMask": "0x10" 707 }, 708 { 709 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 710 "Counter": "3", 711 "EventCode": "0xB", 712 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 713 "MSRIndex": "0x3F6", 714 "MSRValue": "0x2000", 715 "PEBS": "2", 716 "SampleAfterValue": "10", 717 "UMask": "0x10" 718 }, 719 { 720 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 721 "Counter": "0,1,2,3", 722 "EventCode": "0xB", 723 "EventName": "MEM_INST_RETIRED.LOADS", 724 "PEBS": "1", 725 "SampleAfterValue": "2000000", 726 "UMask": "0x1" 727 }, 728 { 729 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 730 "Counter": "0,1,2,3", 731 "EventCode": "0xB", 732 "EventName": "MEM_INST_RETIRED.STORES", 733 "PEBS": "1", 734 "SampleAfterValue": "2000000", 735 "UMask": "0x2" 736 }, 737 { 738 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 739 "Counter": "0,1,2,3", 740 "EventCode": "0xCB", 741 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 742 "PEBS": "1", 743 "SampleAfterValue": "200000", 744 "UMask": "0x40" 745 }, 746 { 747 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 748 "Counter": "0,1,2,3", 749 "EventCode": "0xCB", 750 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 751 "PEBS": "1", 752 "SampleAfterValue": "2000000", 753 "UMask": "0x1" 754 }, 755 { 756 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 757 "Counter": "0,1,2,3", 758 "EventCode": "0xCB", 759 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 760 "PEBS": "1", 761 "SampleAfterValue": "200000", 762 "UMask": "0x2" 763 }, 764 { 765 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 766 "Counter": "0,1,2,3", 767 "EventCode": "0xCB", 768 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 769 "PEBS": "1", 770 "SampleAfterValue": "10000", 771 "UMask": "0x10" 772 }, 773 { 774 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 775 "Counter": "0,1,2,3", 776 "EventCode": "0xCB", 777 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 778 "PEBS": "1", 779 "SampleAfterValue": "40000", 780 "UMask": "0x4" 781 }, 782 { 783 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 784 "Counter": "0,1,2,3", 785 "EventCode": "0xCB", 786 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 787 "PEBS": "1", 788 "SampleAfterValue": "40000", 789 "UMask": "0x8" 790 }, 791 { 792 "BriefDescription": "All offcore requests", 793 "Counter": "0,1,2,3", 794 "EventCode": "0xB0", 795 "EventName": "OFFCORE_REQUESTS.ANY", 796 "SampleAfterValue": "100000", 797 "UMask": "0x80" 798 }, 799 { 800 "BriefDescription": "Offcore read requests", 801 "Counter": "0,1,2,3", 802 "EventCode": "0xB0", 803 "EventName": "OFFCORE_REQUESTS.ANY.READ", 804 "SampleAfterValue": "100000", 805 "UMask": "0x8" 806 }, 807 { 808 "BriefDescription": "Offcore RFO requests", 809 "Counter": "0,1,2,3", 810 "EventCode": "0xB0", 811 "EventName": "OFFCORE_REQUESTS.ANY.RFO", 812 "SampleAfterValue": "100000", 813 "UMask": "0x10" 814 }, 815 { 816 "BriefDescription": "Offcore demand code read requests", 817 "Counter": "0,1,2,3", 818 "EventCode": "0xB0", 819 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", 820 "SampleAfterValue": "100000", 821 "UMask": "0x2" 822 }, 823 { 824 "BriefDescription": "Offcore demand data read requests", 825 "Counter": "0,1,2,3", 826 "EventCode": "0xB0", 827 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", 828 "SampleAfterValue": "100000", 829 "UMask": "0x1" 830 }, 831 { 832 "BriefDescription": "Offcore demand RFO requests", 833 "Counter": "0,1,2,3", 834 "EventCode": "0xB0", 835 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", 836 "SampleAfterValue": "100000", 837 "UMask": "0x4" 838 }, 839 { 840 "BriefDescription": "Offcore L1 data cache writebacks", 841 "Counter": "0,1,2,3", 842 "EventCode": "0xB0", 843 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 844 "SampleAfterValue": "100000", 845 "UMask": "0x40" 846 }, 847 { 848 "BriefDescription": "Outstanding offcore reads", 849 "EventCode": "0x60", 850 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", 851 "SampleAfterValue": "2000000", 852 "UMask": "0x8" 853 }, 854 { 855 "BriefDescription": "Cycles offcore reads busy", 856 "CounterMask": "1", 857 "EventCode": "0x60", 858 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", 859 "SampleAfterValue": "2000000", 860 "UMask": "0x8" 861 }, 862 { 863 "BriefDescription": "Outstanding offcore demand code reads", 864 "EventCode": "0x60", 865 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", 866 "SampleAfterValue": "2000000", 867 "UMask": "0x2" 868 }, 869 { 870 "BriefDescription": "Cycles offcore demand code read busy", 871 "CounterMask": "1", 872 "EventCode": "0x60", 873 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", 874 "SampleAfterValue": "2000000", 875 "UMask": "0x2" 876 }, 877 { 878 "BriefDescription": "Outstanding offcore demand data reads", 879 "EventCode": "0x60", 880 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", 881 "SampleAfterValue": "2000000", 882 "UMask": "0x1" 883 }, 884 { 885 "BriefDescription": "Cycles offcore demand data read busy", 886 "CounterMask": "1", 887 "EventCode": "0x60", 888 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", 889 "SampleAfterValue": "2000000", 890 "UMask": "0x1" 891 }, 892 { 893 "BriefDescription": "Outstanding offcore demand RFOs", 894 "EventCode": "0x60", 895 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", 896 "SampleAfterValue": "2000000", 897 "UMask": "0x4" 898 }, 899 { 900 "BriefDescription": "Cycles offcore demand RFOs busy", 901 "CounterMask": "1", 902 "EventCode": "0x60", 903 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", 904 "SampleAfterValue": "2000000", 905 "UMask": "0x4" 906 }, 907 { 908 "BriefDescription": "Offcore requests blocked due to Super Queue full", 909 "Counter": "0,1,2,3", 910 "EventCode": "0xB2", 911 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 912 "SampleAfterValue": "100000", 913 "UMask": "0x1" 914 }, 915 { 916 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 917 "Counter": "0,1,2,3", 918 "EventCode": "0xB7, 0xBB", 919 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 920 "MSRIndex": "0x1a6,0x1a7", 921 "MSRValue": "0x5011", 922 "Offcore": "1", 923 "SampleAfterValue": "100000", 924 "UMask": "0x1" 925 }, 926 { 927 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM", 928 "Counter": "0,1,2,3", 929 "EventCode": "0xB7, 0xBB", 930 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 931 "MSRIndex": "0x1a6,0x1a7", 932 "MSRValue": "0x7f11", 933 "Offcore": "1", 934 "SampleAfterValue": "100000", 935 "UMask": "0x1" 936 }, 937 { 938 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION", 939 "Counter": "0,1,2,3", 940 "EventCode": "0xB7, 0xBB", 941 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 942 "MSRIndex": "0x1a6,0x1a7", 943 "MSRValue": "0xff11", 944 "Offcore": "1", 945 "SampleAfterValue": "100000", 946 "UMask": "0x1" 947 }, 948 { 949 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO", 950 "Counter": "0,1,2,3", 951 "EventCode": "0xB7, 0xBB", 952 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 953 "MSRIndex": "0x1a6,0x1a7", 954 "MSRValue": "0x8011", 955 "Offcore": "1", 956 "SampleAfterValue": "100000", 957 "UMask": "0x1" 958 }, 959 { 960 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE", 961 "Counter": "0,1,2,3", 962 "EventCode": "0xB7, 0xBB", 963 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 964 "MSRIndex": "0x1a6,0x1a7", 965 "MSRValue": "0x111", 966 "Offcore": "1", 967 "SampleAfterValue": "100000", 968 "UMask": "0x1" 969 }, 970 { 971 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 972 "Counter": "0,1,2,3", 973 "EventCode": "0xB7, 0xBB", 974 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 975 "MSRIndex": "0x1a6,0x1a7", 976 "MSRValue": "0x211", 977 "Offcore": "1", 978 "SampleAfterValue": "100000", 979 "UMask": "0x1" 980 }, 981 { 982 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 983 "Counter": "0,1,2,3", 984 "EventCode": "0xB7, 0xBB", 985 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 986 "MSRIndex": "0x1a6,0x1a7", 987 "MSRValue": "0x411", 988 "Offcore": "1", 989 "SampleAfterValue": "100000", 990 "UMask": "0x1" 991 }, 992 { 993 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE", 994 "Counter": "0,1,2,3", 995 "EventCode": "0xB7, 0xBB", 996 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 997 "MSRIndex": "0x1a6,0x1a7", 998 "MSRValue": "0x711", 999 "Offcore": "1", 1000 "SampleAfterValue": "100000", 1001 "UMask": "0x1" 1002 }, 1003 { 1004 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1005 "Counter": "0,1,2,3", 1006 "EventCode": "0xB7, 0xBB", 1007 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1008 "MSRIndex": "0x1a6,0x1a7", 1009 "MSRValue": "0x1011", 1010 "Offcore": "1", 1011 "SampleAfterValue": "100000", 1012 "UMask": "0x1" 1013 }, 1014 { 1015 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM", 1016 "Counter": "0,1,2,3", 1017 "EventCode": "0xB7, 0xBB", 1018 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1019 "MSRIndex": "0x1a6,0x1a7", 1020 "MSRValue": "0x811", 1021 "Offcore": "1", 1022 "SampleAfterValue": "100000", 1023 "UMask": "0x1" 1024 }, 1025 { 1026 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1027 "Counter": "0,1,2,3", 1028 "EventCode": "0xB7, 0xBB", 1029 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1030 "MSRIndex": "0x1a6,0x1a7", 1031 "MSRValue": "0x5044", 1032 "Offcore": "1", 1033 "SampleAfterValue": "100000", 1034 "UMask": "0x1" 1035 }, 1036 { 1037 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM", 1038 "Counter": "0,1,2,3", 1039 "EventCode": "0xB7, 0xBB", 1040 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1041 "MSRIndex": "0x1a6,0x1a7", 1042 "MSRValue": "0x7f44", 1043 "Offcore": "1", 1044 "SampleAfterValue": "100000", 1045 "UMask": "0x1" 1046 }, 1047 { 1048 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION", 1049 "Counter": "0,1,2,3", 1050 "EventCode": "0xB7, 0xBB", 1051 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1052 "MSRIndex": "0x1a6,0x1a7", 1053 "MSRValue": "0xff44", 1054 "Offcore": "1", 1055 "SampleAfterValue": "100000", 1056 "UMask": "0x1" 1057 }, 1058 { 1059 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO", 1060 "Counter": "0,1,2,3", 1061 "EventCode": "0xB7, 0xBB", 1062 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1063 "MSRIndex": "0x1a6,0x1a7", 1064 "MSRValue": "0x8044", 1065 "Offcore": "1", 1066 "SampleAfterValue": "100000", 1067 "UMask": "0x1" 1068 }, 1069 { 1070 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1071 "Counter": "0,1,2,3", 1072 "EventCode": "0xB7, 0xBB", 1073 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1074 "MSRIndex": "0x1a6,0x1a7", 1075 "MSRValue": "0x144", 1076 "Offcore": "1", 1077 "SampleAfterValue": "100000", 1078 "UMask": "0x1" 1079 }, 1080 { 1081 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1082 "Counter": "0,1,2,3", 1083 "EventCode": "0xB7, 0xBB", 1084 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1085 "MSRIndex": "0x1a6,0x1a7", 1086 "MSRValue": "0x244", 1087 "Offcore": "1", 1088 "SampleAfterValue": "100000", 1089 "UMask": "0x1" 1090 }, 1091 { 1092 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1093 "Counter": "0,1,2,3", 1094 "EventCode": "0xB7, 0xBB", 1095 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1096 "MSRIndex": "0x1a6,0x1a7", 1097 "MSRValue": "0x444", 1098 "Offcore": "1", 1099 "SampleAfterValue": "100000", 1100 "UMask": "0x1" 1101 }, 1102 { 1103 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE", 1104 "Counter": "0,1,2,3", 1105 "EventCode": "0xB7, 0xBB", 1106 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1107 "MSRIndex": "0x1a6,0x1a7", 1108 "MSRValue": "0x744", 1109 "Offcore": "1", 1110 "SampleAfterValue": "100000", 1111 "UMask": "0x1" 1112 }, 1113 { 1114 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1115 "Counter": "0,1,2,3", 1116 "EventCode": "0xB7, 0xBB", 1117 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1118 "MSRIndex": "0x1a6,0x1a7", 1119 "MSRValue": "0x1044", 1120 "Offcore": "1", 1121 "SampleAfterValue": "100000", 1122 "UMask": "0x1" 1123 }, 1124 { 1125 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM", 1126 "Counter": "0,1,2,3", 1127 "EventCode": "0xB7, 0xBB", 1128 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1129 "MSRIndex": "0x1a6,0x1a7", 1130 "MSRValue": "0x844", 1131 "Offcore": "1", 1132 "SampleAfterValue": "100000", 1133 "UMask": "0x1" 1134 }, 1135 { 1136 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1137 "Counter": "0,1,2,3", 1138 "EventCode": "0xB7, 0xBB", 1139 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1140 "MSRIndex": "0x1a6,0x1a7", 1141 "MSRValue": "0x50ff", 1142 "Offcore": "1", 1143 "SampleAfterValue": "100000", 1144 "UMask": "0x1" 1145 }, 1146 { 1147 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM", 1148 "Counter": "0,1,2,3", 1149 "EventCode": "0xB7, 0xBB", 1150 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1151 "MSRIndex": "0x1a6,0x1a7", 1152 "MSRValue": "0x7fff", 1153 "Offcore": "1", 1154 "SampleAfterValue": "100000", 1155 "UMask": "0x1" 1156 }, 1157 { 1158 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION", 1159 "Counter": "0,1,2,3", 1160 "EventCode": "0xB7, 0xBB", 1161 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1162 "MSRIndex": "0x1a6,0x1a7", 1163 "MSRValue": "0xffff", 1164 "Offcore": "1", 1165 "SampleAfterValue": "100000", 1166 "UMask": "0x1" 1167 }, 1168 { 1169 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO", 1170 "Counter": "0,1,2,3", 1171 "EventCode": "0xB7, 0xBB", 1172 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1173 "MSRIndex": "0x1a6,0x1a7", 1174 "MSRValue": "0x80ff", 1175 "Offcore": "1", 1176 "SampleAfterValue": "100000", 1177 "UMask": "0x1" 1178 }, 1179 { 1180 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1181 "Counter": "0,1,2,3", 1182 "EventCode": "0xB7, 0xBB", 1183 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1184 "MSRIndex": "0x1a6,0x1a7", 1185 "MSRValue": "0x1ff", 1186 "Offcore": "1", 1187 "SampleAfterValue": "100000", 1188 "UMask": "0x1" 1189 }, 1190 { 1191 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1192 "Counter": "0,1,2,3", 1193 "EventCode": "0xB7, 0xBB", 1194 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1195 "MSRIndex": "0x1a6,0x1a7", 1196 "MSRValue": "0x2ff", 1197 "Offcore": "1", 1198 "SampleAfterValue": "100000", 1199 "UMask": "0x1" 1200 }, 1201 { 1202 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1203 "Counter": "0,1,2,3", 1204 "EventCode": "0xB7, 0xBB", 1205 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1206 "MSRIndex": "0x1a6,0x1a7", 1207 "MSRValue": "0x4ff", 1208 "Offcore": "1", 1209 "SampleAfterValue": "100000", 1210 "UMask": "0x1" 1211 }, 1212 { 1213 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE", 1214 "Counter": "0,1,2,3", 1215 "EventCode": "0xB7, 0xBB", 1216 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1217 "MSRIndex": "0x1a6,0x1a7", 1218 "MSRValue": "0x7ff", 1219 "Offcore": "1", 1220 "SampleAfterValue": "100000", 1221 "UMask": "0x1" 1222 }, 1223 { 1224 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1225 "Counter": "0,1,2,3", 1226 "EventCode": "0xB7, 0xBB", 1227 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1228 "MSRIndex": "0x1a6,0x1a7", 1229 "MSRValue": "0x10ff", 1230 "Offcore": "1", 1231 "SampleAfterValue": "100000", 1232 "UMask": "0x1" 1233 }, 1234 { 1235 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM", 1236 "Counter": "0,1,2,3", 1237 "EventCode": "0xB7, 0xBB", 1238 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1239 "MSRIndex": "0x1a6,0x1a7", 1240 "MSRValue": "0x8ff", 1241 "Offcore": "1", 1242 "SampleAfterValue": "100000", 1243 "UMask": "0x1" 1244 }, 1245 { 1246 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1247 "Counter": "0,1,2,3", 1248 "EventCode": "0xB7, 0xBB", 1249 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1250 "MSRIndex": "0x1a6,0x1a7", 1251 "MSRValue": "0x5022", 1252 "Offcore": "1", 1253 "SampleAfterValue": "100000", 1254 "UMask": "0x1" 1255 }, 1256 { 1257 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM", 1258 "Counter": "0,1,2,3", 1259 "EventCode": "0xB7, 0xBB", 1260 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1261 "MSRIndex": "0x1a6,0x1a7", 1262 "MSRValue": "0x7f22", 1263 "Offcore": "1", 1264 "SampleAfterValue": "100000", 1265 "UMask": "0x1" 1266 }, 1267 { 1268 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION", 1269 "Counter": "0,1,2,3", 1270 "EventCode": "0xB7, 0xBB", 1271 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1272 "MSRIndex": "0x1a6,0x1a7", 1273 "MSRValue": "0xff22", 1274 "Offcore": "1", 1275 "SampleAfterValue": "100000", 1276 "UMask": "0x1" 1277 }, 1278 { 1279 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO", 1280 "Counter": "0,1,2,3", 1281 "EventCode": "0xB7, 0xBB", 1282 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1283 "MSRIndex": "0x1a6,0x1a7", 1284 "MSRValue": "0x8022", 1285 "Offcore": "1", 1286 "SampleAfterValue": "100000", 1287 "UMask": "0x1" 1288 }, 1289 { 1290 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1291 "Counter": "0,1,2,3", 1292 "EventCode": "0xB7, 0xBB", 1293 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1294 "MSRIndex": "0x1a6,0x1a7", 1295 "MSRValue": "0x122", 1296 "Offcore": "1", 1297 "SampleAfterValue": "100000", 1298 "UMask": "0x1" 1299 }, 1300 { 1301 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1302 "Counter": "0,1,2,3", 1303 "EventCode": "0xB7, 0xBB", 1304 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1305 "MSRIndex": "0x1a6,0x1a7", 1306 "MSRValue": "0x222", 1307 "Offcore": "1", 1308 "SampleAfterValue": "100000", 1309 "UMask": "0x1" 1310 }, 1311 { 1312 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1313 "Counter": "0,1,2,3", 1314 "EventCode": "0xB7, 0xBB", 1315 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1316 "MSRIndex": "0x1a6,0x1a7", 1317 "MSRValue": "0x422", 1318 "Offcore": "1", 1319 "SampleAfterValue": "100000", 1320 "UMask": "0x1" 1321 }, 1322 { 1323 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE", 1324 "Counter": "0,1,2,3", 1325 "EventCode": "0xB7, 0xBB", 1326 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1327 "MSRIndex": "0x1a6,0x1a7", 1328 "MSRValue": "0x722", 1329 "Offcore": "1", 1330 "SampleAfterValue": "100000", 1331 "UMask": "0x1" 1332 }, 1333 { 1334 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1335 "Counter": "0,1,2,3", 1336 "EventCode": "0xB7, 0xBB", 1337 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1338 "MSRIndex": "0x1a6,0x1a7", 1339 "MSRValue": "0x1022", 1340 "Offcore": "1", 1341 "SampleAfterValue": "100000", 1342 "UMask": "0x1" 1343 }, 1344 { 1345 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM", 1346 "Counter": "0,1,2,3", 1347 "EventCode": "0xB7, 0xBB", 1348 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1349 "MSRIndex": "0x1a6,0x1a7", 1350 "MSRValue": "0x822", 1351 "Offcore": "1", 1352 "SampleAfterValue": "100000", 1353 "UMask": "0x1" 1354 }, 1355 { 1356 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1357 "Counter": "0,1,2,3", 1358 "EventCode": "0xB7, 0xBB", 1359 "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1360 "MSRIndex": "0x1a6,0x1a7", 1361 "MSRValue": "0x5008", 1362 "Offcore": "1", 1363 "SampleAfterValue": "100000", 1364 "UMask": "0x1" 1365 }, 1366 { 1367 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM", 1368 "Counter": "0,1,2,3", 1369 "EventCode": "0xB7, 0xBB", 1370 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1371 "MSRIndex": "0x1a6,0x1a7", 1372 "MSRValue": "0x7f08", 1373 "Offcore": "1", 1374 "SampleAfterValue": "100000", 1375 "UMask": "0x1" 1376 }, 1377 { 1378 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION", 1379 "Counter": "0,1,2,3", 1380 "EventCode": "0xB7, 0xBB", 1381 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1382 "MSRIndex": "0x1a6,0x1a7", 1383 "MSRValue": "0xff08", 1384 "Offcore": "1", 1385 "SampleAfterValue": "100000", 1386 "UMask": "0x1" 1387 }, 1388 { 1389 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO", 1390 "Counter": "0,1,2,3", 1391 "EventCode": "0xB7, 0xBB", 1392 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1393 "MSRIndex": "0x1a6,0x1a7", 1394 "MSRValue": "0x8008", 1395 "Offcore": "1", 1396 "SampleAfterValue": "100000", 1397 "UMask": "0x1" 1398 }, 1399 { 1400 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1401 "Counter": "0,1,2,3", 1402 "EventCode": "0xB7, 0xBB", 1403 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1404 "MSRIndex": "0x1a6,0x1a7", 1405 "MSRValue": "0x108", 1406 "Offcore": "1", 1407 "SampleAfterValue": "100000", 1408 "UMask": "0x1" 1409 }, 1410 { 1411 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1412 "Counter": "0,1,2,3", 1413 "EventCode": "0xB7, 0xBB", 1414 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT", 1415 "MSRIndex": "0x1a6,0x1a7", 1416 "MSRValue": "0x208", 1417 "Offcore": "1", 1418 "SampleAfterValue": "100000", 1419 "UMask": "0x1" 1420 }, 1421 { 1422 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1423 "Counter": "0,1,2,3", 1424 "EventCode": "0xB7, 0xBB", 1425 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1426 "MSRIndex": "0x1a6,0x1a7", 1427 "MSRValue": "0x408", 1428 "Offcore": "1", 1429 "SampleAfterValue": "100000", 1430 "UMask": "0x1" 1431 }, 1432 { 1433 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE", 1434 "Counter": "0,1,2,3", 1435 "EventCode": "0xB7, 0xBB", 1436 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1437 "MSRIndex": "0x1a6,0x1a7", 1438 "MSRValue": "0x708", 1439 "Offcore": "1", 1440 "SampleAfterValue": "100000", 1441 "UMask": "0x1" 1442 }, 1443 { 1444 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1445 "Counter": "0,1,2,3", 1446 "EventCode": "0xB7, 0xBB", 1447 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1448 "MSRIndex": "0x1a6,0x1a7", 1449 "MSRValue": "0x1008", 1450 "Offcore": "1", 1451 "SampleAfterValue": "100000", 1452 "UMask": "0x1" 1453 }, 1454 { 1455 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM", 1456 "Counter": "0,1,2,3", 1457 "EventCode": "0xB7, 0xBB", 1458 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1459 "MSRIndex": "0x1a6,0x1a7", 1460 "MSRValue": "0x808", 1461 "Offcore": "1", 1462 "SampleAfterValue": "100000", 1463 "UMask": "0x1" 1464 }, 1465 { 1466 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1467 "Counter": "0,1,2,3", 1468 "EventCode": "0xB7, 0xBB", 1469 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1470 "MSRIndex": "0x1a6,0x1a7", 1471 "MSRValue": "0x5077", 1472 "Offcore": "1", 1473 "SampleAfterValue": "100000", 1474 "UMask": "0x1" 1475 }, 1476 { 1477 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM", 1478 "Counter": "0,1,2,3", 1479 "EventCode": "0xB7, 0xBB", 1480 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1481 "MSRIndex": "0x1a6,0x1a7", 1482 "MSRValue": "0x7f77", 1483 "Offcore": "1", 1484 "SampleAfterValue": "100000", 1485 "UMask": "0x1" 1486 }, 1487 { 1488 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION", 1489 "Counter": "0,1,2,3", 1490 "EventCode": "0xB7, 0xBB", 1491 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1492 "MSRIndex": "0x1a6,0x1a7", 1493 "MSRValue": "0xff77", 1494 "Offcore": "1", 1495 "SampleAfterValue": "100000", 1496 "UMask": "0x1" 1497 }, 1498 { 1499 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO", 1500 "Counter": "0,1,2,3", 1501 "EventCode": "0xB7, 0xBB", 1502 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1503 "MSRIndex": "0x1a6,0x1a7", 1504 "MSRValue": "0x8077", 1505 "Offcore": "1", 1506 "SampleAfterValue": "100000", 1507 "UMask": "0x1" 1508 }, 1509 { 1510 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1511 "Counter": "0,1,2,3", 1512 "EventCode": "0xB7, 0xBB", 1513 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1514 "MSRIndex": "0x1a6,0x1a7", 1515 "MSRValue": "0x177", 1516 "Offcore": "1", 1517 "SampleAfterValue": "100000", 1518 "UMask": "0x1" 1519 }, 1520 { 1521 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1522 "Counter": "0,1,2,3", 1523 "EventCode": "0xB7, 0xBB", 1524 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1525 "MSRIndex": "0x1a6,0x1a7", 1526 "MSRValue": "0x277", 1527 "Offcore": "1", 1528 "SampleAfterValue": "100000", 1529 "UMask": "0x1" 1530 }, 1531 { 1532 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1533 "Counter": "0,1,2,3", 1534 "EventCode": "0xB7, 0xBB", 1535 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1536 "MSRIndex": "0x1a6,0x1a7", 1537 "MSRValue": "0x477", 1538 "Offcore": "1", 1539 "SampleAfterValue": "100000", 1540 "UMask": "0x1" 1541 }, 1542 { 1543 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE", 1544 "Counter": "0,1,2,3", 1545 "EventCode": "0xB7, 0xBB", 1546 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1547 "MSRIndex": "0x1a6,0x1a7", 1548 "MSRValue": "0x777", 1549 "Offcore": "1", 1550 "SampleAfterValue": "100000", 1551 "UMask": "0x1" 1552 }, 1553 { 1554 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1555 "Counter": "0,1,2,3", 1556 "EventCode": "0xB7, 0xBB", 1557 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1558 "MSRIndex": "0x1a6,0x1a7", 1559 "MSRValue": "0x1077", 1560 "Offcore": "1", 1561 "SampleAfterValue": "100000", 1562 "UMask": "0x1" 1563 }, 1564 { 1565 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM", 1566 "Counter": "0,1,2,3", 1567 "EventCode": "0xB7, 0xBB", 1568 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1569 "MSRIndex": "0x1a6,0x1a7", 1570 "MSRValue": "0x877", 1571 "Offcore": "1", 1572 "SampleAfterValue": "100000", 1573 "UMask": "0x1" 1574 }, 1575 { 1576 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1577 "Counter": "0,1,2,3", 1578 "EventCode": "0xB7, 0xBB", 1579 "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1580 "MSRIndex": "0x1a6,0x1a7", 1581 "MSRValue": "0x5033", 1582 "Offcore": "1", 1583 "SampleAfterValue": "100000", 1584 "UMask": "0x1" 1585 }, 1586 { 1587 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM", 1588 "Counter": "0,1,2,3", 1589 "EventCode": "0xB7, 0xBB", 1590 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1591 "MSRIndex": "0x1a6,0x1a7", 1592 "MSRValue": "0x7f33", 1593 "Offcore": "1", 1594 "SampleAfterValue": "100000", 1595 "UMask": "0x1" 1596 }, 1597 { 1598 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION", 1599 "Counter": "0,1,2,3", 1600 "EventCode": "0xB7, 0xBB", 1601 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1602 "MSRIndex": "0x1a6,0x1a7", 1603 "MSRValue": "0xff33", 1604 "Offcore": "1", 1605 "SampleAfterValue": "100000", 1606 "UMask": "0x1" 1607 }, 1608 { 1609 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO", 1610 "Counter": "0,1,2,3", 1611 "EventCode": "0xB7, 0xBB", 1612 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1613 "MSRIndex": "0x1a6,0x1a7", 1614 "MSRValue": "0x8033", 1615 "Offcore": "1", 1616 "SampleAfterValue": "100000", 1617 "UMask": "0x1" 1618 }, 1619 { 1620 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1621 "Counter": "0,1,2,3", 1622 "EventCode": "0xB7, 0xBB", 1623 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1624 "MSRIndex": "0x1a6,0x1a7", 1625 "MSRValue": "0x133", 1626 "Offcore": "1", 1627 "SampleAfterValue": "100000", 1628 "UMask": "0x1" 1629 }, 1630 { 1631 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1632 "Counter": "0,1,2,3", 1633 "EventCode": "0xB7, 0xBB", 1634 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1635 "MSRIndex": "0x1a6,0x1a7", 1636 "MSRValue": "0x233", 1637 "Offcore": "1", 1638 "SampleAfterValue": "100000", 1639 "UMask": "0x1" 1640 }, 1641 { 1642 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1643 "Counter": "0,1,2,3", 1644 "EventCode": "0xB7, 0xBB", 1645 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1646 "MSRIndex": "0x1a6,0x1a7", 1647 "MSRValue": "0x433", 1648 "Offcore": "1", 1649 "SampleAfterValue": "100000", 1650 "UMask": "0x1" 1651 }, 1652 { 1653 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE", 1654 "Counter": "0,1,2,3", 1655 "EventCode": "0xB7, 0xBB", 1656 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1657 "MSRIndex": "0x1a6,0x1a7", 1658 "MSRValue": "0x733", 1659 "Offcore": "1", 1660 "SampleAfterValue": "100000", 1661 "UMask": "0x1" 1662 }, 1663 { 1664 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1665 "Counter": "0,1,2,3", 1666 "EventCode": "0xB7, 0xBB", 1667 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1668 "MSRIndex": "0x1a6,0x1a7", 1669 "MSRValue": "0x1033", 1670 "Offcore": "1", 1671 "SampleAfterValue": "100000", 1672 "UMask": "0x1" 1673 }, 1674 { 1675 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM", 1676 "Counter": "0,1,2,3", 1677 "EventCode": "0xB7, 0xBB", 1678 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1679 "MSRIndex": "0x1a6,0x1a7", 1680 "MSRValue": "0x833", 1681 "Offcore": "1", 1682 "SampleAfterValue": "100000", 1683 "UMask": "0x1" 1684 }, 1685 { 1686 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1687 "Counter": "0,1,2,3", 1688 "EventCode": "0xB7, 0xBB", 1689 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1690 "MSRIndex": "0x1a6,0x1a7", 1691 "MSRValue": "0x5003", 1692 "Offcore": "1", 1693 "SampleAfterValue": "100000", 1694 "UMask": "0x1" 1695 }, 1696 { 1697 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM", 1698 "Counter": "0,1,2,3", 1699 "EventCode": "0xB7, 0xBB", 1700 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1701 "MSRIndex": "0x1a6,0x1a7", 1702 "MSRValue": "0x7f03", 1703 "Offcore": "1", 1704 "SampleAfterValue": "100000", 1705 "UMask": "0x1" 1706 }, 1707 { 1708 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION", 1709 "Counter": "0,1,2,3", 1710 "EventCode": "0xB7, 0xBB", 1711 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1712 "MSRIndex": "0x1a6,0x1a7", 1713 "MSRValue": "0xff03", 1714 "Offcore": "1", 1715 "SampleAfterValue": "100000", 1716 "UMask": "0x1" 1717 }, 1718 { 1719 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO", 1720 "Counter": "0,1,2,3", 1721 "EventCode": "0xB7, 0xBB", 1722 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1723 "MSRIndex": "0x1a6,0x1a7", 1724 "MSRValue": "0x8003", 1725 "Offcore": "1", 1726 "SampleAfterValue": "100000", 1727 "UMask": "0x1" 1728 }, 1729 { 1730 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1731 "Counter": "0,1,2,3", 1732 "EventCode": "0xB7, 0xBB", 1733 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1734 "MSRIndex": "0x1a6,0x1a7", 1735 "MSRValue": "0x103", 1736 "Offcore": "1", 1737 "SampleAfterValue": "100000", 1738 "UMask": "0x1" 1739 }, 1740 { 1741 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1742 "Counter": "0,1,2,3", 1743 "EventCode": "0xB7, 0xBB", 1744 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1745 "MSRIndex": "0x1a6,0x1a7", 1746 "MSRValue": "0x203", 1747 "Offcore": "1", 1748 "SampleAfterValue": "100000", 1749 "UMask": "0x1" 1750 }, 1751 { 1752 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1753 "Counter": "0,1,2,3", 1754 "EventCode": "0xB7, 0xBB", 1755 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1756 "MSRIndex": "0x1a6,0x1a7", 1757 "MSRValue": "0x403", 1758 "Offcore": "1", 1759 "SampleAfterValue": "100000", 1760 "UMask": "0x1" 1761 }, 1762 { 1763 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE", 1764 "Counter": "0,1,2,3", 1765 "EventCode": "0xB7, 0xBB", 1766 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1767 "MSRIndex": "0x1a6,0x1a7", 1768 "MSRValue": "0x703", 1769 "Offcore": "1", 1770 "SampleAfterValue": "100000", 1771 "UMask": "0x1" 1772 }, 1773 { 1774 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1775 "Counter": "0,1,2,3", 1776 "EventCode": "0xB7, 0xBB", 1777 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1778 "MSRIndex": "0x1a6,0x1a7", 1779 "MSRValue": "0x1003", 1780 "Offcore": "1", 1781 "SampleAfterValue": "100000", 1782 "UMask": "0x1" 1783 }, 1784 { 1785 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM", 1786 "Counter": "0,1,2,3", 1787 "EventCode": "0xB7, 0xBB", 1788 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1789 "MSRIndex": "0x1a6,0x1a7", 1790 "MSRValue": "0x803", 1791 "Offcore": "1", 1792 "SampleAfterValue": "100000", 1793 "UMask": "0x1" 1794 }, 1795 { 1796 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1797 "Counter": "0,1,2,3", 1798 "EventCode": "0xB7, 0xBB", 1799 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1800 "MSRIndex": "0x1a6,0x1a7", 1801 "MSRValue": "0x5001", 1802 "Offcore": "1", 1803 "SampleAfterValue": "100000", 1804 "UMask": "0x1" 1805 }, 1806 { 1807 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM", 1808 "Counter": "0,1,2,3", 1809 "EventCode": "0xB7, 0xBB", 1810 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1811 "MSRIndex": "0x1a6,0x1a7", 1812 "MSRValue": "0x7f01", 1813 "Offcore": "1", 1814 "SampleAfterValue": "100000", 1815 "UMask": "0x1" 1816 }, 1817 { 1818 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION", 1819 "Counter": "0,1,2,3", 1820 "EventCode": "0xB7, 0xBB", 1821 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1822 "MSRIndex": "0x1a6,0x1a7", 1823 "MSRValue": "0xff01", 1824 "Offcore": "1", 1825 "SampleAfterValue": "100000", 1826 "UMask": "0x1" 1827 }, 1828 { 1829 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO", 1830 "Counter": "0,1,2,3", 1831 "EventCode": "0xB7, 0xBB", 1832 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1833 "MSRIndex": "0x1a6,0x1a7", 1834 "MSRValue": "0x8001", 1835 "Offcore": "1", 1836 "SampleAfterValue": "100000", 1837 "UMask": "0x1" 1838 }, 1839 { 1840 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1841 "Counter": "0,1,2,3", 1842 "EventCode": "0xB7, 0xBB", 1843 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1844 "MSRIndex": "0x1a6,0x1a7", 1845 "MSRValue": "0x101", 1846 "Offcore": "1", 1847 "SampleAfterValue": "100000", 1848 "UMask": "0x1" 1849 }, 1850 { 1851 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1852 "Counter": "0,1,2,3", 1853 "EventCode": "0xB7, 0xBB", 1854 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1855 "MSRIndex": "0x1a6,0x1a7", 1856 "MSRValue": "0x201", 1857 "Offcore": "1", 1858 "SampleAfterValue": "100000", 1859 "UMask": "0x1" 1860 }, 1861 { 1862 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1863 "Counter": "0,1,2,3", 1864 "EventCode": "0xB7, 0xBB", 1865 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1866 "MSRIndex": "0x1a6,0x1a7", 1867 "MSRValue": "0x401", 1868 "Offcore": "1", 1869 "SampleAfterValue": "100000", 1870 "UMask": "0x1" 1871 }, 1872 { 1873 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE", 1874 "Counter": "0,1,2,3", 1875 "EventCode": "0xB7, 0xBB", 1876 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1877 "MSRIndex": "0x1a6,0x1a7", 1878 "MSRValue": "0x701", 1879 "Offcore": "1", 1880 "SampleAfterValue": "100000", 1881 "UMask": "0x1" 1882 }, 1883 { 1884 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1885 "Counter": "0,1,2,3", 1886 "EventCode": "0xB7, 0xBB", 1887 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1888 "MSRIndex": "0x1a6,0x1a7", 1889 "MSRValue": "0x1001", 1890 "Offcore": "1", 1891 "SampleAfterValue": "100000", 1892 "UMask": "0x1" 1893 }, 1894 { 1895 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", 1896 "Counter": "0,1,2,3", 1897 "EventCode": "0xB7, 0xBB", 1898 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 1899 "MSRIndex": "0x1a6,0x1a7", 1900 "MSRValue": "0x801", 1901 "Offcore": "1", 1902 "SampleAfterValue": "100000", 1903 "UMask": "0x1" 1904 }, 1905 { 1906 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1907 "Counter": "0,1,2,3", 1908 "EventCode": "0xB7, 0xBB", 1909 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1910 "MSRIndex": "0x1a6,0x1a7", 1911 "MSRValue": "0x5004", 1912 "Offcore": "1", 1913 "SampleAfterValue": "100000", 1914 "UMask": "0x1" 1915 }, 1916 { 1917 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM", 1918 "Counter": "0,1,2,3", 1919 "EventCode": "0xB7, 0xBB", 1920 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 1921 "MSRIndex": "0x1a6,0x1a7", 1922 "MSRValue": "0x7f04", 1923 "Offcore": "1", 1924 "SampleAfterValue": "100000", 1925 "UMask": "0x1" 1926 }, 1927 { 1928 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION", 1929 "Counter": "0,1,2,3", 1930 "EventCode": "0xB7, 0xBB", 1931 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 1932 "MSRIndex": "0x1a6,0x1a7", 1933 "MSRValue": "0xff04", 1934 "Offcore": "1", 1935 "SampleAfterValue": "100000", 1936 "UMask": "0x1" 1937 }, 1938 { 1939 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO", 1940 "Counter": "0,1,2,3", 1941 "EventCode": "0xB7, 0xBB", 1942 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 1943 "MSRIndex": "0x1a6,0x1a7", 1944 "MSRValue": "0x8004", 1945 "Offcore": "1", 1946 "SampleAfterValue": "100000", 1947 "UMask": "0x1" 1948 }, 1949 { 1950 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1951 "Counter": "0,1,2,3", 1952 "EventCode": "0xB7, 0xBB", 1953 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 1954 "MSRIndex": "0x1a6,0x1a7", 1955 "MSRValue": "0x104", 1956 "Offcore": "1", 1957 "SampleAfterValue": "100000", 1958 "UMask": "0x1" 1959 }, 1960 { 1961 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1962 "Counter": "0,1,2,3", 1963 "EventCode": "0xB7, 0xBB", 1964 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1965 "MSRIndex": "0x1a6,0x1a7", 1966 "MSRValue": "0x204", 1967 "Offcore": "1", 1968 "SampleAfterValue": "100000", 1969 "UMask": "0x1" 1970 }, 1971 { 1972 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1973 "Counter": "0,1,2,3", 1974 "EventCode": "0xB7, 0xBB", 1975 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1976 "MSRIndex": "0x1a6,0x1a7", 1977 "MSRValue": "0x404", 1978 "Offcore": "1", 1979 "SampleAfterValue": "100000", 1980 "UMask": "0x1" 1981 }, 1982 { 1983 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE", 1984 "Counter": "0,1,2,3", 1985 "EventCode": "0xB7, 0xBB", 1986 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 1987 "MSRIndex": "0x1a6,0x1a7", 1988 "MSRValue": "0x704", 1989 "Offcore": "1", 1990 "SampleAfterValue": "100000", 1991 "UMask": "0x1" 1992 }, 1993 { 1994 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1995 "Counter": "0,1,2,3", 1996 "EventCode": "0xB7, 0xBB", 1997 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1998 "MSRIndex": "0x1a6,0x1a7", 1999 "MSRValue": "0x1004", 2000 "Offcore": "1", 2001 "SampleAfterValue": "100000", 2002 "UMask": "0x1" 2003 }, 2004 { 2005 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM", 2006 "Counter": "0,1,2,3", 2007 "EventCode": "0xB7, 0xBB", 2008 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2009 "MSRIndex": "0x1a6,0x1a7", 2010 "MSRValue": "0x804", 2011 "Offcore": "1", 2012 "SampleAfterValue": "100000", 2013 "UMask": "0x1" 2014 }, 2015 { 2016 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2017 "Counter": "0,1,2,3", 2018 "EventCode": "0xB7, 0xBB", 2019 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2020 "MSRIndex": "0x1a6,0x1a7", 2021 "MSRValue": "0x5002", 2022 "Offcore": "1", 2023 "SampleAfterValue": "100000", 2024 "UMask": "0x1" 2025 }, 2026 { 2027 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM", 2028 "Counter": "0,1,2,3", 2029 "EventCode": "0xB7, 0xBB", 2030 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2031 "MSRIndex": "0x1a6,0x1a7", 2032 "MSRValue": "0x7f02", 2033 "Offcore": "1", 2034 "SampleAfterValue": "100000", 2035 "UMask": "0x1" 2036 }, 2037 { 2038 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION", 2039 "Counter": "0,1,2,3", 2040 "EventCode": "0xB7, 0xBB", 2041 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2042 "MSRIndex": "0x1a6,0x1a7", 2043 "MSRValue": "0xff02", 2044 "Offcore": "1", 2045 "SampleAfterValue": "100000", 2046 "UMask": "0x1" 2047 }, 2048 { 2049 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO", 2050 "Counter": "0,1,2,3", 2051 "EventCode": "0xB7, 0xBB", 2052 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2053 "MSRIndex": "0x1a6,0x1a7", 2054 "MSRValue": "0x8002", 2055 "Offcore": "1", 2056 "SampleAfterValue": "100000", 2057 "UMask": "0x1" 2058 }, 2059 { 2060 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2061 "Counter": "0,1,2,3", 2062 "EventCode": "0xB7, 0xBB", 2063 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2064 "MSRIndex": "0x1a6,0x1a7", 2065 "MSRValue": "0x102", 2066 "Offcore": "1", 2067 "SampleAfterValue": "100000", 2068 "UMask": "0x1" 2069 }, 2070 { 2071 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2072 "Counter": "0,1,2,3", 2073 "EventCode": "0xB7, 0xBB", 2074 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2075 "MSRIndex": "0x1a6,0x1a7", 2076 "MSRValue": "0x202", 2077 "Offcore": "1", 2078 "SampleAfterValue": "100000", 2079 "UMask": "0x1" 2080 }, 2081 { 2082 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2083 "Counter": "0,1,2,3", 2084 "EventCode": "0xB7, 0xBB", 2085 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2086 "MSRIndex": "0x1a6,0x1a7", 2087 "MSRValue": "0x402", 2088 "Offcore": "1", 2089 "SampleAfterValue": "100000", 2090 "UMask": "0x1" 2091 }, 2092 { 2093 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE", 2094 "Counter": "0,1,2,3", 2095 "EventCode": "0xB7, 0xBB", 2096 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2097 "MSRIndex": "0x1a6,0x1a7", 2098 "MSRValue": "0x702", 2099 "Offcore": "1", 2100 "SampleAfterValue": "100000", 2101 "UMask": "0x1" 2102 }, 2103 { 2104 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2105 "Counter": "0,1,2,3", 2106 "EventCode": "0xB7, 0xBB", 2107 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2108 "MSRIndex": "0x1a6,0x1a7", 2109 "MSRValue": "0x1002", 2110 "Offcore": "1", 2111 "SampleAfterValue": "100000", 2112 "UMask": "0x1" 2113 }, 2114 { 2115 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM", 2116 "Counter": "0,1,2,3", 2117 "EventCode": "0xB7, 0xBB", 2118 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2119 "MSRIndex": "0x1a6,0x1a7", 2120 "MSRValue": "0x802", 2121 "Offcore": "1", 2122 "SampleAfterValue": "100000", 2123 "UMask": "0x1" 2124 }, 2125 { 2126 "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2127 "Counter": "0,1,2,3", 2128 "EventCode": "0xB7, 0xBB", 2129 "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2130 "MSRIndex": "0x1a6,0x1a7", 2131 "MSRValue": "0x5080", 2132 "Offcore": "1", 2133 "SampleAfterValue": "100000", 2134 "UMask": "0x1" 2135 }, 2136 { 2137 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM", 2138 "Counter": "0,1,2,3", 2139 "EventCode": "0xB7, 0xBB", 2140 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2141 "MSRIndex": "0x1a6,0x1a7", 2142 "MSRValue": "0x7f80", 2143 "Offcore": "1", 2144 "SampleAfterValue": "100000", 2145 "UMask": "0x1" 2146 }, 2147 { 2148 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION", 2149 "Counter": "0,1,2,3", 2150 "EventCode": "0xB7, 0xBB", 2151 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2152 "MSRIndex": "0x1a6,0x1a7", 2153 "MSRValue": "0xff80", 2154 "Offcore": "1", 2155 "SampleAfterValue": "100000", 2156 "UMask": "0x1" 2157 }, 2158 { 2159 "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO", 2160 "Counter": "0,1,2,3", 2161 "EventCode": "0xB7, 0xBB", 2162 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2163 "MSRIndex": "0x1a6,0x1a7", 2164 "MSRValue": "0x8080", 2165 "Offcore": "1", 2166 "SampleAfterValue": "100000", 2167 "UMask": "0x1" 2168 }, 2169 { 2170 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2171 "Counter": "0,1,2,3", 2172 "EventCode": "0xB7, 0xBB", 2173 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2174 "MSRIndex": "0x1a6,0x1a7", 2175 "MSRValue": "0x180", 2176 "Offcore": "1", 2177 "SampleAfterValue": "100000", 2178 "UMask": "0x1" 2179 }, 2180 { 2181 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2182 "Counter": "0,1,2,3", 2183 "EventCode": "0xB7, 0xBB", 2184 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2185 "MSRIndex": "0x1a6,0x1a7", 2186 "MSRValue": "0x280", 2187 "Offcore": "1", 2188 "SampleAfterValue": "100000", 2189 "UMask": "0x1" 2190 }, 2191 { 2192 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2193 "Counter": "0,1,2,3", 2194 "EventCode": "0xB7, 0xBB", 2195 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2196 "MSRIndex": "0x1a6,0x1a7", 2197 "MSRValue": "0x480", 2198 "Offcore": "1", 2199 "SampleAfterValue": "100000", 2200 "UMask": "0x1" 2201 }, 2202 { 2203 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE", 2204 "Counter": "0,1,2,3", 2205 "EventCode": "0xB7, 0xBB", 2206 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2207 "MSRIndex": "0x1a6,0x1a7", 2208 "MSRValue": "0x780", 2209 "Offcore": "1", 2210 "SampleAfterValue": "100000", 2211 "UMask": "0x1" 2212 }, 2213 { 2214 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2215 "Counter": "0,1,2,3", 2216 "EventCode": "0xB7, 0xBB", 2217 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2218 "MSRIndex": "0x1a6,0x1a7", 2219 "MSRValue": "0x1080", 2220 "Offcore": "1", 2221 "SampleAfterValue": "100000", 2222 "UMask": "0x1" 2223 }, 2224 { 2225 "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM", 2226 "Counter": "0,1,2,3", 2227 "EventCode": "0xB7, 0xBB", 2228 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2229 "MSRIndex": "0x1a6,0x1a7", 2230 "MSRValue": "0x880", 2231 "Offcore": "1", 2232 "SampleAfterValue": "100000", 2233 "UMask": "0x1" 2234 }, 2235 { 2236 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2237 "Counter": "0,1,2,3", 2238 "EventCode": "0xB7, 0xBB", 2239 "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2240 "MSRIndex": "0x1a6,0x1a7", 2241 "MSRValue": "0x5050", 2242 "Offcore": "1", 2243 "SampleAfterValue": "100000", 2244 "UMask": "0x1" 2245 }, 2246 { 2247 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM", 2248 "Counter": "0,1,2,3", 2249 "EventCode": "0xB7, 0xBB", 2250 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2251 "MSRIndex": "0x1a6,0x1a7", 2252 "MSRValue": "0x7f50", 2253 "Offcore": "1", 2254 "SampleAfterValue": "100000", 2255 "UMask": "0x1" 2256 }, 2257 { 2258 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION", 2259 "Counter": "0,1,2,3", 2260 "EventCode": "0xB7, 0xBB", 2261 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2262 "MSRIndex": "0x1a6,0x1a7", 2263 "MSRValue": "0xff50", 2264 "Offcore": "1", 2265 "SampleAfterValue": "100000", 2266 "UMask": "0x1" 2267 }, 2268 { 2269 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO", 2270 "Counter": "0,1,2,3", 2271 "EventCode": "0xB7, 0xBB", 2272 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2273 "MSRIndex": "0x1a6,0x1a7", 2274 "MSRValue": "0x8050", 2275 "Offcore": "1", 2276 "SampleAfterValue": "100000", 2277 "UMask": "0x1" 2278 }, 2279 { 2280 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2281 "Counter": "0,1,2,3", 2282 "EventCode": "0xB7, 0xBB", 2283 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2284 "MSRIndex": "0x1a6,0x1a7", 2285 "MSRValue": "0x150", 2286 "Offcore": "1", 2287 "SampleAfterValue": "100000", 2288 "UMask": "0x1" 2289 }, 2290 { 2291 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2292 "Counter": "0,1,2,3", 2293 "EventCode": "0xB7, 0xBB", 2294 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2295 "MSRIndex": "0x1a6,0x1a7", 2296 "MSRValue": "0x250", 2297 "Offcore": "1", 2298 "SampleAfterValue": "100000", 2299 "UMask": "0x1" 2300 }, 2301 { 2302 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2303 "Counter": "0,1,2,3", 2304 "EventCode": "0xB7, 0xBB", 2305 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2306 "MSRIndex": "0x1a6,0x1a7", 2307 "MSRValue": "0x450", 2308 "Offcore": "1", 2309 "SampleAfterValue": "100000", 2310 "UMask": "0x1" 2311 }, 2312 { 2313 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE", 2314 "Counter": "0,1,2,3", 2315 "EventCode": "0xB7, 0xBB", 2316 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2317 "MSRIndex": "0x1a6,0x1a7", 2318 "MSRValue": "0x750", 2319 "Offcore": "1", 2320 "SampleAfterValue": "100000", 2321 "UMask": "0x1" 2322 }, 2323 { 2324 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2325 "Counter": "0,1,2,3", 2326 "EventCode": "0xB7, 0xBB", 2327 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2328 "MSRIndex": "0x1a6,0x1a7", 2329 "MSRValue": "0x1050", 2330 "Offcore": "1", 2331 "SampleAfterValue": "100000", 2332 "UMask": "0x1" 2333 }, 2334 { 2335 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM", 2336 "Counter": "0,1,2,3", 2337 "EventCode": "0xB7, 0xBB", 2338 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2339 "MSRIndex": "0x1a6,0x1a7", 2340 "MSRValue": "0x850", 2341 "Offcore": "1", 2342 "SampleAfterValue": "100000", 2343 "UMask": "0x1" 2344 }, 2345 { 2346 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2347 "Counter": "0,1,2,3", 2348 "EventCode": "0xB7, 0xBB", 2349 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2350 "MSRIndex": "0x1a6,0x1a7", 2351 "MSRValue": "0x5010", 2352 "Offcore": "1", 2353 "SampleAfterValue": "100000", 2354 "UMask": "0x1" 2355 }, 2356 { 2357 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM", 2358 "Counter": "0,1,2,3", 2359 "EventCode": "0xB7, 0xBB", 2360 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2361 "MSRIndex": "0x1a6,0x1a7", 2362 "MSRValue": "0x7f10", 2363 "Offcore": "1", 2364 "SampleAfterValue": "100000", 2365 "UMask": "0x1" 2366 }, 2367 { 2368 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION", 2369 "Counter": "0,1,2,3", 2370 "EventCode": "0xB7, 0xBB", 2371 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2372 "MSRIndex": "0x1a6,0x1a7", 2373 "MSRValue": "0xff10", 2374 "Offcore": "1", 2375 "SampleAfterValue": "100000", 2376 "UMask": "0x1" 2377 }, 2378 { 2379 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO", 2380 "Counter": "0,1,2,3", 2381 "EventCode": "0xB7, 0xBB", 2382 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2383 "MSRIndex": "0x1a6,0x1a7", 2384 "MSRValue": "0x8010", 2385 "Offcore": "1", 2386 "SampleAfterValue": "100000", 2387 "UMask": "0x1" 2388 }, 2389 { 2390 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2391 "Counter": "0,1,2,3", 2392 "EventCode": "0xB7, 0xBB", 2393 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2394 "MSRIndex": "0x1a6,0x1a7", 2395 "MSRValue": "0x110", 2396 "Offcore": "1", 2397 "SampleAfterValue": "100000", 2398 "UMask": "0x1" 2399 }, 2400 { 2401 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2402 "Counter": "0,1,2,3", 2403 "EventCode": "0xB7, 0xBB", 2404 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2405 "MSRIndex": "0x1a6,0x1a7", 2406 "MSRValue": "0x210", 2407 "Offcore": "1", 2408 "SampleAfterValue": "100000", 2409 "UMask": "0x1" 2410 }, 2411 { 2412 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2413 "Counter": "0,1,2,3", 2414 "EventCode": "0xB7, 0xBB", 2415 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2416 "MSRIndex": "0x1a6,0x1a7", 2417 "MSRValue": "0x410", 2418 "Offcore": "1", 2419 "SampleAfterValue": "100000", 2420 "UMask": "0x1" 2421 }, 2422 { 2423 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE", 2424 "Counter": "0,1,2,3", 2425 "EventCode": "0xB7, 0xBB", 2426 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2427 "MSRIndex": "0x1a6,0x1a7", 2428 "MSRValue": "0x710", 2429 "Offcore": "1", 2430 "SampleAfterValue": "100000", 2431 "UMask": "0x1" 2432 }, 2433 { 2434 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2435 "Counter": "0,1,2,3", 2436 "EventCode": "0xB7, 0xBB", 2437 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2438 "MSRIndex": "0x1a6,0x1a7", 2439 "MSRValue": "0x1010", 2440 "Offcore": "1", 2441 "SampleAfterValue": "100000", 2442 "UMask": "0x1" 2443 }, 2444 { 2445 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", 2446 "Counter": "0,1,2,3", 2447 "EventCode": "0xB7, 0xBB", 2448 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2449 "MSRIndex": "0x1a6,0x1a7", 2450 "MSRValue": "0x810", 2451 "Offcore": "1", 2452 "SampleAfterValue": "100000", 2453 "UMask": "0x1" 2454 }, 2455 { 2456 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2457 "Counter": "0,1,2,3", 2458 "EventCode": "0xB7, 0xBB", 2459 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2460 "MSRIndex": "0x1a6,0x1a7", 2461 "MSRValue": "0x5040", 2462 "Offcore": "1", 2463 "SampleAfterValue": "100000", 2464 "UMask": "0x1" 2465 }, 2466 { 2467 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM", 2468 "Counter": "0,1,2,3", 2469 "EventCode": "0xB7, 0xBB", 2470 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2471 "MSRIndex": "0x1a6,0x1a7", 2472 "MSRValue": "0x7f40", 2473 "Offcore": "1", 2474 "SampleAfterValue": "100000", 2475 "UMask": "0x1" 2476 }, 2477 { 2478 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION", 2479 "Counter": "0,1,2,3", 2480 "EventCode": "0xB7, 0xBB", 2481 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2482 "MSRIndex": "0x1a6,0x1a7", 2483 "MSRValue": "0xff40", 2484 "Offcore": "1", 2485 "SampleAfterValue": "100000", 2486 "UMask": "0x1" 2487 }, 2488 { 2489 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO", 2490 "Counter": "0,1,2,3", 2491 "EventCode": "0xB7, 0xBB", 2492 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2493 "MSRIndex": "0x1a6,0x1a7", 2494 "MSRValue": "0x8040", 2495 "Offcore": "1", 2496 "SampleAfterValue": "100000", 2497 "UMask": "0x1" 2498 }, 2499 { 2500 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2501 "Counter": "0,1,2,3", 2502 "EventCode": "0xB7, 0xBB", 2503 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2504 "MSRIndex": "0x1a6,0x1a7", 2505 "MSRValue": "0x140", 2506 "Offcore": "1", 2507 "SampleAfterValue": "100000", 2508 "UMask": "0x1" 2509 }, 2510 { 2511 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2512 "Counter": "0,1,2,3", 2513 "EventCode": "0xB7, 0xBB", 2514 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2515 "MSRIndex": "0x1a6,0x1a7", 2516 "MSRValue": "0x240", 2517 "Offcore": "1", 2518 "SampleAfterValue": "100000", 2519 "UMask": "0x1" 2520 }, 2521 { 2522 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2523 "Counter": "0,1,2,3", 2524 "EventCode": "0xB7, 0xBB", 2525 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2526 "MSRIndex": "0x1a6,0x1a7", 2527 "MSRValue": "0x440", 2528 "Offcore": "1", 2529 "SampleAfterValue": "100000", 2530 "UMask": "0x1" 2531 }, 2532 { 2533 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE", 2534 "Counter": "0,1,2,3", 2535 "EventCode": "0xB7, 0xBB", 2536 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2537 "MSRIndex": "0x1a6,0x1a7", 2538 "MSRValue": "0x740", 2539 "Offcore": "1", 2540 "SampleAfterValue": "100000", 2541 "UMask": "0x1" 2542 }, 2543 { 2544 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2545 "Counter": "0,1,2,3", 2546 "EventCode": "0xB7, 0xBB", 2547 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2548 "MSRIndex": "0x1a6,0x1a7", 2549 "MSRValue": "0x1040", 2550 "Offcore": "1", 2551 "SampleAfterValue": "100000", 2552 "UMask": "0x1" 2553 }, 2554 { 2555 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM", 2556 "Counter": "0,1,2,3", 2557 "EventCode": "0xB7, 0xBB", 2558 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2559 "MSRIndex": "0x1a6,0x1a7", 2560 "MSRValue": "0x840", 2561 "Offcore": "1", 2562 "SampleAfterValue": "100000", 2563 "UMask": "0x1" 2564 }, 2565 { 2566 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2567 "Counter": "0,1,2,3", 2568 "EventCode": "0xB7, 0xBB", 2569 "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2570 "MSRIndex": "0x1a6,0x1a7", 2571 "MSRValue": "0x5020", 2572 "Offcore": "1", 2573 "SampleAfterValue": "100000", 2574 "UMask": "0x1" 2575 }, 2576 { 2577 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM", 2578 "Counter": "0,1,2,3", 2579 "EventCode": "0xB7, 0xBB", 2580 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2581 "MSRIndex": "0x1a6,0x1a7", 2582 "MSRValue": "0x7f20", 2583 "Offcore": "1", 2584 "SampleAfterValue": "100000", 2585 "UMask": "0x1" 2586 }, 2587 { 2588 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION", 2589 "Counter": "0,1,2,3", 2590 "EventCode": "0xB7, 0xBB", 2591 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2592 "MSRIndex": "0x1a6,0x1a7", 2593 "MSRValue": "0xff20", 2594 "Offcore": "1", 2595 "SampleAfterValue": "100000", 2596 "UMask": "0x1" 2597 }, 2598 { 2599 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO", 2600 "Counter": "0,1,2,3", 2601 "EventCode": "0xB7, 0xBB", 2602 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2603 "MSRIndex": "0x1a6,0x1a7", 2604 "MSRValue": "0x8020", 2605 "Offcore": "1", 2606 "SampleAfterValue": "100000", 2607 "UMask": "0x1" 2608 }, 2609 { 2610 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2611 "Counter": "0,1,2,3", 2612 "EventCode": "0xB7, 0xBB", 2613 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2614 "MSRIndex": "0x1a6,0x1a7", 2615 "MSRValue": "0x120", 2616 "Offcore": "1", 2617 "SampleAfterValue": "100000", 2618 "UMask": "0x1" 2619 }, 2620 { 2621 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2622 "Counter": "0,1,2,3", 2623 "EventCode": "0xB7, 0xBB", 2624 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2625 "MSRIndex": "0x1a6,0x1a7", 2626 "MSRValue": "0x220", 2627 "Offcore": "1", 2628 "SampleAfterValue": "100000", 2629 "UMask": "0x1" 2630 }, 2631 { 2632 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2633 "Counter": "0,1,2,3", 2634 "EventCode": "0xB7, 0xBB", 2635 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2636 "MSRIndex": "0x1a6,0x1a7", 2637 "MSRValue": "0x420", 2638 "Offcore": "1", 2639 "SampleAfterValue": "100000", 2640 "UMask": "0x1" 2641 }, 2642 { 2643 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE", 2644 "Counter": "0,1,2,3", 2645 "EventCode": "0xB7, 0xBB", 2646 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2647 "MSRIndex": "0x1a6,0x1a7", 2648 "MSRValue": "0x720", 2649 "Offcore": "1", 2650 "SampleAfterValue": "100000", 2651 "UMask": "0x1" 2652 }, 2653 { 2654 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2655 "Counter": "0,1,2,3", 2656 "EventCode": "0xB7, 0xBB", 2657 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2658 "MSRIndex": "0x1a6,0x1a7", 2659 "MSRValue": "0x1020", 2660 "Offcore": "1", 2661 "SampleAfterValue": "100000", 2662 "UMask": "0x1" 2663 }, 2664 { 2665 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM", 2666 "Counter": "0,1,2,3", 2667 "EventCode": "0xB7, 0xBB", 2668 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2669 "MSRIndex": "0x1a6,0x1a7", 2670 "MSRValue": "0x820", 2671 "Offcore": "1", 2672 "SampleAfterValue": "100000", 2673 "UMask": "0x1" 2674 }, 2675 { 2676 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2677 "Counter": "0,1,2,3", 2678 "EventCode": "0xB7, 0xBB", 2679 "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2680 "MSRIndex": "0x1a6,0x1a7", 2681 "MSRValue": "0x5070", 2682 "Offcore": "1", 2683 "SampleAfterValue": "100000", 2684 "UMask": "0x1" 2685 }, 2686 { 2687 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM", 2688 "Counter": "0,1,2,3", 2689 "EventCode": "0xB7, 0xBB", 2690 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2691 "MSRIndex": "0x1a6,0x1a7", 2692 "MSRValue": "0x7f70", 2693 "Offcore": "1", 2694 "SampleAfterValue": "100000", 2695 "UMask": "0x1" 2696 }, 2697 { 2698 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION", 2699 "Counter": "0,1,2,3", 2700 "EventCode": "0xB7, 0xBB", 2701 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2702 "MSRIndex": "0x1a6,0x1a7", 2703 "MSRValue": "0xff70", 2704 "Offcore": "1", 2705 "SampleAfterValue": "100000", 2706 "UMask": "0x1" 2707 }, 2708 { 2709 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO", 2710 "Counter": "0,1,2,3", 2711 "EventCode": "0xB7, 0xBB", 2712 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2713 "MSRIndex": "0x1a6,0x1a7", 2714 "MSRValue": "0x8070", 2715 "Offcore": "1", 2716 "SampleAfterValue": "100000", 2717 "UMask": "0x1" 2718 }, 2719 { 2720 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2721 "Counter": "0,1,2,3", 2722 "EventCode": "0xB7, 0xBB", 2723 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2724 "MSRIndex": "0x1a6,0x1a7", 2725 "MSRValue": "0x170", 2726 "Offcore": "1", 2727 "SampleAfterValue": "100000", 2728 "UMask": "0x1" 2729 }, 2730 { 2731 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2732 "Counter": "0,1,2,3", 2733 "EventCode": "0xB7, 0xBB", 2734 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2735 "MSRIndex": "0x1a6,0x1a7", 2736 "MSRValue": "0x270", 2737 "Offcore": "1", 2738 "SampleAfterValue": "100000", 2739 "UMask": "0x1" 2740 }, 2741 { 2742 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2743 "Counter": "0,1,2,3", 2744 "EventCode": "0xB7, 0xBB", 2745 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2746 "MSRIndex": "0x1a6,0x1a7", 2747 "MSRValue": "0x470", 2748 "Offcore": "1", 2749 "SampleAfterValue": "100000", 2750 "UMask": "0x1" 2751 }, 2752 { 2753 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE", 2754 "Counter": "0,1,2,3", 2755 "EventCode": "0xB7, 0xBB", 2756 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2757 "MSRIndex": "0x1a6,0x1a7", 2758 "MSRValue": "0x770", 2759 "Offcore": "1", 2760 "SampleAfterValue": "100000", 2761 "UMask": "0x1" 2762 }, 2763 { 2764 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2765 "Counter": "0,1,2,3", 2766 "EventCode": "0xB7, 0xBB", 2767 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2768 "MSRIndex": "0x1a6,0x1a7", 2769 "MSRValue": "0x1070", 2770 "Offcore": "1", 2771 "SampleAfterValue": "100000", 2772 "UMask": "0x1" 2773 }, 2774 { 2775 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM", 2776 "Counter": "0,1,2,3", 2777 "EventCode": "0xB7, 0xBB", 2778 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 2779 "MSRIndex": "0x1a6,0x1a7", 2780 "MSRValue": "0x870", 2781 "Offcore": "1", 2782 "SampleAfterValue": "100000", 2783 "UMask": "0x1" 2784 }, 2785 { 2786 "BriefDescription": "Super Queue LRU hints sent to LLC", 2787 "Counter": "0,1,2,3", 2788 "EventCode": "0xF4", 2789 "EventName": "SQ_MISC.LRU_HINTS", 2790 "SampleAfterValue": "2000000", 2791 "UMask": "0x4" 2792 }, 2793 { 2794 "BriefDescription": "Super Queue lock splits across a cache line", 2795 "Counter": "0,1,2,3", 2796 "EventCode": "0xF4", 2797 "EventName": "SQ_MISC.SPLIT_LOCK", 2798 "SampleAfterValue": "2000000", 2799 "UMask": "0x10" 2800 }, 2801 { 2802 "BriefDescription": "Loads delayed with at-Retirement block code", 2803 "Counter": "0,1,2,3", 2804 "EventCode": "0x6", 2805 "EventName": "STORE_BLOCKS.AT_RET", 2806 "SampleAfterValue": "200000", 2807 "UMask": "0x4" 2808 }, 2809 { 2810 "BriefDescription": "Cacheable loads delayed with L1D block code", 2811 "Counter": "0,1,2,3", 2812 "EventCode": "0x6", 2813 "EventName": "STORE_BLOCKS.L1D_BLOCK", 2814 "SampleAfterValue": "200000", 2815 "UMask": "0x8" 2816 } 2817]