1[
2    {
3        "BriefDescription": "Cycles L1D locked",
4        "EventCode": "0x63",
5        "EventName": "CACHE_LOCK_CYCLES.L1D",
6        "SampleAfterValue": "2000000",
7        "UMask": "0x2"
8    },
9    {
10        "BriefDescription": "Cycles L1D and L2 locked",
11        "EventCode": "0x63",
12        "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
13        "SampleAfterValue": "2000000",
14        "UMask": "0x1"
15    },
16    {
17        "BriefDescription": "L1D cache lines replaced in M state",
18        "EventCode": "0x51",
19        "EventName": "L1D.M_EVICT",
20        "SampleAfterValue": "2000000",
21        "UMask": "0x4"
22    },
23    {
24        "BriefDescription": "L1D cache lines allocated in the M state",
25        "EventCode": "0x51",
26        "EventName": "L1D.M_REPL",
27        "SampleAfterValue": "2000000",
28        "UMask": "0x2"
29    },
30    {
31        "BriefDescription": "L1D snoop eviction of cache lines in M state",
32        "EventCode": "0x51",
33        "EventName": "L1D.M_SNOOP_EVICT",
34        "SampleAfterValue": "2000000",
35        "UMask": "0x8"
36    },
37    {
38        "BriefDescription": "L1 data cache lines allocated",
39        "EventCode": "0x51",
40        "EventName": "L1D.REPL",
41        "SampleAfterValue": "2000000",
42        "UMask": "0x1"
43    },
44    {
45        "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
46        "EventCode": "0x52",
47        "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
48        "SampleAfterValue": "2000000",
49        "UMask": "0x1"
50    },
51    {
52        "BriefDescription": "L1D hardware prefetch misses",
53        "EventCode": "0x4E",
54        "EventName": "L1D_PREFETCH.MISS",
55        "SampleAfterValue": "200000",
56        "UMask": "0x2"
57    },
58    {
59        "BriefDescription": "L1D hardware prefetch requests",
60        "EventCode": "0x4E",
61        "EventName": "L1D_PREFETCH.REQUESTS",
62        "SampleAfterValue": "200000",
63        "UMask": "0x1"
64    },
65    {
66        "BriefDescription": "L1D hardware prefetch requests triggered",
67        "EventCode": "0x4E",
68        "EventName": "L1D_PREFETCH.TRIGGERS",
69        "SampleAfterValue": "200000",
70        "UMask": "0x4"
71    },
72    {
73        "BriefDescription": "L1 writebacks to L2 in E state",
74        "EventCode": "0x28",
75        "EventName": "L1D_WB_L2.E_STATE",
76        "SampleAfterValue": "100000",
77        "UMask": "0x4"
78    },
79    {
80        "BriefDescription": "L1 writebacks to L2 in I state (misses)",
81        "EventCode": "0x28",
82        "EventName": "L1D_WB_L2.I_STATE",
83        "SampleAfterValue": "100000",
84        "UMask": "0x1"
85    },
86    {
87        "BriefDescription": "All L1 writebacks to L2",
88        "EventCode": "0x28",
89        "EventName": "L1D_WB_L2.MESI",
90        "SampleAfterValue": "100000",
91        "UMask": "0xf"
92    },
93    {
94        "BriefDescription": "L1 writebacks to L2 in M state",
95        "EventCode": "0x28",
96        "EventName": "L1D_WB_L2.M_STATE",
97        "SampleAfterValue": "100000",
98        "UMask": "0x8"
99    },
100    {
101        "BriefDescription": "L1 writebacks to L2 in S state",
102        "EventCode": "0x28",
103        "EventName": "L1D_WB_L2.S_STATE",
104        "SampleAfterValue": "100000",
105        "UMask": "0x2"
106    },
107    {
108        "BriefDescription": "All L2 data requests",
109        "EventCode": "0x26",
110        "EventName": "L2_DATA_RQSTS.ANY",
111        "SampleAfterValue": "200000",
112        "UMask": "0xff"
113    },
114    {
115        "BriefDescription": "L2 data demand loads in E state",
116        "EventCode": "0x26",
117        "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
118        "SampleAfterValue": "200000",
119        "UMask": "0x4"
120    },
121    {
122        "BriefDescription": "L2 data demand loads in I state (misses)",
123        "EventCode": "0x26",
124        "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
125        "SampleAfterValue": "200000",
126        "UMask": "0x1"
127    },
128    {
129        "BriefDescription": "L2 data demand requests",
130        "EventCode": "0x26",
131        "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
132        "SampleAfterValue": "200000",
133        "UMask": "0xf"
134    },
135    {
136        "BriefDescription": "L2 data demand loads in M state",
137        "EventCode": "0x26",
138        "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
139        "SampleAfterValue": "200000",
140        "UMask": "0x8"
141    },
142    {
143        "BriefDescription": "L2 data demand loads in S state",
144        "EventCode": "0x26",
145        "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
146        "SampleAfterValue": "200000",
147        "UMask": "0x2"
148    },
149    {
150        "BriefDescription": "L2 data prefetches in E state",
151        "EventCode": "0x26",
152        "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
153        "SampleAfterValue": "200000",
154        "UMask": "0x40"
155    },
156    {
157        "BriefDescription": "L2 data prefetches in the I state (misses)",
158        "EventCode": "0x26",
159        "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
160        "SampleAfterValue": "200000",
161        "UMask": "0x10"
162    },
163    {
164        "BriefDescription": "All L2 data prefetches",
165        "EventCode": "0x26",
166        "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
167        "SampleAfterValue": "200000",
168        "UMask": "0xf0"
169    },
170    {
171        "BriefDescription": "L2 data prefetches in M state",
172        "EventCode": "0x26",
173        "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
174        "SampleAfterValue": "200000",
175        "UMask": "0x80"
176    },
177    {
178        "BriefDescription": "L2 data prefetches in the S state",
179        "EventCode": "0x26",
180        "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
181        "SampleAfterValue": "200000",
182        "UMask": "0x20"
183    },
184    {
185        "BriefDescription": "L2 lines allocated",
186        "EventCode": "0xF1",
187        "EventName": "L2_LINES_IN.ANY",
188        "SampleAfterValue": "100000",
189        "UMask": "0x7"
190    },
191    {
192        "BriefDescription": "L2 lines allocated in the E state",
193        "EventCode": "0xF1",
194        "EventName": "L2_LINES_IN.E_STATE",
195        "SampleAfterValue": "100000",
196        "UMask": "0x4"
197    },
198    {
199        "BriefDescription": "L2 lines allocated in the S state",
200        "EventCode": "0xF1",
201        "EventName": "L2_LINES_IN.S_STATE",
202        "SampleAfterValue": "100000",
203        "UMask": "0x2"
204    },
205    {
206        "BriefDescription": "L2 lines evicted",
207        "EventCode": "0xF2",
208        "EventName": "L2_LINES_OUT.ANY",
209        "SampleAfterValue": "100000",
210        "UMask": "0xf"
211    },
212    {
213        "BriefDescription": "L2 lines evicted by a demand request",
214        "EventCode": "0xF2",
215        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
216        "SampleAfterValue": "100000",
217        "UMask": "0x1"
218    },
219    {
220        "BriefDescription": "L2 modified lines evicted by a demand request",
221        "EventCode": "0xF2",
222        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
223        "SampleAfterValue": "100000",
224        "UMask": "0x2"
225    },
226    {
227        "BriefDescription": "L2 lines evicted by a prefetch request",
228        "EventCode": "0xF2",
229        "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
230        "SampleAfterValue": "100000",
231        "UMask": "0x4"
232    },
233    {
234        "BriefDescription": "L2 modified lines evicted by a prefetch request",
235        "EventCode": "0xF2",
236        "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
237        "SampleAfterValue": "100000",
238        "UMask": "0x8"
239    },
240    {
241        "BriefDescription": "L2 instruction fetches",
242        "EventCode": "0x24",
243        "EventName": "L2_RQSTS.IFETCHES",
244        "SampleAfterValue": "200000",
245        "UMask": "0x30"
246    },
247    {
248        "BriefDescription": "L2 instruction fetch hits",
249        "EventCode": "0x24",
250        "EventName": "L2_RQSTS.IFETCH_HIT",
251        "SampleAfterValue": "200000",
252        "UMask": "0x10"
253    },
254    {
255        "BriefDescription": "L2 instruction fetch misses",
256        "EventCode": "0x24",
257        "EventName": "L2_RQSTS.IFETCH_MISS",
258        "SampleAfterValue": "200000",
259        "UMask": "0x20"
260    },
261    {
262        "BriefDescription": "L2 load hits",
263        "EventCode": "0x24",
264        "EventName": "L2_RQSTS.LD_HIT",
265        "SampleAfterValue": "200000",
266        "UMask": "0x1"
267    },
268    {
269        "BriefDescription": "L2 load misses",
270        "EventCode": "0x24",
271        "EventName": "L2_RQSTS.LD_MISS",
272        "SampleAfterValue": "200000",
273        "UMask": "0x2"
274    },
275    {
276        "BriefDescription": "L2 requests",
277        "EventCode": "0x24",
278        "EventName": "L2_RQSTS.LOADS",
279        "SampleAfterValue": "200000",
280        "UMask": "0x3"
281    },
282    {
283        "BriefDescription": "All L2 misses",
284        "EventCode": "0x24",
285        "EventName": "L2_RQSTS.MISS",
286        "SampleAfterValue": "200000",
287        "UMask": "0xaa"
288    },
289    {
290        "BriefDescription": "All L2 prefetches",
291        "EventCode": "0x24",
292        "EventName": "L2_RQSTS.PREFETCHES",
293        "SampleAfterValue": "200000",
294        "UMask": "0xc0"
295    },
296    {
297        "BriefDescription": "L2 prefetch hits",
298        "EventCode": "0x24",
299        "EventName": "L2_RQSTS.PREFETCH_HIT",
300        "SampleAfterValue": "200000",
301        "UMask": "0x40"
302    },
303    {
304        "BriefDescription": "L2 prefetch misses",
305        "EventCode": "0x24",
306        "EventName": "L2_RQSTS.PREFETCH_MISS",
307        "SampleAfterValue": "200000",
308        "UMask": "0x80"
309    },
310    {
311        "BriefDescription": "All L2 requests",
312        "EventCode": "0x24",
313        "EventName": "L2_RQSTS.REFERENCES",
314        "SampleAfterValue": "200000",
315        "UMask": "0xff"
316    },
317    {
318        "BriefDescription": "L2 RFO requests",
319        "EventCode": "0x24",
320        "EventName": "L2_RQSTS.RFOS",
321        "SampleAfterValue": "200000",
322        "UMask": "0xc"
323    },
324    {
325        "BriefDescription": "L2 RFO hits",
326        "EventCode": "0x24",
327        "EventName": "L2_RQSTS.RFO_HIT",
328        "SampleAfterValue": "200000",
329        "UMask": "0x4"
330    },
331    {
332        "BriefDescription": "L2 RFO misses",
333        "EventCode": "0x24",
334        "EventName": "L2_RQSTS.RFO_MISS",
335        "SampleAfterValue": "200000",
336        "UMask": "0x8"
337    },
338    {
339        "BriefDescription": "All L2 transactions",
340        "EventCode": "0xF0",
341        "EventName": "L2_TRANSACTIONS.ANY",
342        "SampleAfterValue": "200000",
343        "UMask": "0x80"
344    },
345    {
346        "BriefDescription": "L2 fill transactions",
347        "EventCode": "0xF0",
348        "EventName": "L2_TRANSACTIONS.FILL",
349        "SampleAfterValue": "200000",
350        "UMask": "0x20"
351    },
352    {
353        "BriefDescription": "L2 instruction fetch transactions",
354        "EventCode": "0xF0",
355        "EventName": "L2_TRANSACTIONS.IFETCH",
356        "SampleAfterValue": "200000",
357        "UMask": "0x4"
358    },
359    {
360        "BriefDescription": "L1D writeback to L2 transactions",
361        "EventCode": "0xF0",
362        "EventName": "L2_TRANSACTIONS.L1D_WB",
363        "SampleAfterValue": "200000",
364        "UMask": "0x10"
365    },
366    {
367        "BriefDescription": "L2 Load transactions",
368        "EventCode": "0xF0",
369        "EventName": "L2_TRANSACTIONS.LOAD",
370        "SampleAfterValue": "200000",
371        "UMask": "0x1"
372    },
373    {
374        "BriefDescription": "L2 prefetch transactions",
375        "EventCode": "0xF0",
376        "EventName": "L2_TRANSACTIONS.PREFETCH",
377        "SampleAfterValue": "200000",
378        "UMask": "0x8"
379    },
380    {
381        "BriefDescription": "L2 RFO transactions",
382        "EventCode": "0xF0",
383        "EventName": "L2_TRANSACTIONS.RFO",
384        "SampleAfterValue": "200000",
385        "UMask": "0x2"
386    },
387    {
388        "BriefDescription": "L2 writeback to LLC transactions",
389        "EventCode": "0xF0",
390        "EventName": "L2_TRANSACTIONS.WB",
391        "SampleAfterValue": "200000",
392        "UMask": "0x40"
393    },
394    {
395        "BriefDescription": "L2 demand lock RFOs in E state",
396        "EventCode": "0x27",
397        "EventName": "L2_WRITE.LOCK.E_STATE",
398        "SampleAfterValue": "100000",
399        "UMask": "0x40"
400    },
401    {
402        "BriefDescription": "All demand L2 lock RFOs that hit the cache",
403        "EventCode": "0x27",
404        "EventName": "L2_WRITE.LOCK.HIT",
405        "SampleAfterValue": "100000",
406        "UMask": "0xe0"
407    },
408    {
409        "BriefDescription": "L2 demand lock RFOs in I state (misses)",
410        "EventCode": "0x27",
411        "EventName": "L2_WRITE.LOCK.I_STATE",
412        "SampleAfterValue": "100000",
413        "UMask": "0x10"
414    },
415    {
416        "BriefDescription": "All demand L2 lock RFOs",
417        "EventCode": "0x27",
418        "EventName": "L2_WRITE.LOCK.MESI",
419        "SampleAfterValue": "100000",
420        "UMask": "0xf0"
421    },
422    {
423        "BriefDescription": "L2 demand lock RFOs in M state",
424        "EventCode": "0x27",
425        "EventName": "L2_WRITE.LOCK.M_STATE",
426        "SampleAfterValue": "100000",
427        "UMask": "0x80"
428    },
429    {
430        "BriefDescription": "L2 demand lock RFOs in S state",
431        "EventCode": "0x27",
432        "EventName": "L2_WRITE.LOCK.S_STATE",
433        "SampleAfterValue": "100000",
434        "UMask": "0x20"
435    },
436    {
437        "BriefDescription": "All L2 demand store RFOs that hit the cache",
438        "EventCode": "0x27",
439        "EventName": "L2_WRITE.RFO.HIT",
440        "SampleAfterValue": "100000",
441        "UMask": "0xe"
442    },
443    {
444        "BriefDescription": "L2 demand store RFOs in I state (misses)",
445        "EventCode": "0x27",
446        "EventName": "L2_WRITE.RFO.I_STATE",
447        "SampleAfterValue": "100000",
448        "UMask": "0x1"
449    },
450    {
451        "BriefDescription": "All L2 demand store RFOs",
452        "EventCode": "0x27",
453        "EventName": "L2_WRITE.RFO.MESI",
454        "SampleAfterValue": "100000",
455        "UMask": "0xf"
456    },
457    {
458        "BriefDescription": "L2 demand store RFOs in M state",
459        "EventCode": "0x27",
460        "EventName": "L2_WRITE.RFO.M_STATE",
461        "SampleAfterValue": "100000",
462        "UMask": "0x8"
463    },
464    {
465        "BriefDescription": "L2 demand store RFOs in S state",
466        "EventCode": "0x27",
467        "EventName": "L2_WRITE.RFO.S_STATE",
468        "SampleAfterValue": "100000",
469        "UMask": "0x2"
470    },
471    {
472        "BriefDescription": "Longest latency cache miss",
473        "EventCode": "0x2E",
474        "EventName": "LONGEST_LAT_CACHE.MISS",
475        "SampleAfterValue": "100000",
476        "UMask": "0x41"
477    },
478    {
479        "BriefDescription": "Longest latency cache reference",
480        "EventCode": "0x2E",
481        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
482        "SampleAfterValue": "200000",
483        "UMask": "0x4f"
484    },
485    {
486        "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
487        "EventCode": "0xB",
488        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
489        "MSRIndex": "0x3F6",
490        "PEBS": "2",
491        "SampleAfterValue": "2000000",
492        "UMask": "0x10"
493    },
494    {
495        "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
496        "EventCode": "0xB",
497        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
498        "MSRIndex": "0x3F6",
499        "MSRValue": "0x400",
500        "PEBS": "2",
501        "SampleAfterValue": "100",
502        "UMask": "0x10"
503    },
504    {
505        "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
506        "EventCode": "0xB",
507        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
508        "MSRIndex": "0x3F6",
509        "MSRValue": "0x80",
510        "PEBS": "2",
511        "SampleAfterValue": "1000",
512        "UMask": "0x10"
513    },
514    {
515        "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
516        "EventCode": "0xB",
517        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
518        "MSRIndex": "0x3F6",
519        "MSRValue": "0x10",
520        "PEBS": "2",
521        "SampleAfterValue": "10000",
522        "UMask": "0x10"
523    },
524    {
525        "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
526        "EventCode": "0xB",
527        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
528        "MSRIndex": "0x3F6",
529        "MSRValue": "0x4000",
530        "PEBS": "2",
531        "SampleAfterValue": "5",
532        "UMask": "0x10"
533    },
534    {
535        "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
536        "EventCode": "0xB",
537        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
538        "MSRIndex": "0x3F6",
539        "MSRValue": "0x800",
540        "PEBS": "2",
541        "SampleAfterValue": "50",
542        "UMask": "0x10"
543    },
544    {
545        "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
546        "EventCode": "0xB",
547        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
548        "MSRIndex": "0x3F6",
549        "MSRValue": "0x100",
550        "PEBS": "2",
551        "SampleAfterValue": "500",
552        "UMask": "0x10"
553    },
554    {
555        "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
556        "EventCode": "0xB",
557        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
558        "MSRIndex": "0x3F6",
559        "MSRValue": "0x20",
560        "PEBS": "2",
561        "SampleAfterValue": "5000",
562        "UMask": "0x10"
563    },
564    {
565        "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
566        "EventCode": "0xB",
567        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
568        "MSRIndex": "0x3F6",
569        "MSRValue": "0x8000",
570        "PEBS": "2",
571        "SampleAfterValue": "3",
572        "UMask": "0x10"
573    },
574    {
575        "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
576        "EventCode": "0xB",
577        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
578        "MSRIndex": "0x3F6",
579        "MSRValue": "0x4",
580        "PEBS": "2",
581        "SampleAfterValue": "50000",
582        "UMask": "0x10"
583    },
584    {
585        "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
586        "EventCode": "0xB",
587        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
588        "MSRIndex": "0x3F6",
589        "MSRValue": "0x1000",
590        "PEBS": "2",
591        "SampleAfterValue": "20",
592        "UMask": "0x10"
593    },
594    {
595        "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
596        "EventCode": "0xB",
597        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
598        "MSRIndex": "0x3F6",
599        "MSRValue": "0x200",
600        "PEBS": "2",
601        "SampleAfterValue": "200",
602        "UMask": "0x10"
603    },
604    {
605        "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
606        "EventCode": "0xB",
607        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
608        "MSRIndex": "0x3F6",
609        "MSRValue": "0x40",
610        "PEBS": "2",
611        "SampleAfterValue": "2000",
612        "UMask": "0x10"
613    },
614    {
615        "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
616        "EventCode": "0xB",
617        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
618        "MSRIndex": "0x3F6",
619        "MSRValue": "0x8",
620        "PEBS": "2",
621        "SampleAfterValue": "20000",
622        "UMask": "0x10"
623    },
624    {
625        "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
626        "EventCode": "0xB",
627        "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
628        "MSRIndex": "0x3F6",
629        "MSRValue": "0x2000",
630        "PEBS": "2",
631        "SampleAfterValue": "10",
632        "UMask": "0x10"
633    },
634    {
635        "BriefDescription": "Instructions retired which contains a load (Precise Event)",
636        "EventCode": "0xB",
637        "EventName": "MEM_INST_RETIRED.LOADS",
638        "PEBS": "1",
639        "SampleAfterValue": "2000000",
640        "UMask": "0x1"
641    },
642    {
643        "BriefDescription": "Instructions retired which contains a store (Precise Event)",
644        "EventCode": "0xB",
645        "EventName": "MEM_INST_RETIRED.STORES",
646        "PEBS": "1",
647        "SampleAfterValue": "2000000",
648        "UMask": "0x2"
649    },
650    {
651        "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
652        "EventCode": "0xCB",
653        "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
654        "PEBS": "1",
655        "SampleAfterValue": "200000",
656        "UMask": "0x40"
657    },
658    {
659        "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
660        "EventCode": "0xCB",
661        "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
662        "PEBS": "1",
663        "SampleAfterValue": "2000000",
664        "UMask": "0x1"
665    },
666    {
667        "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
668        "EventCode": "0xCB",
669        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
670        "PEBS": "1",
671        "SampleAfterValue": "200000",
672        "UMask": "0x2"
673    },
674    {
675        "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
676        "EventCode": "0xCB",
677        "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
678        "PEBS": "1",
679        "SampleAfterValue": "10000",
680        "UMask": "0x10"
681    },
682    {
683        "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
684        "EventCode": "0xCB",
685        "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
686        "PEBS": "1",
687        "SampleAfterValue": "40000",
688        "UMask": "0x4"
689    },
690    {
691        "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
692        "EventCode": "0xCB",
693        "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
694        "PEBS": "1",
695        "SampleAfterValue": "40000",
696        "UMask": "0x8"
697    },
698    {
699        "BriefDescription": "All offcore requests",
700        "EventCode": "0xB0",
701        "EventName": "OFFCORE_REQUESTS.ANY",
702        "SampleAfterValue": "100000",
703        "UMask": "0x80"
704    },
705    {
706        "BriefDescription": "Offcore read requests",
707        "EventCode": "0xB0",
708        "EventName": "OFFCORE_REQUESTS.ANY.READ",
709        "SampleAfterValue": "100000",
710        "UMask": "0x8"
711    },
712    {
713        "BriefDescription": "Offcore RFO requests",
714        "EventCode": "0xB0",
715        "EventName": "OFFCORE_REQUESTS.ANY.RFO",
716        "SampleAfterValue": "100000",
717        "UMask": "0x10"
718    },
719    {
720        "BriefDescription": "Offcore demand code read requests",
721        "EventCode": "0xB0",
722        "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
723        "SampleAfterValue": "100000",
724        "UMask": "0x2"
725    },
726    {
727        "BriefDescription": "Offcore demand data read requests",
728        "EventCode": "0xB0",
729        "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
730        "SampleAfterValue": "100000",
731        "UMask": "0x1"
732    },
733    {
734        "BriefDescription": "Offcore demand RFO requests",
735        "EventCode": "0xB0",
736        "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
737        "SampleAfterValue": "100000",
738        "UMask": "0x4"
739    },
740    {
741        "BriefDescription": "Offcore L1 data cache writebacks",
742        "EventCode": "0xB0",
743        "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
744        "SampleAfterValue": "100000",
745        "UMask": "0x40"
746    },
747    {
748        "BriefDescription": "Outstanding offcore reads",
749        "EventCode": "0x60",
750        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
751        "SampleAfterValue": "2000000",
752        "UMask": "0x8"
753    },
754    {
755        "BriefDescription": "Cycles offcore reads busy",
756        "CounterMask": "1",
757        "EventCode": "0x60",
758        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
759        "SampleAfterValue": "2000000",
760        "UMask": "0x8"
761    },
762    {
763        "BriefDescription": "Outstanding offcore demand code reads",
764        "EventCode": "0x60",
765        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
766        "SampleAfterValue": "2000000",
767        "UMask": "0x2"
768    },
769    {
770        "BriefDescription": "Cycles offcore demand code read busy",
771        "CounterMask": "1",
772        "EventCode": "0x60",
773        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
774        "SampleAfterValue": "2000000",
775        "UMask": "0x2"
776    },
777    {
778        "BriefDescription": "Outstanding offcore demand data reads",
779        "EventCode": "0x60",
780        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
781        "SampleAfterValue": "2000000",
782        "UMask": "0x1"
783    },
784    {
785        "BriefDescription": "Cycles offcore demand data read busy",
786        "CounterMask": "1",
787        "EventCode": "0x60",
788        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
789        "SampleAfterValue": "2000000",
790        "UMask": "0x1"
791    },
792    {
793        "BriefDescription": "Outstanding offcore demand RFOs",
794        "EventCode": "0x60",
795        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
796        "SampleAfterValue": "2000000",
797        "UMask": "0x4"
798    },
799    {
800        "BriefDescription": "Cycles offcore demand RFOs busy",
801        "CounterMask": "1",
802        "EventCode": "0x60",
803        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
804        "SampleAfterValue": "2000000",
805        "UMask": "0x4"
806    },
807    {
808        "BriefDescription": "Offcore requests blocked due to Super Queue full",
809        "EventCode": "0xB2",
810        "EventName": "OFFCORE_REQUESTS_SQ_FULL",
811        "SampleAfterValue": "100000",
812        "UMask": "0x1"
813    },
814    {
815        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
816        "EventCode": "0xB7, 0xBB",
817        "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
818        "MSRIndex": "0x1a6,0x1a7",
819        "MSRValue": "0x5011",
820        "SampleAfterValue": "100000",
821        "UMask": "0x1"
822    },
823    {
824        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM",
825        "EventCode": "0xB7, 0xBB",
826        "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
827        "MSRIndex": "0x1a6,0x1a7",
828        "MSRValue": "0x7f11",
829        "SampleAfterValue": "100000",
830        "UMask": "0x1"
831    },
832    {
833        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION",
834        "EventCode": "0xB7, 0xBB",
835        "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
836        "MSRIndex": "0x1a6,0x1a7",
837        "MSRValue": "0xff11",
838        "SampleAfterValue": "100000",
839        "UMask": "0x1"
840    },
841    {
842        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO",
843        "EventCode": "0xB7, 0xBB",
844        "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
845        "MSRIndex": "0x1a6,0x1a7",
846        "MSRValue": "0x8011",
847        "SampleAfterValue": "100000",
848        "UMask": "0x1"
849    },
850    {
851        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE",
852        "EventCode": "0xB7, 0xBB",
853        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
854        "MSRIndex": "0x1a6,0x1a7",
855        "MSRValue": "0x111",
856        "SampleAfterValue": "100000",
857        "UMask": "0x1"
858    },
859    {
860        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
861        "EventCode": "0xB7, 0xBB",
862        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
863        "MSRIndex": "0x1a6,0x1a7",
864        "MSRValue": "0x211",
865        "SampleAfterValue": "100000",
866        "UMask": "0x1"
867    },
868    {
869        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
870        "EventCode": "0xB7, 0xBB",
871        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
872        "MSRIndex": "0x1a6,0x1a7",
873        "MSRValue": "0x411",
874        "SampleAfterValue": "100000",
875        "UMask": "0x1"
876    },
877    {
878        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE",
879        "EventCode": "0xB7, 0xBB",
880        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
881        "MSRIndex": "0x1a6,0x1a7",
882        "MSRValue": "0x711",
883        "SampleAfterValue": "100000",
884        "UMask": "0x1"
885    },
886    {
887        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
888        "EventCode": "0xB7, 0xBB",
889        "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
890        "MSRIndex": "0x1a6,0x1a7",
891        "MSRValue": "0x1011",
892        "SampleAfterValue": "100000",
893        "UMask": "0x1"
894    },
895    {
896        "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM",
897        "EventCode": "0xB7, 0xBB",
898        "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
899        "MSRIndex": "0x1a6,0x1a7",
900        "MSRValue": "0x811",
901        "SampleAfterValue": "100000",
902        "UMask": "0x1"
903    },
904    {
905        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
906        "EventCode": "0xB7, 0xBB",
907        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
908        "MSRIndex": "0x1a6,0x1a7",
909        "MSRValue": "0x5044",
910        "SampleAfterValue": "100000",
911        "UMask": "0x1"
912    },
913    {
914        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM",
915        "EventCode": "0xB7, 0xBB",
916        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
917        "MSRIndex": "0x1a6,0x1a7",
918        "MSRValue": "0x7f44",
919        "SampleAfterValue": "100000",
920        "UMask": "0x1"
921    },
922    {
923        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION",
924        "EventCode": "0xB7, 0xBB",
925        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
926        "MSRIndex": "0x1a6,0x1a7",
927        "MSRValue": "0xff44",
928        "SampleAfterValue": "100000",
929        "UMask": "0x1"
930    },
931    {
932        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO",
933        "EventCode": "0xB7, 0xBB",
934        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
935        "MSRIndex": "0x1a6,0x1a7",
936        "MSRValue": "0x8044",
937        "SampleAfterValue": "100000",
938        "UMask": "0x1"
939    },
940    {
941        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
942        "EventCode": "0xB7, 0xBB",
943        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
944        "MSRIndex": "0x1a6,0x1a7",
945        "MSRValue": "0x144",
946        "SampleAfterValue": "100000",
947        "UMask": "0x1"
948    },
949    {
950        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
951        "EventCode": "0xB7, 0xBB",
952        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
953        "MSRIndex": "0x1a6,0x1a7",
954        "MSRValue": "0x244",
955        "SampleAfterValue": "100000",
956        "UMask": "0x1"
957    },
958    {
959        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
960        "EventCode": "0xB7, 0xBB",
961        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
962        "MSRIndex": "0x1a6,0x1a7",
963        "MSRValue": "0x444",
964        "SampleAfterValue": "100000",
965        "UMask": "0x1"
966    },
967    {
968        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE",
969        "EventCode": "0xB7, 0xBB",
970        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
971        "MSRIndex": "0x1a6,0x1a7",
972        "MSRValue": "0x744",
973        "SampleAfterValue": "100000",
974        "UMask": "0x1"
975    },
976    {
977        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
978        "EventCode": "0xB7, 0xBB",
979        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
980        "MSRIndex": "0x1a6,0x1a7",
981        "MSRValue": "0x1044",
982        "SampleAfterValue": "100000",
983        "UMask": "0x1"
984    },
985    {
986        "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM",
987        "EventCode": "0xB7, 0xBB",
988        "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
989        "MSRIndex": "0x1a6,0x1a7",
990        "MSRValue": "0x844",
991        "SampleAfterValue": "100000",
992        "UMask": "0x1"
993    },
994    {
995        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
996        "EventCode": "0xB7, 0xBB",
997        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
998        "MSRIndex": "0x1a6,0x1a7",
999        "MSRValue": "0x50ff",
1000        "SampleAfterValue": "100000",
1001        "UMask": "0x1"
1002    },
1003    {
1004        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM",
1005        "EventCode": "0xB7, 0xBB",
1006        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1007        "MSRIndex": "0x1a6,0x1a7",
1008        "MSRValue": "0x7fff",
1009        "SampleAfterValue": "100000",
1010        "UMask": "0x1"
1011    },
1012    {
1013        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION",
1014        "EventCode": "0xB7, 0xBB",
1015        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1016        "MSRIndex": "0x1a6,0x1a7",
1017        "MSRValue": "0xffff",
1018        "SampleAfterValue": "100000",
1019        "UMask": "0x1"
1020    },
1021    {
1022        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO",
1023        "EventCode": "0xB7, 0xBB",
1024        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1025        "MSRIndex": "0x1a6,0x1a7",
1026        "MSRValue": "0x80ff",
1027        "SampleAfterValue": "100000",
1028        "UMask": "0x1"
1029    },
1030    {
1031        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1032        "EventCode": "0xB7, 0xBB",
1033        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1034        "MSRIndex": "0x1a6,0x1a7",
1035        "MSRValue": "0x1ff",
1036        "SampleAfterValue": "100000",
1037        "UMask": "0x1"
1038    },
1039    {
1040        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1041        "EventCode": "0xB7, 0xBB",
1042        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1043        "MSRIndex": "0x1a6,0x1a7",
1044        "MSRValue": "0x2ff",
1045        "SampleAfterValue": "100000",
1046        "UMask": "0x1"
1047    },
1048    {
1049        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1050        "EventCode": "0xB7, 0xBB",
1051        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1052        "MSRIndex": "0x1a6,0x1a7",
1053        "MSRValue": "0x4ff",
1054        "SampleAfterValue": "100000",
1055        "UMask": "0x1"
1056    },
1057    {
1058        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE",
1059        "EventCode": "0xB7, 0xBB",
1060        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1061        "MSRIndex": "0x1a6,0x1a7",
1062        "MSRValue": "0x7ff",
1063        "SampleAfterValue": "100000",
1064        "UMask": "0x1"
1065    },
1066    {
1067        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1068        "EventCode": "0xB7, 0xBB",
1069        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1070        "MSRIndex": "0x1a6,0x1a7",
1071        "MSRValue": "0x10ff",
1072        "SampleAfterValue": "100000",
1073        "UMask": "0x1"
1074    },
1075    {
1076        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM",
1077        "EventCode": "0xB7, 0xBB",
1078        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1079        "MSRIndex": "0x1a6,0x1a7",
1080        "MSRValue": "0x8ff",
1081        "SampleAfterValue": "100000",
1082        "UMask": "0x1"
1083    },
1084    {
1085        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1086        "EventCode": "0xB7, 0xBB",
1087        "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1088        "MSRIndex": "0x1a6,0x1a7",
1089        "MSRValue": "0x5022",
1090        "SampleAfterValue": "100000",
1091        "UMask": "0x1"
1092    },
1093    {
1094        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM",
1095        "EventCode": "0xB7, 0xBB",
1096        "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1097        "MSRIndex": "0x1a6,0x1a7",
1098        "MSRValue": "0x7f22",
1099        "SampleAfterValue": "100000",
1100        "UMask": "0x1"
1101    },
1102    {
1103        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION",
1104        "EventCode": "0xB7, 0xBB",
1105        "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1106        "MSRIndex": "0x1a6,0x1a7",
1107        "MSRValue": "0xff22",
1108        "SampleAfterValue": "100000",
1109        "UMask": "0x1"
1110    },
1111    {
1112        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO",
1113        "EventCode": "0xB7, 0xBB",
1114        "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1115        "MSRIndex": "0x1a6,0x1a7",
1116        "MSRValue": "0x8022",
1117        "SampleAfterValue": "100000",
1118        "UMask": "0x1"
1119    },
1120    {
1121        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1122        "EventCode": "0xB7, 0xBB",
1123        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1124        "MSRIndex": "0x1a6,0x1a7",
1125        "MSRValue": "0x122",
1126        "SampleAfterValue": "100000",
1127        "UMask": "0x1"
1128    },
1129    {
1130        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1131        "EventCode": "0xB7, 0xBB",
1132        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1133        "MSRIndex": "0x1a6,0x1a7",
1134        "MSRValue": "0x222",
1135        "SampleAfterValue": "100000",
1136        "UMask": "0x1"
1137    },
1138    {
1139        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1140        "EventCode": "0xB7, 0xBB",
1141        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1142        "MSRIndex": "0x1a6,0x1a7",
1143        "MSRValue": "0x422",
1144        "SampleAfterValue": "100000",
1145        "UMask": "0x1"
1146    },
1147    {
1148        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE",
1149        "EventCode": "0xB7, 0xBB",
1150        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1151        "MSRIndex": "0x1a6,0x1a7",
1152        "MSRValue": "0x722",
1153        "SampleAfterValue": "100000",
1154        "UMask": "0x1"
1155    },
1156    {
1157        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1158        "EventCode": "0xB7, 0xBB",
1159        "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1160        "MSRIndex": "0x1a6,0x1a7",
1161        "MSRValue": "0x1022",
1162        "SampleAfterValue": "100000",
1163        "UMask": "0x1"
1164    },
1165    {
1166        "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM",
1167        "EventCode": "0xB7, 0xBB",
1168        "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1169        "MSRIndex": "0x1a6,0x1a7",
1170        "MSRValue": "0x822",
1171        "SampleAfterValue": "100000",
1172        "UMask": "0x1"
1173    },
1174    {
1175        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1176        "EventCode": "0xB7, 0xBB",
1177        "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1178        "MSRIndex": "0x1a6,0x1a7",
1179        "MSRValue": "0x5008",
1180        "SampleAfterValue": "100000",
1181        "UMask": "0x1"
1182    },
1183    {
1184        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM",
1185        "EventCode": "0xB7, 0xBB",
1186        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1187        "MSRIndex": "0x1a6,0x1a7",
1188        "MSRValue": "0x7f08",
1189        "SampleAfterValue": "100000",
1190        "UMask": "0x1"
1191    },
1192    {
1193        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION",
1194        "EventCode": "0xB7, 0xBB",
1195        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1196        "MSRIndex": "0x1a6,0x1a7",
1197        "MSRValue": "0xff08",
1198        "SampleAfterValue": "100000",
1199        "UMask": "0x1"
1200    },
1201    {
1202        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO",
1203        "EventCode": "0xB7, 0xBB",
1204        "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1205        "MSRIndex": "0x1a6,0x1a7",
1206        "MSRValue": "0x8008",
1207        "SampleAfterValue": "100000",
1208        "UMask": "0x1"
1209    },
1210    {
1211        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1212        "EventCode": "0xB7, 0xBB",
1213        "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1214        "MSRIndex": "0x1a6,0x1a7",
1215        "MSRValue": "0x108",
1216        "SampleAfterValue": "100000",
1217        "UMask": "0x1"
1218    },
1219    {
1220        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1221        "EventCode": "0xB7, 0xBB",
1222        "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT",
1223        "MSRIndex": "0x1a6,0x1a7",
1224        "MSRValue": "0x208",
1225        "SampleAfterValue": "100000",
1226        "UMask": "0x1"
1227    },
1228    {
1229        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1230        "EventCode": "0xB7, 0xBB",
1231        "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1232        "MSRIndex": "0x1a6,0x1a7",
1233        "MSRValue": "0x408",
1234        "SampleAfterValue": "100000",
1235        "UMask": "0x1"
1236    },
1237    {
1238        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE",
1239        "EventCode": "0xB7, 0xBB",
1240        "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1241        "MSRIndex": "0x1a6,0x1a7",
1242        "MSRValue": "0x708",
1243        "SampleAfterValue": "100000",
1244        "UMask": "0x1"
1245    },
1246    {
1247        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1248        "EventCode": "0xB7, 0xBB",
1249        "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1250        "MSRIndex": "0x1a6,0x1a7",
1251        "MSRValue": "0x1008",
1252        "SampleAfterValue": "100000",
1253        "UMask": "0x1"
1254    },
1255    {
1256        "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM",
1257        "EventCode": "0xB7, 0xBB",
1258        "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1259        "MSRIndex": "0x1a6,0x1a7",
1260        "MSRValue": "0x808",
1261        "SampleAfterValue": "100000",
1262        "UMask": "0x1"
1263    },
1264    {
1265        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1266        "EventCode": "0xB7, 0xBB",
1267        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1268        "MSRIndex": "0x1a6,0x1a7",
1269        "MSRValue": "0x5077",
1270        "SampleAfterValue": "100000",
1271        "UMask": "0x1"
1272    },
1273    {
1274        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM",
1275        "EventCode": "0xB7, 0xBB",
1276        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1277        "MSRIndex": "0x1a6,0x1a7",
1278        "MSRValue": "0x7f77",
1279        "SampleAfterValue": "100000",
1280        "UMask": "0x1"
1281    },
1282    {
1283        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION",
1284        "EventCode": "0xB7, 0xBB",
1285        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1286        "MSRIndex": "0x1a6,0x1a7",
1287        "MSRValue": "0xff77",
1288        "SampleAfterValue": "100000",
1289        "UMask": "0x1"
1290    },
1291    {
1292        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO",
1293        "EventCode": "0xB7, 0xBB",
1294        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1295        "MSRIndex": "0x1a6,0x1a7",
1296        "MSRValue": "0x8077",
1297        "SampleAfterValue": "100000",
1298        "UMask": "0x1"
1299    },
1300    {
1301        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1302        "EventCode": "0xB7, 0xBB",
1303        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1304        "MSRIndex": "0x1a6,0x1a7",
1305        "MSRValue": "0x177",
1306        "SampleAfterValue": "100000",
1307        "UMask": "0x1"
1308    },
1309    {
1310        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1311        "EventCode": "0xB7, 0xBB",
1312        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1313        "MSRIndex": "0x1a6,0x1a7",
1314        "MSRValue": "0x277",
1315        "SampleAfterValue": "100000",
1316        "UMask": "0x1"
1317    },
1318    {
1319        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1320        "EventCode": "0xB7, 0xBB",
1321        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1322        "MSRIndex": "0x1a6,0x1a7",
1323        "MSRValue": "0x477",
1324        "SampleAfterValue": "100000",
1325        "UMask": "0x1"
1326    },
1327    {
1328        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE",
1329        "EventCode": "0xB7, 0xBB",
1330        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1331        "MSRIndex": "0x1a6,0x1a7",
1332        "MSRValue": "0x777",
1333        "SampleAfterValue": "100000",
1334        "UMask": "0x1"
1335    },
1336    {
1337        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1338        "EventCode": "0xB7, 0xBB",
1339        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1340        "MSRIndex": "0x1a6,0x1a7",
1341        "MSRValue": "0x1077",
1342        "SampleAfterValue": "100000",
1343        "UMask": "0x1"
1344    },
1345    {
1346        "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
1347        "EventCode": "0xB7, 0xBB",
1348        "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1349        "MSRIndex": "0x1a6,0x1a7",
1350        "MSRValue": "0x877",
1351        "SampleAfterValue": "100000",
1352        "UMask": "0x1"
1353    },
1354    {
1355        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1356        "EventCode": "0xB7, 0xBB",
1357        "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1358        "MSRIndex": "0x1a6,0x1a7",
1359        "MSRValue": "0x5033",
1360        "SampleAfterValue": "100000",
1361        "UMask": "0x1"
1362    },
1363    {
1364        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM",
1365        "EventCode": "0xB7, 0xBB",
1366        "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1367        "MSRIndex": "0x1a6,0x1a7",
1368        "MSRValue": "0x7f33",
1369        "SampleAfterValue": "100000",
1370        "UMask": "0x1"
1371    },
1372    {
1373        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION",
1374        "EventCode": "0xB7, 0xBB",
1375        "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1376        "MSRIndex": "0x1a6,0x1a7",
1377        "MSRValue": "0xff33",
1378        "SampleAfterValue": "100000",
1379        "UMask": "0x1"
1380    },
1381    {
1382        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO",
1383        "EventCode": "0xB7, 0xBB",
1384        "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1385        "MSRIndex": "0x1a6,0x1a7",
1386        "MSRValue": "0x8033",
1387        "SampleAfterValue": "100000",
1388        "UMask": "0x1"
1389    },
1390    {
1391        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1392        "EventCode": "0xB7, 0xBB",
1393        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1394        "MSRIndex": "0x1a6,0x1a7",
1395        "MSRValue": "0x133",
1396        "SampleAfterValue": "100000",
1397        "UMask": "0x1"
1398    },
1399    {
1400        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1401        "EventCode": "0xB7, 0xBB",
1402        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1403        "MSRIndex": "0x1a6,0x1a7",
1404        "MSRValue": "0x233",
1405        "SampleAfterValue": "100000",
1406        "UMask": "0x1"
1407    },
1408    {
1409        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1410        "EventCode": "0xB7, 0xBB",
1411        "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1412        "MSRIndex": "0x1a6,0x1a7",
1413        "MSRValue": "0x433",
1414        "SampleAfterValue": "100000",
1415        "UMask": "0x1"
1416    },
1417    {
1418        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE",
1419        "EventCode": "0xB7, 0xBB",
1420        "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1421        "MSRIndex": "0x1a6,0x1a7",
1422        "MSRValue": "0x733",
1423        "SampleAfterValue": "100000",
1424        "UMask": "0x1"
1425    },
1426    {
1427        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1428        "EventCode": "0xB7, 0xBB",
1429        "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1430        "MSRIndex": "0x1a6,0x1a7",
1431        "MSRValue": "0x1033",
1432        "SampleAfterValue": "100000",
1433        "UMask": "0x1"
1434    },
1435    {
1436        "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM",
1437        "EventCode": "0xB7, 0xBB",
1438        "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1439        "MSRIndex": "0x1a6,0x1a7",
1440        "MSRValue": "0x833",
1441        "SampleAfterValue": "100000",
1442        "UMask": "0x1"
1443    },
1444    {
1445        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1446        "EventCode": "0xB7, 0xBB",
1447        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1448        "MSRIndex": "0x1a6,0x1a7",
1449        "MSRValue": "0x5003",
1450        "SampleAfterValue": "100000",
1451        "UMask": "0x1"
1452    },
1453    {
1454        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM",
1455        "EventCode": "0xB7, 0xBB",
1456        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1457        "MSRIndex": "0x1a6,0x1a7",
1458        "MSRValue": "0x7f03",
1459        "SampleAfterValue": "100000",
1460        "UMask": "0x1"
1461    },
1462    {
1463        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION",
1464        "EventCode": "0xB7, 0xBB",
1465        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1466        "MSRIndex": "0x1a6,0x1a7",
1467        "MSRValue": "0xff03",
1468        "SampleAfterValue": "100000",
1469        "UMask": "0x1"
1470    },
1471    {
1472        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO",
1473        "EventCode": "0xB7, 0xBB",
1474        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1475        "MSRIndex": "0x1a6,0x1a7",
1476        "MSRValue": "0x8003",
1477        "SampleAfterValue": "100000",
1478        "UMask": "0x1"
1479    },
1480    {
1481        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1482        "EventCode": "0xB7, 0xBB",
1483        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1484        "MSRIndex": "0x1a6,0x1a7",
1485        "MSRValue": "0x103",
1486        "SampleAfterValue": "100000",
1487        "UMask": "0x1"
1488    },
1489    {
1490        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1491        "EventCode": "0xB7, 0xBB",
1492        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1493        "MSRIndex": "0x1a6,0x1a7",
1494        "MSRValue": "0x203",
1495        "SampleAfterValue": "100000",
1496        "UMask": "0x1"
1497    },
1498    {
1499        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1500        "EventCode": "0xB7, 0xBB",
1501        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1502        "MSRIndex": "0x1a6,0x1a7",
1503        "MSRValue": "0x403",
1504        "SampleAfterValue": "100000",
1505        "UMask": "0x1"
1506    },
1507    {
1508        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE",
1509        "EventCode": "0xB7, 0xBB",
1510        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1511        "MSRIndex": "0x1a6,0x1a7",
1512        "MSRValue": "0x703",
1513        "SampleAfterValue": "100000",
1514        "UMask": "0x1"
1515    },
1516    {
1517        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1518        "EventCode": "0xB7, 0xBB",
1519        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1520        "MSRIndex": "0x1a6,0x1a7",
1521        "MSRValue": "0x1003",
1522        "SampleAfterValue": "100000",
1523        "UMask": "0x1"
1524    },
1525    {
1526        "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM",
1527        "EventCode": "0xB7, 0xBB",
1528        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
1529        "MSRIndex": "0x1a6,0x1a7",
1530        "MSRValue": "0x803",
1531        "SampleAfterValue": "100000",
1532        "UMask": "0x1"
1533    },
1534    {
1535        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1536        "EventCode": "0xB7, 0xBB",
1537        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1538        "MSRIndex": "0x1a6,0x1a7",
1539        "MSRValue": "0x5001",
1540        "SampleAfterValue": "100000",
1541        "UMask": "0x1"
1542    },
1543    {
1544        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
1545        "EventCode": "0xB7, 0xBB",
1546        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
1547        "MSRIndex": "0x1a6,0x1a7",
1548        "MSRValue": "0x7f01",
1549        "SampleAfterValue": "100000",
1550        "UMask": "0x1"
1551    },
1552    {
1553        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION",
1554        "EventCode": "0xB7, 0xBB",
1555        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
1556        "MSRIndex": "0x1a6,0x1a7",
1557        "MSRValue": "0xff01",
1558        "SampleAfterValue": "100000",
1559        "UMask": "0x1"
1560    },
1561    {
1562        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO",
1563        "EventCode": "0xB7, 0xBB",
1564        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
1565        "MSRIndex": "0x1a6,0x1a7",
1566        "MSRValue": "0x8001",
1567        "SampleAfterValue": "100000",
1568        "UMask": "0x1"
1569    },
1570    {
1571        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1572        "EventCode": "0xB7, 0xBB",
1573        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
1574        "MSRIndex": "0x1a6,0x1a7",
1575        "MSRValue": "0x101",
1576        "SampleAfterValue": "100000",
1577        "UMask": "0x1"
1578    },
1579    {
1580        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1581        "EventCode": "0xB7, 0xBB",
1582        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
1583        "MSRIndex": "0x1a6,0x1a7",
1584        "MSRValue": "0x201",
1585        "SampleAfterValue": "100000",
1586        "UMask": "0x1"
1587    },
1588    {
1589        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1590        "EventCode": "0xB7, 0xBB",
1591        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
1592        "MSRIndex": "0x1a6,0x1a7",
1593        "MSRValue": "0x401",
1594        "SampleAfterValue": "100000",
1595        "UMask": "0x1"
1596    },
1597    {
1598        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE",
1599        "EventCode": "0xB7, 0xBB",
1600        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
1601        "MSRIndex": "0x1a6,0x1a7",
1602        "MSRValue": "0x701",
1603        "SampleAfterValue": "100000",
1604        "UMask": "0x1"
1605    },
1606    {
1607        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1608        "EventCode": "0xB7, 0xBB",
1609        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1610        "MSRIndex": "0x1a6,0x1a7",
1611        "MSRValue": "0x1001",
1612        "SampleAfterValue": "100000",
1613        "UMask": "0x1"
1614    },
1615    {
1616        "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
1617        "EventCode": "0xB7, 0xBB",
1618        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
1619        "MSRIndex": "0x1a6,0x1a7",
1620        "MSRValue": "0x801",
1621        "SampleAfterValue": "100000",
1622        "UMask": "0x1"
1623    },
1624    {
1625        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1626        "EventCode": "0xB7, 0xBB",
1627        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1628        "MSRIndex": "0x1a6,0x1a7",
1629        "MSRValue": "0x5004",
1630        "SampleAfterValue": "100000",
1631        "UMask": "0x1"
1632    },
1633    {
1634        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM",
1635        "EventCode": "0xB7, 0xBB",
1636        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
1637        "MSRIndex": "0x1a6,0x1a7",
1638        "MSRValue": "0x7f04",
1639        "SampleAfterValue": "100000",
1640        "UMask": "0x1"
1641    },
1642    {
1643        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION",
1644        "EventCode": "0xB7, 0xBB",
1645        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
1646        "MSRIndex": "0x1a6,0x1a7",
1647        "MSRValue": "0xff04",
1648        "SampleAfterValue": "100000",
1649        "UMask": "0x1"
1650    },
1651    {
1652        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO",
1653        "EventCode": "0xB7, 0xBB",
1654        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
1655        "MSRIndex": "0x1a6,0x1a7",
1656        "MSRValue": "0x8004",
1657        "SampleAfterValue": "100000",
1658        "UMask": "0x1"
1659    },
1660    {
1661        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1662        "EventCode": "0xB7, 0xBB",
1663        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
1664        "MSRIndex": "0x1a6,0x1a7",
1665        "MSRValue": "0x104",
1666        "SampleAfterValue": "100000",
1667        "UMask": "0x1"
1668    },
1669    {
1670        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1671        "EventCode": "0xB7, 0xBB",
1672        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1673        "MSRIndex": "0x1a6,0x1a7",
1674        "MSRValue": "0x204",
1675        "SampleAfterValue": "100000",
1676        "UMask": "0x1"
1677    },
1678    {
1679        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1680        "EventCode": "0xB7, 0xBB",
1681        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1682        "MSRIndex": "0x1a6,0x1a7",
1683        "MSRValue": "0x404",
1684        "SampleAfterValue": "100000",
1685        "UMask": "0x1"
1686    },
1687    {
1688        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE",
1689        "EventCode": "0xB7, 0xBB",
1690        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
1691        "MSRIndex": "0x1a6,0x1a7",
1692        "MSRValue": "0x704",
1693        "SampleAfterValue": "100000",
1694        "UMask": "0x1"
1695    },
1696    {
1697        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1698        "EventCode": "0xB7, 0xBB",
1699        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1700        "MSRIndex": "0x1a6,0x1a7",
1701        "MSRValue": "0x1004",
1702        "SampleAfterValue": "100000",
1703        "UMask": "0x1"
1704    },
1705    {
1706        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
1707        "EventCode": "0xB7, 0xBB",
1708        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
1709        "MSRIndex": "0x1a6,0x1a7",
1710        "MSRValue": "0x804",
1711        "SampleAfterValue": "100000",
1712        "UMask": "0x1"
1713    },
1714    {
1715        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1716        "EventCode": "0xB7, 0xBB",
1717        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1718        "MSRIndex": "0x1a6,0x1a7",
1719        "MSRValue": "0x5002",
1720        "SampleAfterValue": "100000",
1721        "UMask": "0x1"
1722    },
1723    {
1724        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM",
1725        "EventCode": "0xB7, 0xBB",
1726        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
1727        "MSRIndex": "0x1a6,0x1a7",
1728        "MSRValue": "0x7f02",
1729        "SampleAfterValue": "100000",
1730        "UMask": "0x1"
1731    },
1732    {
1733        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION",
1734        "EventCode": "0xB7, 0xBB",
1735        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
1736        "MSRIndex": "0x1a6,0x1a7",
1737        "MSRValue": "0xff02",
1738        "SampleAfterValue": "100000",
1739        "UMask": "0x1"
1740    },
1741    {
1742        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO",
1743        "EventCode": "0xB7, 0xBB",
1744        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
1745        "MSRIndex": "0x1a6,0x1a7",
1746        "MSRValue": "0x8002",
1747        "SampleAfterValue": "100000",
1748        "UMask": "0x1"
1749    },
1750    {
1751        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1752        "EventCode": "0xB7, 0xBB",
1753        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
1754        "MSRIndex": "0x1a6,0x1a7",
1755        "MSRValue": "0x102",
1756        "SampleAfterValue": "100000",
1757        "UMask": "0x1"
1758    },
1759    {
1760        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1761        "EventCode": "0xB7, 0xBB",
1762        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
1763        "MSRIndex": "0x1a6,0x1a7",
1764        "MSRValue": "0x202",
1765        "SampleAfterValue": "100000",
1766        "UMask": "0x1"
1767    },
1768    {
1769        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1770        "EventCode": "0xB7, 0xBB",
1771        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
1772        "MSRIndex": "0x1a6,0x1a7",
1773        "MSRValue": "0x402",
1774        "SampleAfterValue": "100000",
1775        "UMask": "0x1"
1776    },
1777    {
1778        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE",
1779        "EventCode": "0xB7, 0xBB",
1780        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
1781        "MSRIndex": "0x1a6,0x1a7",
1782        "MSRValue": "0x702",
1783        "SampleAfterValue": "100000",
1784        "UMask": "0x1"
1785    },
1786    {
1787        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1788        "EventCode": "0xB7, 0xBB",
1789        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1790        "MSRIndex": "0x1a6,0x1a7",
1791        "MSRValue": "0x1002",
1792        "SampleAfterValue": "100000",
1793        "UMask": "0x1"
1794    },
1795    {
1796        "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM",
1797        "EventCode": "0xB7, 0xBB",
1798        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
1799        "MSRIndex": "0x1a6,0x1a7",
1800        "MSRValue": "0x802",
1801        "SampleAfterValue": "100000",
1802        "UMask": "0x1"
1803    },
1804    {
1805        "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1806        "EventCode": "0xB7, 0xBB",
1807        "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1808        "MSRIndex": "0x1a6,0x1a7",
1809        "MSRValue": "0x5080",
1810        "SampleAfterValue": "100000",
1811        "UMask": "0x1"
1812    },
1813    {
1814        "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM",
1815        "EventCode": "0xB7, 0xBB",
1816        "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
1817        "MSRIndex": "0x1a6,0x1a7",
1818        "MSRValue": "0x7f80",
1819        "SampleAfterValue": "100000",
1820        "UMask": "0x1"
1821    },
1822    {
1823        "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION",
1824        "EventCode": "0xB7, 0xBB",
1825        "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
1826        "MSRIndex": "0x1a6,0x1a7",
1827        "MSRValue": "0xff80",
1828        "SampleAfterValue": "100000",
1829        "UMask": "0x1"
1830    },
1831    {
1832        "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO",
1833        "EventCode": "0xB7, 0xBB",
1834        "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
1835        "MSRIndex": "0x1a6,0x1a7",
1836        "MSRValue": "0x8080",
1837        "SampleAfterValue": "100000",
1838        "UMask": "0x1"
1839    },
1840    {
1841        "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1842        "EventCode": "0xB7, 0xBB",
1843        "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
1844        "MSRIndex": "0x1a6,0x1a7",
1845        "MSRValue": "0x180",
1846        "SampleAfterValue": "100000",
1847        "UMask": "0x1"
1848    },
1849    {
1850        "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1851        "EventCode": "0xB7, 0xBB",
1852        "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
1853        "MSRIndex": "0x1a6,0x1a7",
1854        "MSRValue": "0x280",
1855        "SampleAfterValue": "100000",
1856        "UMask": "0x1"
1857    },
1858    {
1859        "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1860        "EventCode": "0xB7, 0xBB",
1861        "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
1862        "MSRIndex": "0x1a6,0x1a7",
1863        "MSRValue": "0x480",
1864        "SampleAfterValue": "100000",
1865        "UMask": "0x1"
1866    },
1867    {
1868        "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE",
1869        "EventCode": "0xB7, 0xBB",
1870        "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
1871        "MSRIndex": "0x1a6,0x1a7",
1872        "MSRValue": "0x780",
1873        "SampleAfterValue": "100000",
1874        "UMask": "0x1"
1875    },
1876    {
1877        "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1878        "EventCode": "0xB7, 0xBB",
1879        "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1880        "MSRIndex": "0x1a6,0x1a7",
1881        "MSRValue": "0x1080",
1882        "SampleAfterValue": "100000",
1883        "UMask": "0x1"
1884    },
1885    {
1886        "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM",
1887        "EventCode": "0xB7, 0xBB",
1888        "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
1889        "MSRIndex": "0x1a6,0x1a7",
1890        "MSRValue": "0x880",
1891        "SampleAfterValue": "100000",
1892        "UMask": "0x1"
1893    },
1894    {
1895        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1896        "EventCode": "0xB7, 0xBB",
1897        "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1898        "MSRIndex": "0x1a6,0x1a7",
1899        "MSRValue": "0x5050",
1900        "SampleAfterValue": "100000",
1901        "UMask": "0x1"
1902    },
1903    {
1904        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM",
1905        "EventCode": "0xB7, 0xBB",
1906        "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
1907        "MSRIndex": "0x1a6,0x1a7",
1908        "MSRValue": "0x7f50",
1909        "SampleAfterValue": "100000",
1910        "UMask": "0x1"
1911    },
1912    {
1913        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION",
1914        "EventCode": "0xB7, 0xBB",
1915        "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
1916        "MSRIndex": "0x1a6,0x1a7",
1917        "MSRValue": "0xff50",
1918        "SampleAfterValue": "100000",
1919        "UMask": "0x1"
1920    },
1921    {
1922        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO",
1923        "EventCode": "0xB7, 0xBB",
1924        "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
1925        "MSRIndex": "0x1a6,0x1a7",
1926        "MSRValue": "0x8050",
1927        "SampleAfterValue": "100000",
1928        "UMask": "0x1"
1929    },
1930    {
1931        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1932        "EventCode": "0xB7, 0xBB",
1933        "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
1934        "MSRIndex": "0x1a6,0x1a7",
1935        "MSRValue": "0x150",
1936        "SampleAfterValue": "100000",
1937        "UMask": "0x1"
1938    },
1939    {
1940        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1941        "EventCode": "0xB7, 0xBB",
1942        "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
1943        "MSRIndex": "0x1a6,0x1a7",
1944        "MSRValue": "0x250",
1945        "SampleAfterValue": "100000",
1946        "UMask": "0x1"
1947    },
1948    {
1949        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1950        "EventCode": "0xB7, 0xBB",
1951        "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
1952        "MSRIndex": "0x1a6,0x1a7",
1953        "MSRValue": "0x450",
1954        "SampleAfterValue": "100000",
1955        "UMask": "0x1"
1956    },
1957    {
1958        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE",
1959        "EventCode": "0xB7, 0xBB",
1960        "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
1961        "MSRIndex": "0x1a6,0x1a7",
1962        "MSRValue": "0x750",
1963        "SampleAfterValue": "100000",
1964        "UMask": "0x1"
1965    },
1966    {
1967        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1968        "EventCode": "0xB7, 0xBB",
1969        "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1970        "MSRIndex": "0x1a6,0x1a7",
1971        "MSRValue": "0x1050",
1972        "SampleAfterValue": "100000",
1973        "UMask": "0x1"
1974    },
1975    {
1976        "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM",
1977        "EventCode": "0xB7, 0xBB",
1978        "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
1979        "MSRIndex": "0x1a6,0x1a7",
1980        "MSRValue": "0x850",
1981        "SampleAfterValue": "100000",
1982        "UMask": "0x1"
1983    },
1984    {
1985        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1986        "EventCode": "0xB7, 0xBB",
1987        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1988        "MSRIndex": "0x1a6,0x1a7",
1989        "MSRValue": "0x5010",
1990        "SampleAfterValue": "100000",
1991        "UMask": "0x1"
1992    },
1993    {
1994        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
1995        "EventCode": "0xB7, 0xBB",
1996        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
1997        "MSRIndex": "0x1a6,0x1a7",
1998        "MSRValue": "0x7f10",
1999        "SampleAfterValue": "100000",
2000        "UMask": "0x1"
2001    },
2002    {
2003        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION",
2004        "EventCode": "0xB7, 0xBB",
2005        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2006        "MSRIndex": "0x1a6,0x1a7",
2007        "MSRValue": "0xff10",
2008        "SampleAfterValue": "100000",
2009        "UMask": "0x1"
2010    },
2011    {
2012        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO",
2013        "EventCode": "0xB7, 0xBB",
2014        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2015        "MSRIndex": "0x1a6,0x1a7",
2016        "MSRValue": "0x8010",
2017        "SampleAfterValue": "100000",
2018        "UMask": "0x1"
2019    },
2020    {
2021        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2022        "EventCode": "0xB7, 0xBB",
2023        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2024        "MSRIndex": "0x1a6,0x1a7",
2025        "MSRValue": "0x110",
2026        "SampleAfterValue": "100000",
2027        "UMask": "0x1"
2028    },
2029    {
2030        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2031        "EventCode": "0xB7, 0xBB",
2032        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2033        "MSRIndex": "0x1a6,0x1a7",
2034        "MSRValue": "0x210",
2035        "SampleAfterValue": "100000",
2036        "UMask": "0x1"
2037    },
2038    {
2039        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2040        "EventCode": "0xB7, 0xBB",
2041        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2042        "MSRIndex": "0x1a6,0x1a7",
2043        "MSRValue": "0x410",
2044        "SampleAfterValue": "100000",
2045        "UMask": "0x1"
2046    },
2047    {
2048        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE",
2049        "EventCode": "0xB7, 0xBB",
2050        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2051        "MSRIndex": "0x1a6,0x1a7",
2052        "MSRValue": "0x710",
2053        "SampleAfterValue": "100000",
2054        "UMask": "0x1"
2055    },
2056    {
2057        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2058        "EventCode": "0xB7, 0xBB",
2059        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2060        "MSRIndex": "0x1a6,0x1a7",
2061        "MSRValue": "0x1010",
2062        "SampleAfterValue": "100000",
2063        "UMask": "0x1"
2064    },
2065    {
2066        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
2067        "EventCode": "0xB7, 0xBB",
2068        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2069        "MSRIndex": "0x1a6,0x1a7",
2070        "MSRValue": "0x810",
2071        "SampleAfterValue": "100000",
2072        "UMask": "0x1"
2073    },
2074    {
2075        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2076        "EventCode": "0xB7, 0xBB",
2077        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2078        "MSRIndex": "0x1a6,0x1a7",
2079        "MSRValue": "0x5040",
2080        "SampleAfterValue": "100000",
2081        "UMask": "0x1"
2082    },
2083    {
2084        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM",
2085        "EventCode": "0xB7, 0xBB",
2086        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2087        "MSRIndex": "0x1a6,0x1a7",
2088        "MSRValue": "0x7f40",
2089        "SampleAfterValue": "100000",
2090        "UMask": "0x1"
2091    },
2092    {
2093        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION",
2094        "EventCode": "0xB7, 0xBB",
2095        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2096        "MSRIndex": "0x1a6,0x1a7",
2097        "MSRValue": "0xff40",
2098        "SampleAfterValue": "100000",
2099        "UMask": "0x1"
2100    },
2101    {
2102        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO",
2103        "EventCode": "0xB7, 0xBB",
2104        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2105        "MSRIndex": "0x1a6,0x1a7",
2106        "MSRValue": "0x8040",
2107        "SampleAfterValue": "100000",
2108        "UMask": "0x1"
2109    },
2110    {
2111        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2112        "EventCode": "0xB7, 0xBB",
2113        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2114        "MSRIndex": "0x1a6,0x1a7",
2115        "MSRValue": "0x140",
2116        "SampleAfterValue": "100000",
2117        "UMask": "0x1"
2118    },
2119    {
2120        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2121        "EventCode": "0xB7, 0xBB",
2122        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2123        "MSRIndex": "0x1a6,0x1a7",
2124        "MSRValue": "0x240",
2125        "SampleAfterValue": "100000",
2126        "UMask": "0x1"
2127    },
2128    {
2129        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2130        "EventCode": "0xB7, 0xBB",
2131        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2132        "MSRIndex": "0x1a6,0x1a7",
2133        "MSRValue": "0x440",
2134        "SampleAfterValue": "100000",
2135        "UMask": "0x1"
2136    },
2137    {
2138        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE",
2139        "EventCode": "0xB7, 0xBB",
2140        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2141        "MSRIndex": "0x1a6,0x1a7",
2142        "MSRValue": "0x740",
2143        "SampleAfterValue": "100000",
2144        "UMask": "0x1"
2145    },
2146    {
2147        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2148        "EventCode": "0xB7, 0xBB",
2149        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2150        "MSRIndex": "0x1a6,0x1a7",
2151        "MSRValue": "0x1040",
2152        "SampleAfterValue": "100000",
2153        "UMask": "0x1"
2154    },
2155    {
2156        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM",
2157        "EventCode": "0xB7, 0xBB",
2158        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2159        "MSRIndex": "0x1a6,0x1a7",
2160        "MSRValue": "0x840",
2161        "SampleAfterValue": "100000",
2162        "UMask": "0x1"
2163    },
2164    {
2165        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2166        "EventCode": "0xB7, 0xBB",
2167        "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2168        "MSRIndex": "0x1a6,0x1a7",
2169        "MSRValue": "0x5020",
2170        "SampleAfterValue": "100000",
2171        "UMask": "0x1"
2172    },
2173    {
2174        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM",
2175        "EventCode": "0xB7, 0xBB",
2176        "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2177        "MSRIndex": "0x1a6,0x1a7",
2178        "MSRValue": "0x7f20",
2179        "SampleAfterValue": "100000",
2180        "UMask": "0x1"
2181    },
2182    {
2183        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION",
2184        "EventCode": "0xB7, 0xBB",
2185        "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2186        "MSRIndex": "0x1a6,0x1a7",
2187        "MSRValue": "0xff20",
2188        "SampleAfterValue": "100000",
2189        "UMask": "0x1"
2190    },
2191    {
2192        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO",
2193        "EventCode": "0xB7, 0xBB",
2194        "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2195        "MSRIndex": "0x1a6,0x1a7",
2196        "MSRValue": "0x8020",
2197        "SampleAfterValue": "100000",
2198        "UMask": "0x1"
2199    },
2200    {
2201        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2202        "EventCode": "0xB7, 0xBB",
2203        "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
2204        "MSRIndex": "0x1a6,0x1a7",
2205        "MSRValue": "0x120",
2206        "SampleAfterValue": "100000",
2207        "UMask": "0x1"
2208    },
2209    {
2210        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2211        "EventCode": "0xB7, 0xBB",
2212        "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
2213        "MSRIndex": "0x1a6,0x1a7",
2214        "MSRValue": "0x220",
2215        "SampleAfterValue": "100000",
2216        "UMask": "0x1"
2217    },
2218    {
2219        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2220        "EventCode": "0xB7, 0xBB",
2221        "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
2222        "MSRIndex": "0x1a6,0x1a7",
2223        "MSRValue": "0x420",
2224        "SampleAfterValue": "100000",
2225        "UMask": "0x1"
2226    },
2227    {
2228        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE",
2229        "EventCode": "0xB7, 0xBB",
2230        "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
2231        "MSRIndex": "0x1a6,0x1a7",
2232        "MSRValue": "0x720",
2233        "SampleAfterValue": "100000",
2234        "UMask": "0x1"
2235    },
2236    {
2237        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2238        "EventCode": "0xB7, 0xBB",
2239        "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2240        "MSRIndex": "0x1a6,0x1a7",
2241        "MSRValue": "0x1020",
2242        "SampleAfterValue": "100000",
2243        "UMask": "0x1"
2244    },
2245    {
2246        "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
2247        "EventCode": "0xB7, 0xBB",
2248        "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
2249        "MSRIndex": "0x1a6,0x1a7",
2250        "MSRValue": "0x820",
2251        "SampleAfterValue": "100000",
2252        "UMask": "0x1"
2253    },
2254    {
2255        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2256        "EventCode": "0xB7, 0xBB",
2257        "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2258        "MSRIndex": "0x1a6,0x1a7",
2259        "MSRValue": "0x5070",
2260        "SampleAfterValue": "100000",
2261        "UMask": "0x1"
2262    },
2263    {
2264        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM",
2265        "EventCode": "0xB7, 0xBB",
2266        "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
2267        "MSRIndex": "0x1a6,0x1a7",
2268        "MSRValue": "0x7f70",
2269        "SampleAfterValue": "100000",
2270        "UMask": "0x1"
2271    },
2272    {
2273        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION",
2274        "EventCode": "0xB7, 0xBB",
2275        "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
2276        "MSRIndex": "0x1a6,0x1a7",
2277        "MSRValue": "0xff70",
2278        "SampleAfterValue": "100000",
2279        "UMask": "0x1"
2280    },
2281    {
2282        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO",
2283        "EventCode": "0xB7, 0xBB",
2284        "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
2285        "MSRIndex": "0x1a6,0x1a7",
2286        "MSRValue": "0x8070",
2287        "SampleAfterValue": "100000",
2288        "UMask": "0x1"
2289    },
2290    {
2291        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2292        "EventCode": "0xB7, 0xBB",
2293        "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
2294        "MSRIndex": "0x1a6,0x1a7",
2295        "MSRValue": "0x170",
2296        "SampleAfterValue": "100000",
2297        "UMask": "0x1"
2298    },
2299    {
2300        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2301        "EventCode": "0xB7, 0xBB",
2302        "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
2303        "MSRIndex": "0x1a6,0x1a7",
2304        "MSRValue": "0x270",
2305        "SampleAfterValue": "100000",
2306        "UMask": "0x1"
2307    },
2308    {
2309        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2310        "EventCode": "0xB7, 0xBB",
2311        "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
2312        "MSRIndex": "0x1a6,0x1a7",
2313        "MSRValue": "0x470",
2314        "SampleAfterValue": "100000",
2315        "UMask": "0x1"
2316    },
2317    {
2318        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE",
2319        "EventCode": "0xB7, 0xBB",
2320        "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
2321        "MSRIndex": "0x1a6,0x1a7",
2322        "MSRValue": "0x770",
2323        "SampleAfterValue": "100000",
2324        "UMask": "0x1"
2325    },
2326    {
2327        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2328        "EventCode": "0xB7, 0xBB",
2329        "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2330        "MSRIndex": "0x1a6,0x1a7",
2331        "MSRValue": "0x1070",
2332        "SampleAfterValue": "100000",
2333        "UMask": "0x1"
2334    },
2335    {
2336        "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM",
2337        "EventCode": "0xB7, 0xBB",
2338        "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
2339        "MSRIndex": "0x1a6,0x1a7",
2340        "MSRValue": "0x870",
2341        "SampleAfterValue": "100000",
2342        "UMask": "0x1"
2343    },
2344    {
2345        "BriefDescription": "Super Queue LRU hints sent to LLC",
2346        "EventCode": "0xF4",
2347        "EventName": "SQ_MISC.LRU_HINTS",
2348        "SampleAfterValue": "2000000",
2349        "UMask": "0x4"
2350    },
2351    {
2352        "BriefDescription": "Super Queue lock splits across a cache line",
2353        "EventCode": "0xF4",
2354        "EventName": "SQ_MISC.SPLIT_LOCK",
2355        "SampleAfterValue": "2000000",
2356        "UMask": "0x10"
2357    },
2358    {
2359        "BriefDescription": "Loads delayed with at-Retirement block code",
2360        "EventCode": "0x6",
2361        "EventName": "STORE_BLOCKS.AT_RET",
2362        "SampleAfterValue": "200000",
2363        "UMask": "0x4"
2364    },
2365    {
2366        "BriefDescription": "Cacheable loads delayed with L1D block code",
2367        "EventCode": "0x6",
2368        "EventName": "STORE_BLOCKS.L1D_BLOCK",
2369        "SampleAfterValue": "200000",
2370        "UMask": "0x8"
2371    }
2372]
2373