1[ 2 { 3 "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL", 4 "EventCode": "0x84", 5 "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", 6 "PerPkg": "1", 7 "UMask": "0x1", 8 "Unit": "ARB" 9 }, 10 { 11 "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.", 12 "EventCode": "0x85", 13 "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", 14 "PerPkg": "1", 15 "UMask": "0x1", 16 "Unit": "ARB" 17 }, 18 { 19 "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.", 20 "EventCode": "0x85", 21 "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", 22 "PerPkg": "1", 23 "UMask": "0x2", 24 "Unit": "ARB" 25 }, 26 { 27 "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD", 28 "EventCode": "0x81", 29 "EventName": "UNC_ARB_DAT_REQUESTS.RD", 30 "PerPkg": "1", 31 "UMask": "0x2", 32 "Unit": "ARB" 33 }, 34 { 35 "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL", 36 "EventCode": "0x85", 37 "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", 38 "PerPkg": "1", 39 "UMask": "0x1", 40 "Unit": "ARB" 41 }, 42 { 43 "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]", 44 "EventCode": "0x80", 45 "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", 46 "PerPkg": "1", 47 "UMask": "0x2", 48 "Unit": "ARB" 49 }, 50 { 51 "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", 52 "EventCode": "0x81", 53 "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", 54 "PerPkg": "1", 55 "UMask": "0x2", 56 "Unit": "ARB" 57 }, 58 { 59 "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", 60 "EventCode": "0x80", 61 "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", 62 "PerPkg": "1", 63 "UMask": "0x1", 64 "Unit": "ARB" 65 }, 66 { 67 "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]", 68 "EventCode": "0x80", 69 "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", 70 "PerPkg": "1", 71 "UMask": "0x2", 72 "Unit": "ARB" 73 }, 74 { 75 "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", 76 "EventCode": "0x81", 77 "EventName": "UNC_ARB_TRK_REQUESTS.ALL", 78 "PerPkg": "1", 79 "UMask": "0x1", 80 "Unit": "ARB" 81 }, 82 { 83 "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]", 84 "EventCode": "0x81", 85 "EventName": "UNC_ARB_TRK_REQUESTS.RD", 86 "PerPkg": "1", 87 "UMask": "0x2", 88 "Unit": "ARB" 89 }, 90 { 91 "BriefDescription": "UNC_CLOCK.SOCKET", 92 "EventCode": "0xff", 93 "EventName": "UNC_CLOCK.SOCKET", 94 "PerPkg": "1", 95 "Unit": "CLOCK" 96 }, 97 { 98 "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", 99 "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", 100 "PerPkg": "1", 101 "Unit": "imc" 102 }, 103 { 104 "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 105 "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", 106 "PerPkg": "1", 107 "Unit": "imc" 108 }, 109 { 110 "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", 111 "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", 112 "PerPkg": "1", 113 "Unit": "imc" 114 }, 115 { 116 "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", 117 "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", 118 "PerPkg": "1", 119 "Unit": "imc" 120 }, 121 { 122 "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 123 "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", 124 "PerPkg": "1", 125 "Unit": "imc" 126 }, 127 { 128 "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", 129 "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", 130 "PerPkg": "1", 131 "Unit": "imc" 132 } 133] 134