1[
2    {
3        "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL",
4        "EventCode": "0x84",
5        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
6        "PerPkg": "1",
7        "UMask": "0x1",
8        "Unit": "ARB"
9    },
10    {
11        "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
12        "EventCode": "0x85",
13        "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
14        "PerPkg": "1",
15        "UMask": "0x1",
16        "Unit": "ARB"
17    },
18    {
19        "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
20        "EventCode": "0x85",
21        "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
22        "PerPkg": "1",
23        "UMask": "0x2",
24        "Unit": "ARB"
25    },
26    {
27        "BriefDescription": "Number of coherent read requests sent to memory controller that were issued by any core.",
28        "EventCode": "0x81",
29        "EventName": "UNC_ARB_DAT_REQUESTS.RD",
30        "PerPkg": "1",
31        "UMask": "0x2",
32        "Unit": "ARB"
33    },
34    {
35        "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
36        "EventCode": "0x85",
37        "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
38        "PerPkg": "1",
39        "UMask": "0x1",
40        "Unit": "ARB"
41    },
42    {
43        "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_REQUESTS.RD",
44        "EventCode": "0x81",
45        "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
46        "PerPkg": "1",
47        "UMask": "0x2",
48        "Unit": "ARB"
49    },
50    {
51        "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
52        "EventCode": "0x80",
53        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
54        "PerPkg": "1",
55        "UMask": "0x1",
56        "Unit": "ARB"
57    },
58    {
59        "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
60        "EventCode": "0x81",
61        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
62        "PerPkg": "1",
63        "UMask": "0x1",
64        "Unit": "ARB"
65    },
66    {
67        "BriefDescription": "UNC_CLOCK.SOCKET",
68        "EventCode": "0xff",
69        "EventName": "UNC_CLOCK.SOCKET",
70        "PerPkg": "1",
71        "Unit": "CLOCK"
72    },
73    {
74        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
75        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
76        "PerPkg": "1",
77        "Unit": "imc"
78    },
79    {
80        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
81        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
82        "PerPkg": "1",
83        "Unit": "imc"
84    },
85    {
86        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
87        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
88        "PerPkg": "1",
89        "Unit": "imc"
90    },
91    {
92        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
93        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
94        "PerPkg": "1",
95        "Unit": "imc"
96    },
97    {
98        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
99        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
100        "PerPkg": "1",
101        "Unit": "imc"
102    },
103    {
104        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
105        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
106        "PerPkg": "1",
107        "Unit": "imc"
108    }
109]
110