1b9efd75bSJin Yao[ 2b9efd75bSJin Yao { 3*5e1dd4f2SIan Rogers "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", 4*5e1dd4f2SIan Rogers "MetricExpr": "100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS)", 5*5e1dd4f2SIan Rogers "MetricGroup": "Ret", 6*5e1dd4f2SIan Rogers "MetricName": "Branching_Overhead" 7*5e1dd4f2SIan Rogers }, 8*5e1dd4f2SIan Rogers { 9*5e1dd4f2SIan Rogers "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", 10*5e1dd4f2SIan Rogers "MetricExpr": "100 * (( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD) + (10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS)", 11*5e1dd4f2SIan Rogers "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", 12*5e1dd4f2SIan Rogers "MetricName": "Big_Code" 13*5e1dd4f2SIan Rogers }, 14*5e1dd4f2SIan Rogers { 15b9efd75bSJin Yao "BriefDescription": "Instructions Per Cycle (per Logical Processor)", 16b9efd75bSJin Yao "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", 17*5e1dd4f2SIan Rogers "MetricGroup": "Ret;Summary", 18b9efd75bSJin Yao "MetricName": "IPC" 19b9efd75bSJin Yao }, 20b9efd75bSJin Yao { 21b9efd75bSJin Yao "BriefDescription": "Cycles Per Instruction (per Logical Processor)", 22*5e1dd4f2SIan Rogers "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", 23*5e1dd4f2SIan Rogers "MetricGroup": "Pipeline;Mem", 24b9efd75bSJin Yao "MetricName": "CPI" 25b9efd75bSJin Yao }, 26b9efd75bSJin Yao { 27b9efd75bSJin Yao "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", 28b9efd75bSJin Yao "MetricExpr": "CPU_CLK_UNHALTED.THREAD", 29b9efd75bSJin Yao "MetricGroup": "Pipeline", 30b9efd75bSJin Yao "MetricName": "CLKS" 31b9efd75bSJin Yao }, 32b9efd75bSJin Yao { 33*5e1dd4f2SIan Rogers "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", 34*5e1dd4f2SIan Rogers "MetricExpr": "TOPDOWN.SLOTS", 35*5e1dd4f2SIan Rogers "MetricGroup": "TmaL1", 36*5e1dd4f2SIan Rogers "MetricName": "SLOTS" 37*5e1dd4f2SIan Rogers }, 38*5e1dd4f2SIan Rogers { 39*5e1dd4f2SIan Rogers "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", 40*5e1dd4f2SIan Rogers "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", 41b9efd75bSJin Yao "MetricGroup": "SMT;TmaL1", 42*5e1dd4f2SIan Rogers "MetricName": "Slots_Utilization" 43*5e1dd4f2SIan Rogers }, 44*5e1dd4f2SIan Rogers { 45*5e1dd4f2SIan Rogers "BriefDescription": "The ratio of Executed- by Issued-Uops", 46*5e1dd4f2SIan Rogers "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", 47*5e1dd4f2SIan Rogers "MetricGroup": "Cor;Pipeline", 48*5e1dd4f2SIan Rogers "MetricName": "Execute_per_Issue", 49*5e1dd4f2SIan Rogers "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." 50*5e1dd4f2SIan Rogers }, 51*5e1dd4f2SIan Rogers { 52*5e1dd4f2SIan Rogers "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", 53*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED", 54*5e1dd4f2SIan Rogers "MetricGroup": "Ret;SMT;TmaL1", 55b9efd75bSJin Yao "MetricName": "CoreIPC" 56b9efd75bSJin Yao }, 57b9efd75bSJin Yao { 58b9efd75bSJin Yao "BriefDescription": "Floating Point Operations Per Cycle", 59b9efd75bSJin Yao "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", 60*5e1dd4f2SIan Rogers "MetricGroup": "Ret;Flops", 61b9efd75bSJin Yao "MetricName": "FLOPc" 62b9efd75bSJin Yao }, 63b9efd75bSJin Yao { 64*5e1dd4f2SIan Rogers "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", 65*5e1dd4f2SIan Rogers "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", 66*5e1dd4f2SIan Rogers "MetricGroup": "Cor;Flops;HPC", 67*5e1dd4f2SIan Rogers "MetricName": "FP_Arith_Utilization", 68*5e1dd4f2SIan Rogers "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." 69b9efd75bSJin Yao }, 70b9efd75bSJin Yao { 71*5e1dd4f2SIan Rogers "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", 72*5e1dd4f2SIan Rogers "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", 73*5e1dd4f2SIan Rogers "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", 74*5e1dd4f2SIan Rogers "MetricName": "ILP" 75b9efd75bSJin Yao }, 76b9efd75bSJin Yao { 77b9efd75bSJin Yao "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", 78b9efd75bSJin Yao "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", 79b9efd75bSJin Yao "MetricGroup": "SMT", 80b9efd75bSJin Yao "MetricName": "CORE_CLKS" 81b9efd75bSJin Yao }, 82b9efd75bSJin Yao { 83b9efd75bSJin Yao "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", 84b9efd75bSJin Yao "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", 85b9efd75bSJin Yao "MetricGroup": "InsType", 86b9efd75bSJin Yao "MetricName": "IpLoad" 87b9efd75bSJin Yao }, 88b9efd75bSJin Yao { 89b9efd75bSJin Yao "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", 90b9efd75bSJin Yao "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", 91b9efd75bSJin Yao "MetricGroup": "InsType", 92b9efd75bSJin Yao "MetricName": "IpStore" 93b9efd75bSJin Yao }, 94b9efd75bSJin Yao { 95b9efd75bSJin Yao "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", 96b9efd75bSJin Yao "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", 97*5e1dd4f2SIan Rogers "MetricGroup": "Branches;Fed;InsType", 98b9efd75bSJin Yao "MetricName": "IpBranch" 99b9efd75bSJin Yao }, 100b9efd75bSJin Yao { 101b9efd75bSJin Yao "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", 102b9efd75bSJin Yao "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", 103*5e1dd4f2SIan Rogers "MetricGroup": "Branches;Fed;PGO", 104b9efd75bSJin Yao "MetricName": "IpCall" 105b9efd75bSJin Yao }, 106b9efd75bSJin Yao { 107*5e1dd4f2SIan Rogers "BriefDescription": "Instruction per taken branch", 108*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", 109*5e1dd4f2SIan Rogers "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", 110*5e1dd4f2SIan Rogers "MetricName": "IpTB" 111*5e1dd4f2SIan Rogers }, 112*5e1dd4f2SIan Rogers { 113b9efd75bSJin Yao "BriefDescription": "Branch instructions per taken branch. ", 114b9efd75bSJin Yao "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", 115*5e1dd4f2SIan Rogers "MetricGroup": "Branches;Fed;PGO", 116b9efd75bSJin Yao "MetricName": "BpTkBranch" 117b9efd75bSJin Yao }, 118b9efd75bSJin Yao { 119b9efd75bSJin Yao "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", 120b9efd75bSJin Yao "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", 121*5e1dd4f2SIan Rogers "MetricGroup": "Flops;InsType", 122b9efd75bSJin Yao "MetricName": "IpFLOP" 123b9efd75bSJin Yao }, 124b9efd75bSJin Yao { 125*5e1dd4f2SIan Rogers "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", 126*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) )", 127*5e1dd4f2SIan Rogers "MetricGroup": "Flops;InsType", 128*5e1dd4f2SIan Rogers "MetricName": "IpArith", 129*5e1dd4f2SIan Rogers "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." 130*5e1dd4f2SIan Rogers }, 131*5e1dd4f2SIan Rogers { 132*5e1dd4f2SIan Rogers "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", 133*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 134*5e1dd4f2SIan Rogers "MetricGroup": "Flops;FpScalar;InsType", 135*5e1dd4f2SIan Rogers "MetricName": "IpArith_Scalar_SP", 136*5e1dd4f2SIan Rogers "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 137*5e1dd4f2SIan Rogers }, 138*5e1dd4f2SIan Rogers { 139*5e1dd4f2SIan Rogers "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", 140*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 141*5e1dd4f2SIan Rogers "MetricGroup": "Flops;FpScalar;InsType", 142*5e1dd4f2SIan Rogers "MetricName": "IpArith_Scalar_DP", 143*5e1dd4f2SIan Rogers "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 144*5e1dd4f2SIan Rogers }, 145*5e1dd4f2SIan Rogers { 146*5e1dd4f2SIan Rogers "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", 147*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", 148*5e1dd4f2SIan Rogers "MetricGroup": "Flops;FpVector;InsType", 149*5e1dd4f2SIan Rogers "MetricName": "IpArith_AVX128", 150*5e1dd4f2SIan Rogers "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 151*5e1dd4f2SIan Rogers }, 152*5e1dd4f2SIan Rogers { 153*5e1dd4f2SIan Rogers "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", 154*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", 155*5e1dd4f2SIan Rogers "MetricGroup": "Flops;FpVector;InsType", 156*5e1dd4f2SIan Rogers "MetricName": "IpArith_AVX256", 157*5e1dd4f2SIan Rogers "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 158*5e1dd4f2SIan Rogers }, 159*5e1dd4f2SIan Rogers { 160*5e1dd4f2SIan Rogers "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", 161*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", 162*5e1dd4f2SIan Rogers "MetricGroup": "Flops;FpVector;InsType", 163*5e1dd4f2SIan Rogers "MetricName": "IpArith_AVX512", 164*5e1dd4f2SIan Rogers "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 165*5e1dd4f2SIan Rogers }, 166*5e1dd4f2SIan Rogers { 167*5e1dd4f2SIan Rogers "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", 168*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", 169*5e1dd4f2SIan Rogers "MetricGroup": "Prefetches", 170*5e1dd4f2SIan Rogers "MetricName": "IpSWPF" 171*5e1dd4f2SIan Rogers }, 172*5e1dd4f2SIan Rogers { 173b9efd75bSJin Yao "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", 174b9efd75bSJin Yao "MetricExpr": "INST_RETIRED.ANY", 175b9efd75bSJin Yao "MetricGroup": "Summary;TmaL1", 176b9efd75bSJin Yao "MetricName": "Instructions" 177b9efd75bSJin Yao }, 178b9efd75bSJin Yao { 179*5e1dd4f2SIan Rogers "BriefDescription": "", 180*5e1dd4f2SIan Rogers "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", 181*5e1dd4f2SIan Rogers "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", 182*5e1dd4f2SIan Rogers "MetricName": "Execute" 183*5e1dd4f2SIan Rogers }, 184*5e1dd4f2SIan Rogers { 185*5e1dd4f2SIan Rogers "BriefDescription": "Average number of Uops issued by front-end when it issued something", 186*5e1dd4f2SIan Rogers "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", 187*5e1dd4f2SIan Rogers "MetricGroup": "Fed;FetchBW", 188*5e1dd4f2SIan Rogers "MetricName": "Fetch_UpC" 189*5e1dd4f2SIan Rogers }, 190*5e1dd4f2SIan Rogers { 191b9efd75bSJin Yao "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", 192b9efd75bSJin Yao "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", 193*5e1dd4f2SIan Rogers "MetricGroup": "Fed;LSD", 194b9efd75bSJin Yao "MetricName": "LSD_Coverage" 195b9efd75bSJin Yao }, 196b9efd75bSJin Yao { 197b9efd75bSJin Yao "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", 198b9efd75bSJin Yao "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", 199*5e1dd4f2SIan Rogers "MetricGroup": "DSB;Fed;FetchBW", 200b9efd75bSJin Yao "MetricName": "DSB_Coverage" 201b9efd75bSJin Yao }, 202b9efd75bSJin Yao { 203*5e1dd4f2SIan Rogers "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", 204*5e1dd4f2SIan Rogers "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", 205*5e1dd4f2SIan Rogers "MetricGroup": "DSBmiss", 206*5e1dd4f2SIan Rogers "MetricName": "DSB_Switch_Cost" 207*5e1dd4f2SIan Rogers }, 208*5e1dd4f2SIan Rogers { 209*5e1dd4f2SIan Rogers "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", 210*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", 211*5e1dd4f2SIan Rogers "MetricGroup": "DSBmiss;Fed", 212*5e1dd4f2SIan Rogers "MetricName": "IpDSB_Miss_Ret" 213*5e1dd4f2SIan Rogers }, 214*5e1dd4f2SIan Rogers { 215*5e1dd4f2SIan Rogers "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", 216*5e1dd4f2SIan Rogers "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", 217*5e1dd4f2SIan Rogers "MetricGroup": "Bad;BadSpec;BrMispredicts", 218*5e1dd4f2SIan Rogers "MetricName": "IpMispredict" 219*5e1dd4f2SIan Rogers }, 220*5e1dd4f2SIan Rogers { 221*5e1dd4f2SIan Rogers "BriefDescription": "Fraction of branches that are non-taken conditionals", 222*5e1dd4f2SIan Rogers "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", 223*5e1dd4f2SIan Rogers "MetricGroup": "Bad;Branches;CodeGen;PGO", 224*5e1dd4f2SIan Rogers "MetricName": "Cond_NT" 225*5e1dd4f2SIan Rogers }, 226*5e1dd4f2SIan Rogers { 227*5e1dd4f2SIan Rogers "BriefDescription": "Fraction of branches that are taken conditionals", 228*5e1dd4f2SIan Rogers "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", 229*5e1dd4f2SIan Rogers "MetricGroup": "Bad;Branches;CodeGen;PGO", 230*5e1dd4f2SIan Rogers "MetricName": "Cond_TK" 231*5e1dd4f2SIan Rogers }, 232*5e1dd4f2SIan Rogers { 233*5e1dd4f2SIan Rogers "BriefDescription": "Fraction of branches that are CALL or RET", 234*5e1dd4f2SIan Rogers "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", 235*5e1dd4f2SIan Rogers "MetricGroup": "Bad;Branches", 236*5e1dd4f2SIan Rogers "MetricName": "CallRet" 237*5e1dd4f2SIan Rogers }, 238*5e1dd4f2SIan Rogers { 239*5e1dd4f2SIan Rogers "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", 240*5e1dd4f2SIan Rogers "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", 241*5e1dd4f2SIan Rogers "MetricGroup": "Bad;Branches", 242*5e1dd4f2SIan Rogers "MetricName": "Jump" 243*5e1dd4f2SIan Rogers }, 244*5e1dd4f2SIan Rogers { 245*5e1dd4f2SIan Rogers "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", 246*5e1dd4f2SIan Rogers "MetricExpr": "1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) )", 247*5e1dd4f2SIan Rogers "MetricGroup": "Bad;Branches", 248*5e1dd4f2SIan Rogers "MetricName": "Other_Branches" 249*5e1dd4f2SIan Rogers }, 250*5e1dd4f2SIan Rogers { 251*5e1dd4f2SIan Rogers "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", 252b9efd75bSJin Yao "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", 253*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBound;MemoryLat", 254b9efd75bSJin Yao "MetricName": "Load_Miss_Real_Latency" 255b9efd75bSJin Yao }, 256b9efd75bSJin Yao { 257b9efd75bSJin Yao "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", 258b9efd75bSJin Yao "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", 259*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBound;MemoryBW", 260b9efd75bSJin Yao "MetricName": "MLP" 261b9efd75bSJin Yao }, 262b9efd75bSJin Yao { 263b9efd75bSJin Yao "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", 264b9efd75bSJin Yao "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", 265*5e1dd4f2SIan Rogers "MetricGroup": "Mem;CacheMisses", 266b9efd75bSJin Yao "MetricName": "L1MPKI" 267b9efd75bSJin Yao }, 268b9efd75bSJin Yao { 269*5e1dd4f2SIan Rogers "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", 270*5e1dd4f2SIan Rogers "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", 271*5e1dd4f2SIan Rogers "MetricGroup": "Mem;CacheMisses", 272*5e1dd4f2SIan Rogers "MetricName": "L1MPKI_Load" 273*5e1dd4f2SIan Rogers }, 274*5e1dd4f2SIan Rogers { 275b9efd75bSJin Yao "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", 276b9efd75bSJin Yao "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", 277*5e1dd4f2SIan Rogers "MetricGroup": "Mem;Backend;CacheMisses", 278b9efd75bSJin Yao "MetricName": "L2MPKI" 279b9efd75bSJin Yao }, 280b9efd75bSJin Yao { 281*5e1dd4f2SIan Rogers "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", 282*5e1dd4f2SIan Rogers "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", 283*5e1dd4f2SIan Rogers "MetricGroup": "Mem;CacheMisses;Offcore", 284*5e1dd4f2SIan Rogers "MetricName": "L2MPKI_All" 285*5e1dd4f2SIan Rogers }, 286*5e1dd4f2SIan Rogers { 287*5e1dd4f2SIan Rogers "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", 288*5e1dd4f2SIan Rogers "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", 289*5e1dd4f2SIan Rogers "MetricGroup": "Mem;CacheMisses", 290*5e1dd4f2SIan Rogers "MetricName": "L2MPKI_Load" 291*5e1dd4f2SIan Rogers }, 292*5e1dd4f2SIan Rogers { 293*5e1dd4f2SIan Rogers "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", 294*5e1dd4f2SIan Rogers "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", 295*5e1dd4f2SIan Rogers "MetricGroup": "Mem;CacheMisses", 296*5e1dd4f2SIan Rogers "MetricName": "L2HPKI_All" 297*5e1dd4f2SIan Rogers }, 298*5e1dd4f2SIan Rogers { 299*5e1dd4f2SIan Rogers "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", 300*5e1dd4f2SIan Rogers "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", 301*5e1dd4f2SIan Rogers "MetricGroup": "Mem;CacheMisses", 302*5e1dd4f2SIan Rogers "MetricName": "L2HPKI_Load" 303*5e1dd4f2SIan Rogers }, 304*5e1dd4f2SIan Rogers { 305b9efd75bSJin Yao "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", 306b9efd75bSJin Yao "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", 307*5e1dd4f2SIan Rogers "MetricGroup": "Mem;CacheMisses", 308b9efd75bSJin Yao "MetricName": "L3MPKI" 309b9efd75bSJin Yao }, 310b9efd75bSJin Yao { 311*5e1dd4f2SIan Rogers "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", 312*5e1dd4f2SIan Rogers "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", 313*5e1dd4f2SIan Rogers "MetricGroup": "Mem;CacheMisses", 314*5e1dd4f2SIan Rogers "MetricName": "FB_HPKI" 315*5e1dd4f2SIan Rogers }, 316*5e1dd4f2SIan Rogers { 317*5e1dd4f2SIan Rogers "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", 318*5e1dd4f2SIan Rogers "MetricConstraint": "NO_NMI_WATCHDOG", 319*5e1dd4f2SIan Rogers "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", 320*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryTLB", 321*5e1dd4f2SIan Rogers "MetricName": "Page_Walks_Utilization" 322*5e1dd4f2SIan Rogers }, 323*5e1dd4f2SIan Rogers { 324*5e1dd4f2SIan Rogers "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", 325*5e1dd4f2SIan Rogers "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", 326*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBW", 327*5e1dd4f2SIan Rogers "MetricName": "L1D_Cache_Fill_BW" 328*5e1dd4f2SIan Rogers }, 329*5e1dd4f2SIan Rogers { 330*5e1dd4f2SIan Rogers "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", 331*5e1dd4f2SIan Rogers "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", 332*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBW", 333*5e1dd4f2SIan Rogers "MetricName": "L2_Cache_Fill_BW" 334*5e1dd4f2SIan Rogers }, 335*5e1dd4f2SIan Rogers { 336*5e1dd4f2SIan Rogers "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", 337*5e1dd4f2SIan Rogers "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", 338*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBW", 339*5e1dd4f2SIan Rogers "MetricName": "L3_Cache_Fill_BW" 340*5e1dd4f2SIan Rogers }, 341*5e1dd4f2SIan Rogers { 342*5e1dd4f2SIan Rogers "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", 343*5e1dd4f2SIan Rogers "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", 344*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBW;Offcore", 345*5e1dd4f2SIan Rogers "MetricName": "L3_Cache_Access_BW" 346*5e1dd4f2SIan Rogers }, 347*5e1dd4f2SIan Rogers { 348*5e1dd4f2SIan Rogers "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", 349*5e1dd4f2SIan Rogers "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)", 350*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBW", 351*5e1dd4f2SIan Rogers "MetricName": "L1D_Cache_Fill_BW_1T" 352*5e1dd4f2SIan Rogers }, 353*5e1dd4f2SIan Rogers { 354*5e1dd4f2SIan Rogers "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", 355*5e1dd4f2SIan Rogers "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)", 356*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBW", 357*5e1dd4f2SIan Rogers "MetricName": "L2_Cache_Fill_BW_1T" 358*5e1dd4f2SIan Rogers }, 359*5e1dd4f2SIan Rogers { 360*5e1dd4f2SIan Rogers "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", 361*5e1dd4f2SIan Rogers "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time)", 362*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBW", 363*5e1dd4f2SIan Rogers "MetricName": "L3_Cache_Fill_BW_1T" 364*5e1dd4f2SIan Rogers }, 365*5e1dd4f2SIan Rogers { 366*5e1dd4f2SIan Rogers "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", 367*5e1dd4f2SIan Rogers "MetricExpr": "(64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time)", 368*5e1dd4f2SIan Rogers "MetricGroup": "Mem;MemoryBW;Offcore", 369*5e1dd4f2SIan Rogers "MetricName": "L3_Cache_Access_BW_1T" 370*5e1dd4f2SIan Rogers }, 371*5e1dd4f2SIan Rogers { 372b9efd75bSJin Yao "BriefDescription": "Average CPU Utilization", 373b9efd75bSJin Yao "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", 374b9efd75bSJin Yao "MetricGroup": "HPC;Summary", 375b9efd75bSJin Yao "MetricName": "CPU_Utilization" 376b9efd75bSJin Yao }, 377b9efd75bSJin Yao { 378b9efd75bSJin Yao "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", 379b9efd75bSJin Yao "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", 380b9efd75bSJin Yao "MetricGroup": "Summary;Power", 381b9efd75bSJin Yao "MetricName": "Average_Frequency" 382b9efd75bSJin Yao }, 383b9efd75bSJin Yao { 384b9efd75bSJin Yao "BriefDescription": "Giga Floating Point Operations Per Second", 385b9efd75bSJin Yao "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time", 386*5e1dd4f2SIan Rogers "MetricGroup": "Cor;Flops;HPC", 387*5e1dd4f2SIan Rogers "MetricName": "GFLOPs", 388*5e1dd4f2SIan Rogers "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." 389b9efd75bSJin Yao }, 390b9efd75bSJin Yao { 391b9efd75bSJin Yao "BriefDescription": "Average Frequency Utilization relative nominal frequency", 392b9efd75bSJin Yao "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", 393b9efd75bSJin Yao "MetricGroup": "Power", 394b9efd75bSJin Yao "MetricName": "Turbo_Utilization" 395b9efd75bSJin Yao }, 396b9efd75bSJin Yao { 397*5e1dd4f2SIan Rogers "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", 398*5e1dd4f2SIan Rogers "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", 399*5e1dd4f2SIan Rogers "MetricGroup": "Power", 400*5e1dd4f2SIan Rogers "MetricName": "Power_License0_Utilization", 401*5e1dd4f2SIan Rogers "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." 402*5e1dd4f2SIan Rogers }, 403*5e1dd4f2SIan Rogers { 404*5e1dd4f2SIan Rogers "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", 405*5e1dd4f2SIan Rogers "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", 406*5e1dd4f2SIan Rogers "MetricGroup": "Power", 407*5e1dd4f2SIan Rogers "MetricName": "Power_License1_Utilization", 408*5e1dd4f2SIan Rogers "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." 409*5e1dd4f2SIan Rogers }, 410*5e1dd4f2SIan Rogers { 411*5e1dd4f2SIan Rogers "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", 412*5e1dd4f2SIan Rogers "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", 413*5e1dd4f2SIan Rogers "MetricGroup": "Power", 414*5e1dd4f2SIan Rogers "MetricName": "Power_License2_Utilization", 415*5e1dd4f2SIan Rogers "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." 416*5e1dd4f2SIan Rogers }, 417*5e1dd4f2SIan Rogers { 418b9efd75bSJin Yao "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", 419*5e1dd4f2SIan Rogers "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0", 420b9efd75bSJin Yao "MetricGroup": "SMT", 421b9efd75bSJin Yao "MetricName": "SMT_2T_Utilization" 422b9efd75bSJin Yao }, 423b9efd75bSJin Yao { 424b9efd75bSJin Yao "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", 425b9efd75bSJin Yao "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", 426b9efd75bSJin Yao "MetricGroup": "OS", 427b9efd75bSJin Yao "MetricName": "Kernel_Utilization" 428b9efd75bSJin Yao }, 429b9efd75bSJin Yao { 430*5e1dd4f2SIan Rogers "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", 431*5e1dd4f2SIan Rogers "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", 432*5e1dd4f2SIan Rogers "MetricGroup": "OS", 433*5e1dd4f2SIan Rogers "MetricName": "Kernel_CPI" 434*5e1dd4f2SIan Rogers }, 435*5e1dd4f2SIan Rogers { 436*5e1dd4f2SIan Rogers "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", 437*5e1dd4f2SIan Rogers "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", 438*5e1dd4f2SIan Rogers "MetricGroup": "HPC;Mem;MemoryBW;SoC", 439*5e1dd4f2SIan Rogers "MetricName": "DRAM_BW_Use" 440*5e1dd4f2SIan Rogers }, 441*5e1dd4f2SIan Rogers { 442*5e1dd4f2SIan Rogers "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", 443*5e1dd4f2SIan Rogers "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", 444*5e1dd4f2SIan Rogers "MetricGroup": "Mem;SoC", 445*5e1dd4f2SIan Rogers "MetricName": "MEM_Parallel_Requests" 446*5e1dd4f2SIan Rogers }, 447*5e1dd4f2SIan Rogers { 448b9efd75bSJin Yao "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", 449b9efd75bSJin Yao "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", 450b9efd75bSJin Yao "MetricGroup": "Branches;OS", 451b9efd75bSJin Yao "MetricName": "IpFarBranch" 452b9efd75bSJin Yao }, 453b9efd75bSJin Yao { 454b9efd75bSJin Yao "BriefDescription": "C6 residency percent per core", 455b9efd75bSJin Yao "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", 456b9efd75bSJin Yao "MetricGroup": "Power", 457b9efd75bSJin Yao "MetricName": "C6_Core_Residency" 458b9efd75bSJin Yao }, 459b9efd75bSJin Yao { 460b9efd75bSJin Yao "BriefDescription": "C7 residency percent per core", 461b9efd75bSJin Yao "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", 462b9efd75bSJin Yao "MetricGroup": "Power", 463b9efd75bSJin Yao "MetricName": "C7_Core_Residency" 464b9efd75bSJin Yao }, 465b9efd75bSJin Yao { 466*5e1dd4f2SIan Rogers "BriefDescription": "C2 residency percent per package", 467*5e1dd4f2SIan Rogers "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", 468*5e1dd4f2SIan Rogers "MetricGroup": "Power", 469*5e1dd4f2SIan Rogers "MetricName": "C2_Pkg_Residency" 470*5e1dd4f2SIan Rogers }, 471*5e1dd4f2SIan Rogers { 472*5e1dd4f2SIan Rogers "BriefDescription": "C3 residency percent per package", 473*5e1dd4f2SIan Rogers "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", 474*5e1dd4f2SIan Rogers "MetricGroup": "Power", 475*5e1dd4f2SIan Rogers "MetricName": "C3_Pkg_Residency" 476*5e1dd4f2SIan Rogers }, 477*5e1dd4f2SIan Rogers { 478b9efd75bSJin Yao "BriefDescription": "C6 residency percent per package", 479b9efd75bSJin Yao "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", 480b9efd75bSJin Yao "MetricGroup": "Power", 481b9efd75bSJin Yao "MetricName": "C6_Pkg_Residency" 482b9efd75bSJin Yao }, 483b9efd75bSJin Yao { 484b9efd75bSJin Yao "BriefDescription": "C7 residency percent per package", 485b9efd75bSJin Yao "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", 486b9efd75bSJin Yao "MetricGroup": "Power", 487b9efd75bSJin Yao "MetricName": "C7_Pkg_Residency" 488*5e1dd4f2SIan Rogers }, 489*5e1dd4f2SIan Rogers { 490*5e1dd4f2SIan Rogers "BriefDescription": "C8 residency percent per package", 491*5e1dd4f2SIan Rogers "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100", 492*5e1dd4f2SIan Rogers "MetricGroup": "Power", 493*5e1dd4f2SIan Rogers "MetricName": "C8_Pkg_Residency" 494*5e1dd4f2SIan Rogers }, 495*5e1dd4f2SIan Rogers { 496*5e1dd4f2SIan Rogers "BriefDescription": "C9 residency percent per package", 497*5e1dd4f2SIan Rogers "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100", 498*5e1dd4f2SIan Rogers "MetricGroup": "Power", 499*5e1dd4f2SIan Rogers "MetricName": "C9_Pkg_Residency" 500*5e1dd4f2SIan Rogers }, 501*5e1dd4f2SIan Rogers { 502*5e1dd4f2SIan Rogers "BriefDescription": "C10 residency percent per package", 503*5e1dd4f2SIan Rogers "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100", 504*5e1dd4f2SIan Rogers "MetricGroup": "Power", 505*5e1dd4f2SIan Rogers "MetricName": "C10_Pkg_Residency" 506b9efd75bSJin Yao } 507b9efd75bSJin Yao] 508