1[
2    {
3        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
4        "EventCode": "0x28",
5        "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
6        "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
7        "SampleAfterValue": "200003",
8        "UMask": "0x7"
9    },
10    {
11        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
12        "EventCode": "0x28",
13        "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
14        "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
15        "SampleAfterValue": "200003",
16        "UMask": "0x18"
17    },
18    {
19        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
20        "EventCode": "0x28",
21        "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
22        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructions.",
23        "SampleAfterValue": "200003",
24        "UMask": "0x20"
25    },
26    {
27        "BriefDescription": "Counts streaming stores that have any type of response.",
28        "EventCode": "0xB7, 0xBB",
29        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
30        "MSRIndex": "0x1a6,0x1a7",
31        "MSRValue": "0x10800",
32        "SampleAfterValue": "100003",
33        "UMask": "0x1"
34    }
35]
36