1[
2    {
3        "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5,6,7",
6        "EventCode": "0xc1",
7        "EventName": "ASSISTS.ANY",
8        "PEBScounters": "0,1,2,3,4,5,6,7",
9        "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
10        "SampleAfterValue": "100003",
11        "UMask": "0x7"
12    },
13    {
14        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3",
17        "EventCode": "0x28",
18        "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
19        "PEBScounters": "0,1,2,3",
20        "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
21        "SampleAfterValue": "200003",
22        "UMask": "0x7"
23    },
24    {
25        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
26        "CollectPEBSRecord": "2",
27        "Counter": "0,1,2,3",
28        "EventCode": "0x28",
29        "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
30        "PEBScounters": "0,1,2,3",
31        "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
32        "SampleAfterValue": "200003",
33        "UMask": "0x18"
34    },
35    {
36        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
37        "CollectPEBSRecord": "2",
38        "Counter": "0,1,2,3",
39        "EventCode": "0x28",
40        "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
41        "PEBScounters": "0,1,2,3",
42        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructions.",
43        "SampleAfterValue": "200003",
44        "UMask": "0x20"
45    },
46    {
47        "BriefDescription": "Counts streaming stores that have any type of response.",
48        "CollectPEBSRecord": "2",
49        "Counter": "0,1,2,3",
50        "EventCode": "0xB7, 0xBB",
51        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
52        "MSRIndex": "0x1a6,0x1a7",
53        "MSRValue": "0x10800",
54        "Offcore": "1",
55        "PEBScounters": "0,1,2,3",
56        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
57        "SampleAfterValue": "100003",
58        "UMask": "0x1"
59    }
60]