1*4babba55SJin Yao[ 2*4babba55SJin Yao { 3*4babba55SJin Yao "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 4*4babba55SJin Yao "CounterMask": "6", 5*4babba55SJin Yao "EventCode": "0xa3", 6*4babba55SJin Yao "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 7*4babba55SJin Yao "SampleAfterValue": "1000003", 8*4babba55SJin Yao "UMask": "0x6" 9*4babba55SJin Yao }, 10*4babba55SJin Yao { 11*4babba55SJin Yao "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 12*4babba55SJin Yao "EventCode": "0xc3", 13*4babba55SJin Yao "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 14*4babba55SJin Yao "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", 15*4babba55SJin Yao "SampleAfterValue": "100003", 16*4babba55SJin Yao "UMask": "0x2" 17*4babba55SJin Yao }, 18*4babba55SJin Yao { 19*4babba55SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 20*4babba55SJin Yao "Data_LA": "1", 21*4babba55SJin Yao "EventCode": "0xcd", 22*4babba55SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 23*4babba55SJin Yao "MSRIndex": "0x3F6", 24*4babba55SJin Yao "MSRValue": "0x80", 25*4babba55SJin Yao "PEBS": "2", 26*4babba55SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 27*4babba55SJin Yao "SampleAfterValue": "1009", 28*4babba55SJin Yao "UMask": "0x1" 29*4babba55SJin Yao }, 30*4babba55SJin Yao { 31*4babba55SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 32*4babba55SJin Yao "Data_LA": "1", 33*4babba55SJin Yao "EventCode": "0xcd", 34*4babba55SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 35*4babba55SJin Yao "MSRIndex": "0x3F6", 36*4babba55SJin Yao "MSRValue": "0x10", 37*4babba55SJin Yao "PEBS": "2", 38*4babba55SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 39*4babba55SJin Yao "SampleAfterValue": "20011", 40*4babba55SJin Yao "UMask": "0x1" 41*4babba55SJin Yao }, 42*4babba55SJin Yao { 43*4babba55SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 44*4babba55SJin Yao "Data_LA": "1", 45*4babba55SJin Yao "EventCode": "0xcd", 46*4babba55SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 47*4babba55SJin Yao "MSRIndex": "0x3F6", 48*4babba55SJin Yao "MSRValue": "0x100", 49*4babba55SJin Yao "PEBS": "2", 50*4babba55SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 51*4babba55SJin Yao "SampleAfterValue": "503", 52*4babba55SJin Yao "UMask": "0x1" 53*4babba55SJin Yao }, 54*4babba55SJin Yao { 55*4babba55SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 56*4babba55SJin Yao "Data_LA": "1", 57*4babba55SJin Yao "EventCode": "0xcd", 58*4babba55SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 59*4babba55SJin Yao "MSRIndex": "0x3F6", 60*4babba55SJin Yao "MSRValue": "0x20", 61*4babba55SJin Yao "PEBS": "2", 62*4babba55SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 63*4babba55SJin Yao "SampleAfterValue": "100007", 64*4babba55SJin Yao "UMask": "0x1" 65*4babba55SJin Yao }, 66*4babba55SJin Yao { 67*4babba55SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 68*4babba55SJin Yao "Data_LA": "1", 69*4babba55SJin Yao "EventCode": "0xcd", 70*4babba55SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 71*4babba55SJin Yao "MSRIndex": "0x3F6", 72*4babba55SJin Yao "MSRValue": "0x4", 73*4babba55SJin Yao "PEBS": "2", 74*4babba55SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 75*4babba55SJin Yao "SampleAfterValue": "100003", 76*4babba55SJin Yao "UMask": "0x1" 77*4babba55SJin Yao }, 78*4babba55SJin Yao { 79*4babba55SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 80*4babba55SJin Yao "Data_LA": "1", 81*4babba55SJin Yao "EventCode": "0xcd", 82*4babba55SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 83*4babba55SJin Yao "MSRIndex": "0x3F6", 84*4babba55SJin Yao "MSRValue": "0x200", 85*4babba55SJin Yao "PEBS": "2", 86*4babba55SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 87*4babba55SJin Yao "SampleAfterValue": "101", 88*4babba55SJin Yao "UMask": "0x1" 89*4babba55SJin Yao }, 90*4babba55SJin Yao { 91*4babba55SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 92*4babba55SJin Yao "Data_LA": "1", 93*4babba55SJin Yao "EventCode": "0xcd", 94*4babba55SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 95*4babba55SJin Yao "MSRIndex": "0x3F6", 96*4babba55SJin Yao "MSRValue": "0x40", 97*4babba55SJin Yao "PEBS": "2", 98*4babba55SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 99*4babba55SJin Yao "SampleAfterValue": "2003", 100*4babba55SJin Yao "UMask": "0x1" 101*4babba55SJin Yao }, 102*4babba55SJin Yao { 103*4babba55SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 104*4babba55SJin Yao "Data_LA": "1", 105*4babba55SJin Yao "EventCode": "0xcd", 106*4babba55SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 107*4babba55SJin Yao "MSRIndex": "0x3F6", 108*4babba55SJin Yao "MSRValue": "0x8", 109*4babba55SJin Yao "PEBS": "2", 110*4babba55SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 111*4babba55SJin Yao "SampleAfterValue": "50021", 112*4babba55SJin Yao "UMask": "0x1" 113*4babba55SJin Yao }, 114*4babba55SJin Yao { 115*4babba55SJin Yao "BriefDescription": "Demand Data Read requests who miss L3 cache", 116*4babba55SJin Yao "EventCode": "0xb0", 117*4babba55SJin Yao "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 118*4babba55SJin Yao "PublicDescription": "Demand Data Read requests who miss L3 cache.", 119*4babba55SJin Yao "SampleAfterValue": "100003", 120*4babba55SJin Yao "UMask": "0x10" 121*4babba55SJin Yao }, 122*4babba55SJin Yao { 123*4babba55SJin Yao "BriefDescription": "Number of times an RTM execution aborted.", 124*4babba55SJin Yao "EventCode": "0xc9", 125*4babba55SJin Yao "EventName": "RTM_RETIRED.ABORTED", 126*4babba55SJin Yao "PublicDescription": "Counts the number of times RTM abort was triggered.", 127*4babba55SJin Yao "SampleAfterValue": "100003", 128*4babba55SJin Yao "UMask": "0x4" 129*4babba55SJin Yao }, 130*4babba55SJin Yao { 131*4babba55SJin Yao "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 132*4babba55SJin Yao "EventCode": "0xc9", 133*4babba55SJin Yao "EventName": "RTM_RETIRED.ABORTED_EVENTS", 134*4babba55SJin Yao "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 135*4babba55SJin Yao "SampleAfterValue": "100003", 136*4babba55SJin Yao "UMask": "0x80" 137*4babba55SJin Yao }, 138*4babba55SJin Yao { 139*4babba55SJin Yao "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 140*4babba55SJin Yao "EventCode": "0xc9", 141*4babba55SJin Yao "EventName": "RTM_RETIRED.ABORTED_MEM", 142*4babba55SJin Yao "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 143*4babba55SJin Yao "SampleAfterValue": "100003", 144*4babba55SJin Yao "UMask": "0x8" 145*4babba55SJin Yao }, 146*4babba55SJin Yao { 147*4babba55SJin Yao "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 148*4babba55SJin Yao "EventCode": "0xc9", 149*4babba55SJin Yao "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 150*4babba55SJin Yao "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", 151*4babba55SJin Yao "SampleAfterValue": "100003", 152*4babba55SJin Yao "UMask": "0x40" 153*4babba55SJin Yao }, 154*4babba55SJin Yao { 155*4babba55SJin Yao "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 156*4babba55SJin Yao "EventCode": "0xc9", 157*4babba55SJin Yao "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 158*4babba55SJin Yao "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", 159*4babba55SJin Yao "SampleAfterValue": "100003", 160*4babba55SJin Yao "UMask": "0x20" 161*4babba55SJin Yao }, 162*4babba55SJin Yao { 163*4babba55SJin Yao "BriefDescription": "Number of times an RTM execution successfully committed", 164*4babba55SJin Yao "EventCode": "0xc9", 165*4babba55SJin Yao "EventName": "RTM_RETIRED.COMMIT", 166*4babba55SJin Yao "PublicDescription": "Counts the number of times RTM commit succeeded.", 167*4babba55SJin Yao "SampleAfterValue": "100003", 168*4babba55SJin Yao "UMask": "0x2" 169*4babba55SJin Yao }, 170*4babba55SJin Yao { 171*4babba55SJin Yao "BriefDescription": "Number of times an RTM execution started.", 172*4babba55SJin Yao "EventCode": "0xc9", 173*4babba55SJin Yao "EventName": "RTM_RETIRED.START", 174*4babba55SJin Yao "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", 175*4babba55SJin Yao "SampleAfterValue": "100003", 176*4babba55SJin Yao "UMask": "0x1" 177*4babba55SJin Yao }, 178*4babba55SJin Yao { 179*4babba55SJin Yao "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", 180*4babba55SJin Yao "EventCode": "0x5d", 181*4babba55SJin Yao "EventName": "TX_EXEC.MISC2", 182*4babba55SJin Yao "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", 183*4babba55SJin Yao "SampleAfterValue": "100003", 184*4babba55SJin Yao "UMask": "0x2" 185*4babba55SJin Yao }, 186*4babba55SJin Yao { 187*4babba55SJin Yao "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", 188*4babba55SJin Yao "EventCode": "0x5d", 189*4babba55SJin Yao "EventName": "TX_EXEC.MISC3", 190*4babba55SJin Yao "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", 191*4babba55SJin Yao "SampleAfterValue": "100003", 192*4babba55SJin Yao "UMask": "0x4" 193*4babba55SJin Yao }, 194*4babba55SJin Yao { 195*4babba55SJin Yao "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", 196*4babba55SJin Yao "EventCode": "0x54", 197*4babba55SJin Yao "EventName": "TX_MEM.ABORT_CAPACITY_READ", 198*4babba55SJin Yao "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", 199*4babba55SJin Yao "SampleAfterValue": "100003", 200*4babba55SJin Yao "UMask": "0x80" 201*4babba55SJin Yao }, 202*4babba55SJin Yao { 203*4babba55SJin Yao "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", 204*4babba55SJin Yao "EventCode": "0x54", 205*4babba55SJin Yao "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 206*4babba55SJin Yao "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", 207*4babba55SJin Yao "SampleAfterValue": "100003", 208*4babba55SJin Yao "UMask": "0x2" 209*4babba55SJin Yao }, 210*4babba55SJin Yao { 211*4babba55SJin Yao "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 212*4babba55SJin Yao "EventCode": "0x54", 213*4babba55SJin Yao "EventName": "TX_MEM.ABORT_CONFLICT", 214*4babba55SJin Yao "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 215*4babba55SJin Yao "SampleAfterValue": "100003", 216*4babba55SJin Yao "UMask": "0x1" 217*4babba55SJin Yao } 218*4babba55SJin Yao] 219