1[
2    {
3        "BriefDescription": "Counts all microcode FP assists.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5,6,7",
6        "EventCode": "0xc1",
7        "EventName": "ASSISTS.FP",
8        "PEBScounters": "0,1,2,3,4,5,6,7",
9        "PublicDescription": "Counts all microcode Floating Point assists.",
10        "SampleAfterValue": "100003",
11        "UMask": "0x2"
12    },
13    {
14        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3,4,5,6,7",
17        "EventCode": "0xc7",
18        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
19        "PEBScounters": "0,1,2,3,4,5,6,7",
20        "SampleAfterValue": "100003",
21        "UMask": "0x4"
22    },
23    {
24        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
25        "CollectPEBSRecord": "2",
26        "Counter": "0,1,2,3,4,5,6,7",
27        "EventCode": "0xc7",
28        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
29        "PEBScounters": "0,1,2,3,4,5,6,7",
30        "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
31        "SampleAfterValue": "100003",
32        "UMask": "0x8"
33    },
34    {
35        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
36        "CollectPEBSRecord": "2",
37        "Counter": "0,1,2,3,4,5,6,7",
38        "EventCode": "0xc7",
39        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
40        "PEBScounters": "0,1,2,3,4,5,6,7",
41        "SampleAfterValue": "100003",
42        "UMask": "0x10"
43    },
44    {
45        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
46        "CollectPEBSRecord": "2",
47        "Counter": "0,1,2,3,4,5,6,7",
48        "EventCode": "0xc7",
49        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
50        "PEBScounters": "0,1,2,3,4,5,6,7",
51        "SampleAfterValue": "100003",
52        "UMask": "0x20"
53    },
54    {
55        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
56        "CollectPEBSRecord": "2",
57        "Counter": "0,1,2,3,4,5,6,7",
58        "EventCode": "0xc7",
59        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
60        "PEBScounters": "0,1,2,3,4,5,6,7",
61        "SampleAfterValue": "100003",
62        "UMask": "0x40"
63    },
64    {
65        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
66        "CollectPEBSRecord": "2",
67        "Counter": "0,1,2,3,4,5,6,7",
68        "EventCode": "0xc7",
69        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
70        "PEBScounters": "0,1,2,3,4,5,6,7",
71        "SampleAfterValue": "100003",
72        "UMask": "0x80"
73    },
74    {
75        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
76        "CollectPEBSRecord": "2",
77        "Counter": "0,1,2,3,4,5,6,7",
78        "EventCode": "0xc7",
79        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
80        "PEBScounters": "0,1,2,3,4,5,6,7",
81        "SampleAfterValue": "100003",
82        "UMask": "0x1"
83    },
84    {
85        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
86        "CollectPEBSRecord": "2",
87        "Counter": "0,1,2,3,4,5,6,7",
88        "EventCode": "0xc7",
89        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
90        "PEBScounters": "0,1,2,3,4,5,6,7",
91        "SampleAfterValue": "100003",
92        "UMask": "0x2"
93    }
94]