xref: /openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json (revision b43a5442)

[
    {
        "BriefDescription": "Pre-charge for reads",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.RD",
        "PerPkg": "1",
        "UMask": "0x04",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Pre-charge for writes",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.WR",
        "PerPkg": "1",
        "UMask": "0x08",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "LLC_MISSES.MEM_READ",
        "PerPkg": "1",
        "ScaleUnit": "64Bytes",
        "UMask": "0x0f",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "read requests to memory controller",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD",
        "PerPkg": "1",
        "ScaleUnit": "64Bytes",
        "UMask": "0x0f",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "LLC_MISSES.MEM_WRITE",
        "PerPkg": "1",
        "ScaleUnit": "64Bytes",
        "UMask": "0x30",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "write requests to memory controller",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.WR",
        "PerPkg": "1",
        "ScaleUnit": "64Bytes",
        "UMask": "0x30",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "All DRAM CAS commands issued",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.ALL",
        "PerPkg": "1",
        "UMask": "0x3f",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Number of DRAM Refreshes Issued",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x45",
        "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Number of DRAM Refreshes Issued",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x45",
        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Number of DRAM Refreshes Issued",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x45",
        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
        "PerPkg": "1",
        "UMask": "0x04",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x20",
        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x20",
        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.PGT",
        "PerPkg": "1",
        "UMask": "0x10",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Memory controller clock ticks",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventName": "UNC_M_CLOCKTICKS",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Half clockticks for IMC",
        "Counter": "FIXED",
        "CounterType": "FIXED",
        "EventCode": "0xff",
        "EventName": "UNC_M_HCLOCKTICKS",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Occupancy",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x80",
        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Occupancy",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x81",
        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Occupancy",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x82",
        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Occupancy",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x83",
        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Activate Count : All Activates",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x01",
        "EventName": "UNC_M_ACT_COUNT.ALL",
        "PerPkg": "1",
        "UMask": "0x0B",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Precharge commands",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.ALL",
        "PerPkg": "1",
        "UMask": "0x1C",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Data Buffer Inserts",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x17",
        "EventName": "UNC_M_RDB_INSERTS",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD_REG",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM underfill read CAS commands issued",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
        "PerPkg": "1",
        "UMask": "0x04",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x01",
        "EventName": "UNC_M_ACT_COUNT.BYP",
        "PerPkg": "1",
        "UMask": "0x08",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
        "PerPkg": "1",
        "UMask": "0x08",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.WR_PRE",
        "PerPkg": "1",
        "UMask": "0x20",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
        "PerPkg": "1",
        "UMask": "0x04",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
        "PerPkg": "1",
        "UMask": "0x08",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Throttle Cycles for Rank 0",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x86",
        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Throttle Cycles for Rank 0",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x86",
        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Throttle Cycles for Rank 0",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x46",
        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Throttle Cycles for Rank 0",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x46",
        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Not Empty",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x11",
        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Not Empty",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x11",
        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Not Empty",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x21",
        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Not Empty",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x21",
        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue CAM Match",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x23",
        "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue CAM Match",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x23",
        "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue CAM Match",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x24",
        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue CAM Match",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x24",
        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "UNC_M_PCLS.RD",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0xA0",
        "EventName": "UNC_M_PCLS.RD",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "UNC_M_PCLS.WR",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0xA0",
        "EventName": "UNC_M_PCLS.WR",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "UNC_M_PCLS.TOTAL",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0xA0",
        "EventName": "UNC_M_PCLS.TOTAL",
        "PerPkg": "1",
        "UMask": "0x04",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Precharge All Commands",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x44",
        "EventName": "UNC_M_DRAM_PRE_ALL",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "UNC_M_PARITY_ERRORS",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x2c",
        "EventName": "UNC_M_PARITY_ERRORS",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x85",
        "EventName": "UNC_M_POWER_CHANNEL_PPD",
        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
        "MetricName": "power_channel_ppd %",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Cycles Memory is in self refresh power mode",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x43",
        "EventName": "UNC_M_POWER_SELF_REFRESH",
        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
        "MetricName": "power_self_refresh %",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Data Buffer Full",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x19",
        "EventName": "UNC_M_RDB_FULL",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Data Buffer Not Empty",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x18",
        "EventName": "UNC_M_RDB_NOT_EMPTY",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Data Buffer Occupancy",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x1A",
        "EventName": "UNC_M_RDB_OCCUPANCY",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Full Cycles",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x12",
        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Full Cycles",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x15",
        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Full Cycles",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x22",
        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Full Cycles",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x16",
        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
        "PerPkg": "1",
        "UMask": "0x10",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Pre-charges due to page misses",
        "Counter": "0,1,2,3",
        "CounterType": "PGMABLE",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
        "PerPkg": "1",
        "UMask": "0x0c",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Free running counter that increments for the Memory Controller",
        "Counter": "4",
        "CounterType": "FREERUN",
        "EventName": "UNC_M_CLOCKTICKS_FREERUN",
        "PerPkg": "1",
        "Unit": "iMC"
    }
]