1[
2    {
3        "BriefDescription": "pclk Cycles",
4        "Counter": "0,1,2,3",
5        "EventName": "UNC_P_CLOCKTICKS",
6        "PerPkg": "1",
7        "Unit": "PCU"
8    },
9    {
10        "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
11        "Counter": "0,1,2,3",
12        "EventCode": "0x60",
13        "EventName": "UNC_P_CORE_TRANSITION_CYCLES",
14        "PerPkg": "1",
15        "Unit": "PCU"
16    },
17    {
18        "BriefDescription": "UNC_P_DEMOTIONS",
19        "Counter": "0,1,2,3",
20        "EventCode": "0x30",
21        "EventName": "UNC_P_DEMOTIONS",
22        "PerPkg": "1",
23        "Unit": "PCU"
24    },
25    {
26        "BriefDescription": "Phase Shed 0 Cycles",
27        "Counter": "0,1,2,3",
28        "EventCode": "0x75",
29        "EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
30        "PerPkg": "1",
31        "Unit": "PCU"
32    },
33    {
34        "BriefDescription": "Phase Shed 1 Cycles",
35        "Counter": "0,1,2,3",
36        "EventCode": "0x76",
37        "EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
38        "PerPkg": "1",
39        "Unit": "PCU"
40    },
41    {
42        "BriefDescription": "Phase Shed 2 Cycles",
43        "Counter": "0,1,2,3",
44        "EventCode": "0x77",
45        "EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
46        "PerPkg": "1",
47        "Unit": "PCU"
48    },
49    {
50        "BriefDescription": "Phase Shed 3 Cycles",
51        "Counter": "0,1,2,3",
52        "EventCode": "0x78",
53        "EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
54        "PerPkg": "1",
55        "Unit": "PCU"
56    },
57    {
58        "BriefDescription": "Thermal Strongest Upper Limit Cycles",
59        "Counter": "0,1,2,3",
60        "EventCode": "0x4",
61        "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
62        "PerPkg": "1",
63        "Unit": "PCU"
64    },
65    {
66        "BriefDescription": "Power Strongest Upper Limit Cycles",
67        "Counter": "0,1,2,3",
68        "EventCode": "0x5",
69        "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
70        "PerPkg": "1",
71        "Unit": "PCU"
72    },
73    {
74        "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
75        "Counter": "0,1,2,3",
76        "EventCode": "0x73",
77        "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
78        "PerPkg": "1",
79        "Unit": "PCU"
80    },
81    {
82        "BriefDescription": "Cycles spent changing Frequency",
83        "Counter": "0,1,2,3",
84        "EventCode": "0x74",
85        "EventName": "UNC_P_FREQ_TRANS_CYCLES",
86        "PerPkg": "1",
87        "Unit": "PCU"
88    },
89    {
90        "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",
91        "Counter": "0,1,2,3",
92        "EventCode": "0x6",
93        "EventName": "UNC_P_MCP_PROCHOT_CYCLES",
94        "PerPkg": "1",
95        "Unit": "PCU"
96    },
97    {
98        "BriefDescription": "Memory Phase Shedding Cycles",
99        "Counter": "0,1,2,3",
100        "EventCode": "0x2F",
101        "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
102        "PerPkg": "1",
103        "Unit": "PCU"
104    },
105    {
106        "BriefDescription": "Package C State Residency - C0",
107        "Counter": "0,1,2,3",
108        "EventCode": "0x2A",
109        "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
110        "PerPkg": "1",
111        "Unit": "PCU"
112    },
113    {
114        "BriefDescription": "Package C State Residency - C2E",
115        "Counter": "0,1,2,3",
116        "EventCode": "0x2B",
117        "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
118        "PerPkg": "1",
119        "Unit": "PCU"
120    },
121    {
122        "BriefDescription": "Package C State Residency - C3",
123        "Counter": "0,1,2,3",
124        "EventCode": "0x2C",
125        "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
126        "PerPkg": "1",
127        "Unit": "PCU"
128    },
129    {
130        "BriefDescription": "Package C State Residency - C6",
131        "Counter": "0,1,2,3",
132        "EventCode": "0x2D",
133        "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
134        "PerPkg": "1",
135        "Unit": "PCU"
136    },
137    {
138        "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
139        "Counter": "0,1,2,3",
140        "EventCode": "0x7",
141        "EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
142        "PerPkg": "1",
143        "Unit": "PCU"
144    },
145    {
146        "BriefDescription": "Number of cores in C-State; C0 and C1",
147        "Counter": "0,1,2,3",
148        "EventCode": "0x80",
149        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
150        "PerPkg": "1",
151        "Unit": "PCU"
152    },
153    {
154        "BriefDescription": "Number of cores in C-State; C3",
155        "Counter": "0,1,2,3",
156        "EventCode": "0x80",
157        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
158        "PerPkg": "1",
159        "Unit": "PCU"
160    },
161    {
162        "BriefDescription": "Number of cores in C-State; C6 and C7",
163        "Counter": "0,1,2,3",
164        "EventCode": "0x80",
165        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
166        "PerPkg": "1",
167        "Unit": "PCU"
168    },
169    {
170        "BriefDescription": "External Prochot",
171        "Counter": "0,1,2,3",
172        "EventCode": "0xA",
173        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
174        "PerPkg": "1",
175        "Unit": "PCU"
176    },
177    {
178        "BriefDescription": "Internal Prochot",
179        "Counter": "0,1,2,3",
180        "EventCode": "0x9",
181        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
182        "PerPkg": "1",
183        "Unit": "PCU"
184    },
185    {
186        "BriefDescription": "Total Core C State Transition Cycles",
187        "Counter": "0,1,2,3",
188        "EventCode": "0x72",
189        "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
190        "PerPkg": "1",
191        "Unit": "PCU"
192    },
193    {
194        "BriefDescription": "VR Hot",
195        "Counter": "0,1,2,3",
196        "EventCode": "0x42",
197        "EventName": "UNC_P_VR_HOT_CYCLES",
198        "PerPkg": "1",
199        "Unit": "PCU"
200    }
201]
202