1[ 2 { 3 "BriefDescription": "DRAM Page Activate commands sent due to a write request", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x1", 6 "EventName": "UNC_M_ACT_COUNT.WR", 7 "PerPkg": "1", 8 "UMask": "0x2", 9 "Unit": "iMC" 10 }, 11 { 12 "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)", 13 "Counter": "0,1,2,3", 14 "EventCode": "0x4", 15 "EventName": "UNC_M_CAS_COUNT.RD_REG", 16 "PerPkg": "1", 17 "UMask": "0x1", 18 "Unit": "iMC" 19 }, 20 { 21 "BriefDescription": "DRAM Underfill Read CAS Commands issued", 22 "Counter": "0,1,2,3", 23 "EventCode": "0x4", 24 "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", 25 "PerPkg": "1", 26 "UMask": "0x2", 27 "Unit": "iMC" 28 }, 29 { 30 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", 31 "Counter": "0,1,2,3", 32 "EventCode": "0x4", 33 "EventName": "LLC_MISSES.MEM_READ", 34 "PerPkg": "1", 35 "ScaleUnit": "64Bytes", 36 "UMask": "0x3", 37 "Unit": "iMC" 38 }, 39 { 40 "BriefDescription": "read requests to memory controller", 41 "Counter": "0,1,2,3", 42 "EventCode": "0x4", 43 "EventName": "UNC_M_CAS_COUNT.RD", 44 "PerPkg": "1", 45 "ScaleUnit": "64Bytes", 46 "UMask": "0x3", 47 "Unit": "iMC" 48 }, 49 { 50 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", 51 "Counter": "0,1,2,3", 52 "EventCode": "0x4", 53 "EventName": "UNC_M_CAS_COUNT.WR_WMM", 54 "PerPkg": "1", 55 "UMask": "0x4", 56 "Unit": "iMC" 57 }, 58 { 59 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 60 "Counter": "0,1,2,3", 61 "EventCode": "0x4", 62 "EventName": "LLC_MISSES.MEM_WRITE", 63 "PerPkg": "1", 64 "ScaleUnit": "64Bytes", 65 "UMask": "0xC", 66 "Unit": "iMC" 67 }, 68 { 69 "BriefDescription": "write requests to memory controller", 70 "Counter": "0,1,2,3", 71 "EventCode": "0x4", 72 "EventName": "UNC_M_CAS_COUNT.WR", 73 "PerPkg": "1", 74 "ScaleUnit": "64Bytes", 75 "UMask": "0xC", 76 "Unit": "iMC" 77 }, 78 { 79 "BriefDescription": "All DRAM CAS Commands issued", 80 "Counter": "0,1,2,3", 81 "EventCode": "0x4", 82 "EventName": "UNC_M_CAS_COUNT.ALL", 83 "PerPkg": "1", 84 "UMask": "0xF", 85 "Unit": "iMC" 86 }, 87 { 88 "BriefDescription": "Memory controller clock ticks", 89 "Counter": "0,1,2,3", 90 "EventName": "UNC_M_CLOCKTICKS", 91 "PerPkg": "1", 92 "Unit": "iMC" 93 }, 94 { 95 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode", 96 "Counter": "0,1,2,3", 97 "EventCode": "0x85", 98 "EventName": "UNC_M_POWER_CHANNEL_PPD", 99 "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.", 100 "MetricName": "power_channel_ppd %", 101 "PerPkg": "1", 102 "Unit": "iMC" 103 }, 104 { 105 "BriefDescription": "Cycles Memory is in self refresh power mode", 106 "Counter": "0,1,2,3", 107 "EventCode": "0x43", 108 "EventName": "UNC_M_POWER_SELF_REFRESH", 109 "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.", 110 "MetricName": "power_self_refresh %", 111 "PerPkg": "1", 112 "Unit": "iMC" 113 }, 114 { 115 "BriefDescription": "Pre-charges due to page misses", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x2", 118 "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", 119 "PerPkg": "1", 120 "UMask": "0x1", 121 "Unit": "iMC" 122 }, 123 { 124 "BriefDescription": "Pre-charge for reads", 125 "Counter": "0,1,2,3", 126 "EventCode": "0x2", 127 "EventName": "UNC_M_PRE_COUNT.RD", 128 "PerPkg": "1", 129 "UMask": "0x4", 130 "Unit": "iMC" 131 }, 132 { 133 "BriefDescription": "Read Pending Queue Allocations", 134 "Counter": "0,1,2,3", 135 "EventCode": "0x10", 136 "EventName": "UNC_M_RPQ_INSERTS", 137 "PerPkg": "1", 138 "Unit": "iMC" 139 }, 140 { 141 "BriefDescription": "Read Pending Queue Occupancy", 142 "Counter": "0,1,2,3", 143 "EventCode": "0x80", 144 "EventName": "UNC_M_RPQ_OCCUPANCY", 145 "PerPkg": "1", 146 "Unit": "iMC" 147 }, 148 { 149 "BriefDescription": "Write Pending Queue Allocations", 150 "Counter": "0,1,2,3", 151 "EventCode": "0x20", 152 "EventName": "UNC_M_WPQ_INSERTS", 153 "PerPkg": "1", 154 "Unit": "iMC" 155 }, 156 { 157 "BriefDescription": "Write Pending Queue Occupancy", 158 "Counter": "0,1,2,3", 159 "EventCode": "0x81", 160 "EventName": "UNC_M_WPQ_OCCUPANCY", 161 "PerPkg": "1", 162 "Unit": "iMC" 163 }, 164 { 165 "BriefDescription": "DRAM Activate Count; Activate due to Read", 166 "Counter": "0,1,2,3", 167 "EventCode": "0x1", 168 "EventName": "UNC_M_ACT_COUNT.RD", 169 "PerPkg": "1", 170 "UMask": "0x1", 171 "Unit": "iMC" 172 }, 173 { 174 "BriefDescription": "DRAM Activate Count; Activate due to Bypass", 175 "Counter": "0,1,2,3", 176 "EventCode": "0x1", 177 "EventName": "UNC_M_ACT_COUNT.BYP", 178 "PerPkg": "1", 179 "UMask": "0x8", 180 "Unit": "iMC" 181 }, 182 { 183 "BriefDescription": "ACT command issued by 2 cycle bypass", 184 "Counter": "0,1,2,3", 185 "EventCode": "0xA1", 186 "EventName": "UNC_M_BYP_CMDS.ACT", 187 "PerPkg": "1", 188 "UMask": "0x1", 189 "Unit": "iMC" 190 }, 191 { 192 "BriefDescription": "CAS command issued by 2 cycle bypass", 193 "Counter": "0,1,2,3", 194 "EventCode": "0xA1", 195 "EventName": "UNC_M_BYP_CMDS.CAS", 196 "PerPkg": "1", 197 "UMask": "0x2", 198 "Unit": "iMC" 199 }, 200 { 201 "BriefDescription": "PRE command issued by 2 cycle bypass", 202 "Counter": "0,1,2,3", 203 "EventCode": "0xA1", 204 "EventName": "UNC_M_BYP_CMDS.PRE", 205 "PerPkg": "1", 206 "UMask": "0x4", 207 "Unit": "iMC" 208 }, 209 { 210 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", 211 "Counter": "0,1,2,3", 212 "EventCode": "0x4", 213 "EventName": "UNC_M_CAS_COUNT.WR_RMM", 214 "PerPkg": "1", 215 "UMask": "0x8", 216 "Unit": "iMC" 217 }, 218 { 219 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM", 220 "Counter": "0,1,2,3", 221 "EventCode": "0x4", 222 "EventName": "UNC_M_CAS_COUNT.RD_WMM", 223 "PerPkg": "1", 224 "UMask": "0x10", 225 "Unit": "iMC" 226 }, 227 { 228 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM", 229 "Counter": "0,1,2,3", 230 "EventCode": "0x4", 231 "EventName": "UNC_M_CAS_COUNT.RD_RMM", 232 "PerPkg": "1", 233 "UMask": "0x20", 234 "Unit": "iMC" 235 }, 236 { 237 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode", 238 "Counter": "0,1,2,3", 239 "EventCode": "0x4", 240 "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", 241 "PerPkg": "1", 242 "UMask": "0x40", 243 "Unit": "iMC" 244 }, 245 { 246 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode", 247 "Counter": "0,1,2,3", 248 "EventCode": "0x4", 249 "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", 250 "PerPkg": "1", 251 "UMask": "0x80", 252 "Unit": "iMC" 253 }, 254 { 255 "BriefDescription": "DRAM Precharge All Commands", 256 "Counter": "0,1,2,3", 257 "EventCode": "0x6", 258 "EventName": "UNC_M_DRAM_PRE_ALL", 259 "PerPkg": "1", 260 "Unit": "iMC" 261 }, 262 { 263 "BriefDescription": "Number of DRAM Refreshes Issued", 264 "Counter": "0,1,2,3", 265 "EventCode": "0x5", 266 "EventName": "UNC_M_DRAM_REFRESH.PANIC", 267 "PerPkg": "1", 268 "UMask": "0x2", 269 "Unit": "iMC" 270 }, 271 { 272 "BriefDescription": "Number of DRAM Refreshes Issued", 273 "Counter": "0,1,2,3", 274 "EventCode": "0x5", 275 "EventName": "UNC_M_DRAM_REFRESH.HIGH", 276 "PerPkg": "1", 277 "UMask": "0x4", 278 "Unit": "iMC" 279 }, 280 { 281 "BriefDescription": "ECC Correctable Errors", 282 "Counter": "0,1,2,3", 283 "EventCode": "0x9", 284 "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", 285 "PerPkg": "1", 286 "Unit": "iMC" 287 }, 288 { 289 "BriefDescription": "Cycles in a Major Mode; Read Major Mode", 290 "Counter": "0,1,2,3", 291 "EventCode": "0x7", 292 "EventName": "UNC_M_MAJOR_MODES.READ", 293 "PerPkg": "1", 294 "UMask": "0x1", 295 "Unit": "iMC" 296 }, 297 { 298 "BriefDescription": "Cycles in a Major Mode; Write Major Mode", 299 "Counter": "0,1,2,3", 300 "EventCode": "0x7", 301 "EventName": "UNC_M_MAJOR_MODES.WRITE", 302 "PerPkg": "1", 303 "UMask": "0x2", 304 "Unit": "iMC" 305 }, 306 { 307 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x7", 310 "EventName": "UNC_M_MAJOR_MODES.PARTIAL", 311 "PerPkg": "1", 312 "UMask": "0x4", 313 "Unit": "iMC" 314 }, 315 { 316 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", 317 "Counter": "0,1,2,3", 318 "EventCode": "0x7", 319 "EventName": "UNC_M_MAJOR_MODES.ISOCH", 320 "PerPkg": "1", 321 "UMask": "0x8", 322 "Unit": "iMC" 323 }, 324 { 325 "BriefDescription": "Channel DLLOFF Cycles", 326 "Counter": "0,1,2,3", 327 "EventCode": "0x84", 328 "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", 329 "PerPkg": "1", 330 "Unit": "iMC" 331 }, 332 { 333 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 334 "Counter": "0,1,2,3", 335 "EventCode": "0x83", 336 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", 337 "PerPkg": "1", 338 "UMask": "0x1", 339 "Unit": "iMC" 340 }, 341 { 342 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 343 "Counter": "0,1,2,3", 344 "EventCode": "0x83", 345 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", 346 "PerPkg": "1", 347 "UMask": "0x2", 348 "Unit": "iMC" 349 }, 350 { 351 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 352 "Counter": "0,1,2,3", 353 "EventCode": "0x83", 354 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", 355 "PerPkg": "1", 356 "UMask": "0x4", 357 "Unit": "iMC" 358 }, 359 { 360 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 361 "Counter": "0,1,2,3", 362 "EventCode": "0x83", 363 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", 364 "PerPkg": "1", 365 "UMask": "0x8", 366 "Unit": "iMC" 367 }, 368 { 369 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 370 "Counter": "0,1,2,3", 371 "EventCode": "0x83", 372 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", 373 "PerPkg": "1", 374 "UMask": "0x10", 375 "Unit": "iMC" 376 }, 377 { 378 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 379 "Counter": "0,1,2,3", 380 "EventCode": "0x83", 381 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", 382 "PerPkg": "1", 383 "UMask": "0x20", 384 "Unit": "iMC" 385 }, 386 { 387 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 388 "Counter": "0,1,2,3", 389 "EventCode": "0x83", 390 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", 391 "PerPkg": "1", 392 "UMask": "0x40", 393 "Unit": "iMC" 394 }, 395 { 396 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", 397 "Counter": "0,1,2,3", 398 "EventCode": "0x83", 399 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", 400 "PerPkg": "1", 401 "UMask": "0x80", 402 "Unit": "iMC" 403 }, 404 { 405 "BriefDescription": "Critical Throttle Cycles", 406 "Counter": "0,1,2,3", 407 "EventCode": "0x86", 408 "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", 409 "PerPkg": "1", 410 "Unit": "iMC" 411 }, 412 { 413 "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", 414 "Counter": "0,1,2,3", 415 "EventCode": "0x42", 416 "EventName": "UNC_M_POWER_PCU_THROTTLING", 417 "PerPkg": "1", 418 "Unit": "iMC" 419 }, 420 { 421 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 422 "Counter": "0,1,2,3", 423 "EventCode": "0x41", 424 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", 425 "PerPkg": "1", 426 "UMask": "0x1", 427 "Unit": "iMC" 428 }, 429 { 430 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 431 "Counter": "0,1,2,3", 432 "EventCode": "0x41", 433 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", 434 "PerPkg": "1", 435 "UMask": "0x2", 436 "Unit": "iMC" 437 }, 438 { 439 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 440 "Counter": "0,1,2,3", 441 "EventCode": "0x41", 442 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", 443 "PerPkg": "1", 444 "UMask": "0x4", 445 "Unit": "iMC" 446 }, 447 { 448 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 449 "Counter": "0,1,2,3", 450 "EventCode": "0x41", 451 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", 452 "PerPkg": "1", 453 "UMask": "0x8", 454 "Unit": "iMC" 455 }, 456 { 457 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 458 "Counter": "0,1,2,3", 459 "EventCode": "0x41", 460 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", 461 "PerPkg": "1", 462 "UMask": "0x10", 463 "Unit": "iMC" 464 }, 465 { 466 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 467 "Counter": "0,1,2,3", 468 "EventCode": "0x41", 469 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", 470 "PerPkg": "1", 471 "UMask": "0x20", 472 "Unit": "iMC" 473 }, 474 { 475 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x41", 478 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", 479 "PerPkg": "1", 480 "UMask": "0x40", 481 "Unit": "iMC" 482 }, 483 { 484 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", 485 "Counter": "0,1,2,3", 486 "EventCode": "0x41", 487 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", 488 "PerPkg": "1", 489 "UMask": "0x80", 490 "Unit": "iMC" 491 }, 492 { 493 "BriefDescription": "Read Preemption Count; Read over Read Preemption", 494 "Counter": "0,1,2,3", 495 "EventCode": "0x8", 496 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", 497 "PerPkg": "1", 498 "UMask": "0x1", 499 "Unit": "iMC" 500 }, 501 { 502 "BriefDescription": "Read Preemption Count; Read over Write Preemption", 503 "Counter": "0,1,2,3", 504 "EventCode": "0x8", 505 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", 506 "PerPkg": "1", 507 "UMask": "0x2", 508 "Unit": "iMC" 509 }, 510 { 511 "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration", 512 "Counter": "0,1,2,3", 513 "EventCode": "0x2", 514 "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", 515 "PerPkg": "1", 516 "UMask": "0x2", 517 "Unit": "iMC" 518 }, 519 { 520 "BriefDescription": "Pre-charge for writes", 521 "Counter": "0,1,2,3", 522 "EventCode": "0x2", 523 "EventName": "UNC_M_PRE_COUNT.WR", 524 "PerPkg": "1", 525 "UMask": "0x8", 526 "Unit": "iMC" 527 }, 528 { 529 "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass", 530 "Counter": "0,1,2,3", 531 "EventCode": "0x2", 532 "EventName": "UNC_M_PRE_COUNT.BYP", 533 "PerPkg": "1", 534 "UMask": "0x10", 535 "Unit": "iMC" 536 }, 537 { 538 "BriefDescription": "Read CAS issued with LOW priority", 539 "Counter": "0,1,2,3", 540 "EventCode": "0xA0", 541 "EventName": "UNC_M_RD_CAS_PRIO.LOW", 542 "PerPkg": "1", 543 "UMask": "0x1", 544 "Unit": "iMC" 545 }, 546 { 547 "BriefDescription": "Read CAS issued with MEDIUM priority", 548 "Counter": "0,1,2,3", 549 "EventCode": "0xA0", 550 "EventName": "UNC_M_RD_CAS_PRIO.MED", 551 "PerPkg": "1", 552 "UMask": "0x2", 553 "Unit": "iMC" 554 }, 555 { 556 "BriefDescription": "Read CAS issued with HIGH priority", 557 "Counter": "0,1,2,3", 558 "EventCode": "0xA0", 559 "EventName": "UNC_M_RD_CAS_PRIO.HIGH", 560 "PerPkg": "1", 561 "UMask": "0x4", 562 "Unit": "iMC" 563 }, 564 { 565 "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)", 566 "Counter": "0,1,2,3", 567 "EventCode": "0xA0", 568 "EventName": "UNC_M_RD_CAS_PRIO.PANIC", 569 "PerPkg": "1", 570 "UMask": "0x8", 571 "Unit": "iMC" 572 }, 573 { 574 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", 575 "Counter": "0,1,2,3", 576 "EventCode": "0xB0", 577 "EventName": "UNC_M_RD_CAS_RANK0.BANK0", 578 "PerPkg": "1", 579 "Unit": "iMC" 580 }, 581 { 582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", 583 "Counter": "0,1,2,3", 584 "EventCode": "0xB0", 585 "EventName": "UNC_M_RD_CAS_RANK0.BANK1", 586 "PerPkg": "1", 587 "UMask": "0x1", 588 "Unit": "iMC" 589 }, 590 { 591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", 592 "Counter": "0,1,2,3", 593 "EventCode": "0xB0", 594 "EventName": "UNC_M_RD_CAS_RANK0.BANK2", 595 "PerPkg": "1", 596 "UMask": "0x2", 597 "Unit": "iMC" 598 }, 599 { 600 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", 601 "Counter": "0,1,2,3", 602 "EventCode": "0xB0", 603 "EventName": "UNC_M_RD_CAS_RANK0.BANK3", 604 "PerPkg": "1", 605 "UMask": "0x3", 606 "Unit": "iMC" 607 }, 608 { 609 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", 610 "Counter": "0,1,2,3", 611 "EventCode": "0xB0", 612 "EventName": "UNC_M_RD_CAS_RANK0.BANK4", 613 "PerPkg": "1", 614 "UMask": "0x4", 615 "Unit": "iMC" 616 }, 617 { 618 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", 619 "Counter": "0,1,2,3", 620 "EventCode": "0xB0", 621 "EventName": "UNC_M_RD_CAS_RANK0.BANK5", 622 "PerPkg": "1", 623 "UMask": "0x5", 624 "Unit": "iMC" 625 }, 626 { 627 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", 628 "Counter": "0,1,2,3", 629 "EventCode": "0xB0", 630 "EventName": "UNC_M_RD_CAS_RANK0.BANK6", 631 "PerPkg": "1", 632 "UMask": "0x6", 633 "Unit": "iMC" 634 }, 635 { 636 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", 637 "Counter": "0,1,2,3", 638 "EventCode": "0xB0", 639 "EventName": "UNC_M_RD_CAS_RANK0.BANK7", 640 "PerPkg": "1", 641 "UMask": "0x7", 642 "Unit": "iMC" 643 }, 644 { 645 "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", 646 "Counter": "0,1,2,3", 647 "EventCode": "0xB0", 648 "EventName": "UNC_M_RD_CAS_RANK0.BANK8", 649 "PerPkg": "1", 650 "UMask": "0x8", 651 "Unit": "iMC" 652 }, 653 { 654 "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", 655 "Counter": "0,1,2,3", 656 "EventCode": "0xB0", 657 "EventName": "UNC_M_RD_CAS_RANK0.BANK9", 658 "PerPkg": "1", 659 "UMask": "0x9", 660 "Unit": "iMC" 661 }, 662 { 663 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", 664 "Counter": "0,1,2,3", 665 "EventCode": "0xB0", 666 "EventName": "UNC_M_RD_CAS_RANK0.BANK10", 667 "PerPkg": "1", 668 "UMask": "0xA", 669 "Unit": "iMC" 670 }, 671 { 672 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", 673 "Counter": "0,1,2,3", 674 "EventCode": "0xB0", 675 "EventName": "UNC_M_RD_CAS_RANK0.BANK11", 676 "PerPkg": "1", 677 "UMask": "0xB", 678 "Unit": "iMC" 679 }, 680 { 681 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", 682 "Counter": "0,1,2,3", 683 "EventCode": "0xB0", 684 "EventName": "UNC_M_RD_CAS_RANK0.BANK12", 685 "PerPkg": "1", 686 "UMask": "0xC", 687 "Unit": "iMC" 688 }, 689 { 690 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", 691 "Counter": "0,1,2,3", 692 "EventCode": "0xB0", 693 "EventName": "UNC_M_RD_CAS_RANK0.BANK13", 694 "PerPkg": "1", 695 "UMask": "0xD", 696 "Unit": "iMC" 697 }, 698 { 699 "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", 700 "Counter": "0,1,2,3", 701 "EventCode": "0xB0", 702 "EventName": "UNC_M_RD_CAS_RANK0.BANK14", 703 "PerPkg": "1", 704 "UMask": "0xE", 705 "Unit": "iMC" 706 }, 707 { 708 "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", 709 "Counter": "0,1,2,3", 710 "EventCode": "0xB0", 711 "EventName": "UNC_M_RD_CAS_RANK0.BANK15", 712 "PerPkg": "1", 713 "UMask": "0xF", 714 "Unit": "iMC" 715 }, 716 { 717 "BriefDescription": "RD_CAS Access to Rank 0; All Banks", 718 "Counter": "0,1,2,3", 719 "EventCode": "0xB0", 720 "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", 721 "PerPkg": "1", 722 "UMask": "0x10", 723 "Unit": "iMC" 724 }, 725 { 726 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 727 "Counter": "0,1,2,3", 728 "EventCode": "0xB0", 729 "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", 730 "PerPkg": "1", 731 "UMask": "0x11", 732 "Unit": "iMC" 733 }, 734 { 735 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 736 "Counter": "0,1,2,3", 737 "EventCode": "0xB0", 738 "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", 739 "PerPkg": "1", 740 "UMask": "0x12", 741 "Unit": "iMC" 742 }, 743 { 744 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 745 "Counter": "0,1,2,3", 746 "EventCode": "0xB0", 747 "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", 748 "PerPkg": "1", 749 "UMask": "0x13", 750 "Unit": "iMC" 751 }, 752 { 753 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 754 "Counter": "0,1,2,3", 755 "EventCode": "0xB0", 756 "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", 757 "PerPkg": "1", 758 "UMask": "0x14", 759 "Unit": "iMC" 760 }, 761 { 762 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", 763 "Counter": "0,1,2,3", 764 "EventCode": "0xB1", 765 "EventName": "UNC_M_RD_CAS_RANK1.BANK0", 766 "PerPkg": "1", 767 "Unit": "iMC" 768 }, 769 { 770 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", 771 "Counter": "0,1,2,3", 772 "EventCode": "0xB1", 773 "EventName": "UNC_M_RD_CAS_RANK1.BANK1", 774 "PerPkg": "1", 775 "UMask": "0x1", 776 "Unit": "iMC" 777 }, 778 { 779 "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", 780 "Counter": "0,1,2,3", 781 "EventCode": "0xB1", 782 "EventName": "UNC_M_RD_CAS_RANK1.BANK2", 783 "PerPkg": "1", 784 "UMask": "0x2", 785 "Unit": "iMC" 786 }, 787 { 788 "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", 789 "Counter": "0,1,2,3", 790 "EventCode": "0xB1", 791 "EventName": "UNC_M_RD_CAS_RANK1.BANK3", 792 "PerPkg": "1", 793 "UMask": "0x3", 794 "Unit": "iMC" 795 }, 796 { 797 "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", 798 "Counter": "0,1,2,3", 799 "EventCode": "0xB1", 800 "EventName": "UNC_M_RD_CAS_RANK1.BANK4", 801 "PerPkg": "1", 802 "UMask": "0x4", 803 "Unit": "iMC" 804 }, 805 { 806 "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", 807 "Counter": "0,1,2,3", 808 "EventCode": "0xB1", 809 "EventName": "UNC_M_RD_CAS_RANK1.BANK5", 810 "PerPkg": "1", 811 "UMask": "0x5", 812 "Unit": "iMC" 813 }, 814 { 815 "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", 816 "Counter": "0,1,2,3", 817 "EventCode": "0xB1", 818 "EventName": "UNC_M_RD_CAS_RANK1.BANK6", 819 "PerPkg": "1", 820 "UMask": "0x6", 821 "Unit": "iMC" 822 }, 823 { 824 "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", 825 "Counter": "0,1,2,3", 826 "EventCode": "0xB1", 827 "EventName": "UNC_M_RD_CAS_RANK1.BANK7", 828 "PerPkg": "1", 829 "UMask": "0x7", 830 "Unit": "iMC" 831 }, 832 { 833 "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", 834 "Counter": "0,1,2,3", 835 "EventCode": "0xB1", 836 "EventName": "UNC_M_RD_CAS_RANK1.BANK8", 837 "PerPkg": "1", 838 "UMask": "0x8", 839 "Unit": "iMC" 840 }, 841 { 842 "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", 843 "Counter": "0,1,2,3", 844 "EventCode": "0xB1", 845 "EventName": "UNC_M_RD_CAS_RANK1.BANK9", 846 "PerPkg": "1", 847 "UMask": "0x9", 848 "Unit": "iMC" 849 }, 850 { 851 "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", 852 "Counter": "0,1,2,3", 853 "EventCode": "0xB1", 854 "EventName": "UNC_M_RD_CAS_RANK1.BANK10", 855 "PerPkg": "1", 856 "UMask": "0xA", 857 "Unit": "iMC" 858 }, 859 { 860 "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", 861 "Counter": "0,1,2,3", 862 "EventCode": "0xB1", 863 "EventName": "UNC_M_RD_CAS_RANK1.BANK11", 864 "PerPkg": "1", 865 "UMask": "0xB", 866 "Unit": "iMC" 867 }, 868 { 869 "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", 870 "Counter": "0,1,2,3", 871 "EventCode": "0xB1", 872 "EventName": "UNC_M_RD_CAS_RANK1.BANK12", 873 "PerPkg": "1", 874 "UMask": "0xC", 875 "Unit": "iMC" 876 }, 877 { 878 "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", 879 "Counter": "0,1,2,3", 880 "EventCode": "0xB1", 881 "EventName": "UNC_M_RD_CAS_RANK1.BANK13", 882 "PerPkg": "1", 883 "UMask": "0xD", 884 "Unit": "iMC" 885 }, 886 { 887 "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", 888 "Counter": "0,1,2,3", 889 "EventCode": "0xB1", 890 "EventName": "UNC_M_RD_CAS_RANK1.BANK14", 891 "PerPkg": "1", 892 "UMask": "0xE", 893 "Unit": "iMC" 894 }, 895 { 896 "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", 897 "Counter": "0,1,2,3", 898 "EventCode": "0xB1", 899 "EventName": "UNC_M_RD_CAS_RANK1.BANK15", 900 "PerPkg": "1", 901 "UMask": "0xF", 902 "Unit": "iMC" 903 }, 904 { 905 "BriefDescription": "RD_CAS Access to Rank 1; All Banks", 906 "Counter": "0,1,2,3", 907 "EventCode": "0xB1", 908 "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", 909 "PerPkg": "1", 910 "UMask": "0x10", 911 "Unit": "iMC" 912 }, 913 { 914 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 915 "Counter": "0,1,2,3", 916 "EventCode": "0xB1", 917 "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", 918 "PerPkg": "1", 919 "UMask": "0x11", 920 "Unit": "iMC" 921 }, 922 { 923 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 924 "Counter": "0,1,2,3", 925 "EventCode": "0xB1", 926 "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", 927 "PerPkg": "1", 928 "UMask": "0x12", 929 "Unit": "iMC" 930 }, 931 { 932 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 933 "Counter": "0,1,2,3", 934 "EventCode": "0xB1", 935 "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", 936 "PerPkg": "1", 937 "UMask": "0x13", 938 "Unit": "iMC" 939 }, 940 { 941 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 942 "Counter": "0,1,2,3", 943 "EventCode": "0xB1", 944 "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", 945 "PerPkg": "1", 946 "UMask": "0x14", 947 "Unit": "iMC" 948 }, 949 { 950 "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", 951 "Counter": "0,1,2,3", 952 "EventCode": "0xB2", 953 "EventName": "UNC_M_RD_CAS_RANK2.BANK0", 954 "PerPkg": "1", 955 "Unit": "iMC" 956 }, 957 { 958 "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", 959 "Counter": "0,1,2,3", 960 "EventCode": "0xB2", 961 "EventName": "UNC_M_RD_CAS_RANK2.BANK1", 962 "PerPkg": "1", 963 "UMask": "0x1", 964 "Unit": "iMC" 965 }, 966 { 967 "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", 968 "Counter": "0,1,2,3", 969 "EventCode": "0xB2", 970 "EventName": "UNC_M_RD_CAS_RANK2.BANK2", 971 "PerPkg": "1", 972 "UMask": "0x2", 973 "Unit": "iMC" 974 }, 975 { 976 "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", 977 "Counter": "0,1,2,3", 978 "EventCode": "0xB2", 979 "EventName": "UNC_M_RD_CAS_RANK2.BANK3", 980 "PerPkg": "1", 981 "UMask": "0x3", 982 "Unit": "iMC" 983 }, 984 { 985 "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", 986 "Counter": "0,1,2,3", 987 "EventCode": "0xB2", 988 "EventName": "UNC_M_RD_CAS_RANK2.BANK4", 989 "PerPkg": "1", 990 "UMask": "0x4", 991 "Unit": "iMC" 992 }, 993 { 994 "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", 995 "Counter": "0,1,2,3", 996 "EventCode": "0xB2", 997 "EventName": "UNC_M_RD_CAS_RANK2.BANK5", 998 "PerPkg": "1", 999 "UMask": "0x5", 1000 "Unit": "iMC" 1001 }, 1002 { 1003 "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", 1004 "Counter": "0,1,2,3", 1005 "EventCode": "0xB2", 1006 "EventName": "UNC_M_RD_CAS_RANK2.BANK6", 1007 "PerPkg": "1", 1008 "UMask": "0x6", 1009 "Unit": "iMC" 1010 }, 1011 { 1012 "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", 1013 "Counter": "0,1,2,3", 1014 "EventCode": "0xB2", 1015 "EventName": "UNC_M_RD_CAS_RANK2.BANK7", 1016 "PerPkg": "1", 1017 "UMask": "0x7", 1018 "Unit": "iMC" 1019 }, 1020 { 1021 "BriefDescription": "RD_CAS Access to Rank 2; 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Bank Group 1 (Banks 4-7)", 1112 "Counter": "0,1,2,3", 1113 "EventCode": "0xB2", 1114 "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", 1115 "PerPkg": "1", 1116 "UMask": "0x12", 1117 "Unit": "iMC" 1118 }, 1119 { 1120 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)", 1121 "Counter": "0,1,2,3", 1122 "EventCode": "0xB2", 1123 "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", 1124 "PerPkg": "1", 1125 "UMask": "0x13", 1126 "Unit": "iMC" 1127 }, 1128 { 1129 "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)", 1130 "Counter": "0,1,2,3", 1131 "EventCode": "0xB2", 1132 "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", 1133 "PerPkg": "1", 1134 "UMask": "0x14", 1135 "Unit": "iMC" 1136 }, 1137 { 1138 "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", 1139 "Counter": "0,1,2,3", 1140 "EventCode": "0xB3", 1141 "EventName": "UNC_M_RD_CAS_RANK3.BANK0", 1142 "PerPkg": "1", 1143 "Unit": "iMC" 1144 }, 1145 { 1146 "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", 1147 "Counter": "0,1,2,3", 1148 "EventCode": "0xB3", 1149 "EventName": "UNC_M_RD_CAS_RANK3.BANK1", 1150 "PerPkg": "1", 1151 "UMask": "0x1", 1152 "Unit": "iMC" 1153 }, 1154 { 1155 "BriefDescription": "RD_CAS Access to Rank 3; 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Bank 12", 1246 "Counter": "0,1,2,3", 1247 "EventCode": "0xB3", 1248 "EventName": "UNC_M_RD_CAS_RANK3.BANK12", 1249 "PerPkg": "1", 1250 "UMask": "0xC", 1251 "Unit": "iMC" 1252 }, 1253 { 1254 "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", 1255 "Counter": "0,1,2,3", 1256 "EventCode": "0xB3", 1257 "EventName": "UNC_M_RD_CAS_RANK3.BANK13", 1258 "PerPkg": "1", 1259 "UMask": "0xD", 1260 "Unit": "iMC" 1261 }, 1262 { 1263 "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", 1264 "Counter": "0,1,2,3", 1265 "EventCode": "0xB3", 1266 "EventName": "UNC_M_RD_CAS_RANK3.BANK14", 1267 "PerPkg": "1", 1268 "UMask": "0xE", 1269 "Unit": "iMC" 1270 }, 1271 { 1272 "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", 1273 "Counter": "0,1,2,3", 1274 "EventCode": "0xB3", 1275 "EventName": "UNC_M_RD_CAS_RANK3.BANK15", 1276 "PerPkg": "1", 1277 "UMask": "0xF", 1278 "Unit": "iMC" 1279 }, 1280 { 1281 "BriefDescription": "RD_CAS Access to Rank 3; All Banks", 1282 "Counter": "0,1,2,3", 1283 "EventCode": "0xB3", 1284 "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", 1285 "PerPkg": "1", 1286 "UMask": "0x10", 1287 "Unit": "iMC" 1288 }, 1289 { 1290 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)", 1291 "Counter": "0,1,2,3", 1292 "EventCode": "0xB3", 1293 "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", 1294 "PerPkg": "1", 1295 "UMask": "0x11", 1296 "Unit": "iMC" 1297 }, 1298 { 1299 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)", 1300 "Counter": "0,1,2,3", 1301 "EventCode": "0xB3", 1302 "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", 1303 "PerPkg": "1", 1304 "UMask": "0x12", 1305 "Unit": "iMC" 1306 }, 1307 { 1308 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)", 1309 "Counter": "0,1,2,3", 1310 "EventCode": "0xB3", 1311 "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", 1312 "PerPkg": "1", 1313 "UMask": "0x13", 1314 "Unit": "iMC" 1315 }, 1316 { 1317 "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)", 1318 "Counter": "0,1,2,3", 1319 "EventCode": "0xB3", 1320 "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", 1321 "PerPkg": "1", 1322 "UMask": "0x14", 1323 "Unit": "iMC" 1324 }, 1325 { 1326 "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", 1327 "Counter": "0,1,2,3", 1328 "EventCode": "0xB4", 1329 "EventName": "UNC_M_RD_CAS_RANK4.BANK0", 1330 "PerPkg": "1", 1331 "Unit": "iMC" 1332 }, 1333 { 1334 "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", 1335 "Counter": "0,1,2,3", 1336 "EventCode": "0xB4", 1337 "EventName": "UNC_M_RD_CAS_RANK4.BANK1", 1338 "PerPkg": "1", 1339 "UMask": "0x1", 1340 "Unit": "iMC" 1341 }, 1342 { 1343 "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", 1344 "Counter": "0,1,2,3", 1345 "EventCode": "0xB4", 1346 "EventName": "UNC_M_RD_CAS_RANK4.BANK2", 1347 "PerPkg": "1", 1348 "UMask": "0x2", 1349 "Unit": "iMC" 1350 }, 1351 { 1352 "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", 1353 "Counter": "0,1,2,3", 1354 "EventCode": "0xB4", 1355 "EventName": "UNC_M_RD_CAS_RANK4.BANK3", 1356 "PerPkg": "1", 1357 "UMask": "0x3", 1358 "Unit": "iMC" 1359 }, 1360 { 1361 "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", 1362 "Counter": "0,1,2,3", 1363 "EventCode": "0xB4", 1364 "EventName": "UNC_M_RD_CAS_RANK4.BANK4", 1365 "PerPkg": "1", 1366 "UMask": "0x4", 1367 "Unit": "iMC" 1368 }, 1369 { 1370 "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", 1371 "Counter": "0,1,2,3", 1372 "EventCode": "0xB4", 1373 "EventName": "UNC_M_RD_CAS_RANK4.BANK5", 1374 "PerPkg": "1", 1375 "UMask": "0x5", 1376 "Unit": "iMC" 1377 }, 1378 { 1379 "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", 1380 "Counter": "0,1,2,3", 1381 "EventCode": "0xB4", 1382 "EventName": "UNC_M_RD_CAS_RANK4.BANK6", 1383 "PerPkg": "1", 1384 "UMask": "0x6", 1385 "Unit": "iMC" 1386 }, 1387 { 1388 "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", 1389 "Counter": "0,1,2,3", 1390 "EventCode": "0xB4", 1391 "EventName": "UNC_M_RD_CAS_RANK4.BANK7", 1392 "PerPkg": "1", 1393 "UMask": "0x7", 1394 "Unit": "iMC" 1395 }, 1396 { 1397 "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", 1398 "Counter": "0,1,2,3", 1399 "EventCode": "0xB4", 1400 "EventName": "UNC_M_RD_CAS_RANK4.BANK8", 1401 "PerPkg": "1", 1402 "UMask": "0x8", 1403 "Unit": "iMC" 1404 }, 1405 { 1406 "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", 1407 "Counter": "0,1,2,3", 1408 "EventCode": "0xB4", 1409 "EventName": "UNC_M_RD_CAS_RANK4.BANK9", 1410 "PerPkg": "1", 1411 "UMask": "0x9", 1412 "Unit": "iMC" 1413 }, 1414 { 1415 "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", 1416 "Counter": "0,1,2,3", 1417 "EventCode": "0xB4", 1418 "EventName": "UNC_M_RD_CAS_RANK4.BANK10", 1419 "PerPkg": "1", 1420 "UMask": "0xA", 1421 "Unit": "iMC" 1422 }, 1423 { 1424 "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", 1425 "Counter": "0,1,2,3", 1426 "EventCode": "0xB4", 1427 "EventName": "UNC_M_RD_CAS_RANK4.BANK11", 1428 "PerPkg": "1", 1429 "UMask": "0xB", 1430 "Unit": "iMC" 1431 }, 1432 { 1433 "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", 1434 "Counter": "0,1,2,3", 1435 "EventCode": "0xB4", 1436 "EventName": "UNC_M_RD_CAS_RANK4.BANK12", 1437 "PerPkg": "1", 1438 "UMask": "0xC", 1439 "Unit": "iMC" 1440 }, 1441 { 1442 "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", 1443 "Counter": "0,1,2,3", 1444 "EventCode": "0xB4", 1445 "EventName": "UNC_M_RD_CAS_RANK4.BANK13", 1446 "PerPkg": "1", 1447 "UMask": "0xD", 1448 "Unit": "iMC" 1449 }, 1450 { 1451 "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", 1452 "Counter": "0,1,2,3", 1453 "EventCode": "0xB4", 1454 "EventName": "UNC_M_RD_CAS_RANK4.BANK14", 1455 "PerPkg": "1", 1456 "UMask": "0xE", 1457 "Unit": "iMC" 1458 }, 1459 { 1460 "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", 1461 "Counter": "0,1,2,3", 1462 "EventCode": "0xB4", 1463 "EventName": "UNC_M_RD_CAS_RANK4.BANK15", 1464 "PerPkg": "1", 1465 "UMask": "0xF", 1466 "Unit": "iMC" 1467 }, 1468 { 1469 "BriefDescription": "RD_CAS Access to Rank 4; All Banks", 1470 "Counter": "0,1,2,3", 1471 "EventCode": "0xB4", 1472 "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", 1473 "PerPkg": "1", 1474 "UMask": "0x10", 1475 "Unit": "iMC" 1476 }, 1477 { 1478 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)", 1479 "Counter": "0,1,2,3", 1480 "EventCode": "0xB4", 1481 "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", 1482 "PerPkg": "1", 1483 "UMask": "0x11", 1484 "Unit": "iMC" 1485 }, 1486 { 1487 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)", 1488 "Counter": "0,1,2,3", 1489 "EventCode": "0xB4", 1490 "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", 1491 "PerPkg": "1", 1492 "UMask": "0x12", 1493 "Unit": "iMC" 1494 }, 1495 { 1496 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)", 1497 "Counter": "0,1,2,3", 1498 "EventCode": "0xB4", 1499 "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", 1500 "PerPkg": "1", 1501 "UMask": "0x13", 1502 "Unit": "iMC" 1503 }, 1504 { 1505 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)", 1506 "Counter": "0,1,2,3", 1507 "EventCode": "0xB4", 1508 "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", 1509 "PerPkg": "1", 1510 "UMask": "0x14", 1511 "Unit": "iMC" 1512 }, 1513 { 1514 "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", 1515 "Counter": "0,1,2,3", 1516 "EventCode": "0xB5", 1517 "EventName": "UNC_M_RD_CAS_RANK5.BANK0", 1518 "PerPkg": "1", 1519 "Unit": "iMC" 1520 }, 1521 { 1522 "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", 1523 "Counter": "0,1,2,3", 1524 "EventCode": "0xB5", 1525 "EventName": "UNC_M_RD_CAS_RANK5.BANK1", 1526 "PerPkg": "1", 1527 "UMask": "0x1", 1528 "Unit": "iMC" 1529 }, 1530 { 1531 "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", 1532 "Counter": "0,1,2,3", 1533 "EventCode": "0xB5", 1534 "EventName": "UNC_M_RD_CAS_RANK5.BANK2", 1535 "PerPkg": "1", 1536 "UMask": "0x2", 1537 "Unit": "iMC" 1538 }, 1539 { 1540 "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", 1541 "Counter": "0,1,2,3", 1542 "EventCode": "0xB5", 1543 "EventName": "UNC_M_RD_CAS_RANK5.BANK3", 1544 "PerPkg": "1", 1545 "UMask": "0x3", 1546 "Unit": "iMC" 1547 }, 1548 { 1549 "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", 1550 "Counter": "0,1,2,3", 1551 "EventCode": "0xB5", 1552 "EventName": "UNC_M_RD_CAS_RANK5.BANK4", 1553 "PerPkg": "1", 1554 "UMask": "0x4", 1555 "Unit": "iMC" 1556 }, 1557 { 1558 "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", 1559 "Counter": "0,1,2,3", 1560 "EventCode": "0xB5", 1561 "EventName": "UNC_M_RD_CAS_RANK5.BANK5", 1562 "PerPkg": "1", 1563 "UMask": "0x5", 1564 "Unit": "iMC" 1565 }, 1566 { 1567 "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", 1568 "Counter": "0,1,2,3", 1569 "EventCode": "0xB5", 1570 "EventName": "UNC_M_RD_CAS_RANK5.BANK6", 1571 "PerPkg": "1", 1572 "UMask": "0x6", 1573 "Unit": "iMC" 1574 }, 1575 { 1576 "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", 1577 "Counter": "0,1,2,3", 1578 "EventCode": "0xB5", 1579 "EventName": "UNC_M_RD_CAS_RANK5.BANK7", 1580 "PerPkg": "1", 1581 "UMask": "0x7", 1582 "Unit": "iMC" 1583 }, 1584 { 1585 "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", 1586 "Counter": "0,1,2,3", 1587 "EventCode": "0xB5", 1588 "EventName": "UNC_M_RD_CAS_RANK5.BANK8", 1589 "PerPkg": "1", 1590 "UMask": "0x8", 1591 "Unit": "iMC" 1592 }, 1593 { 1594 "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", 1595 "Counter": "0,1,2,3", 1596 "EventCode": "0xB5", 1597 "EventName": "UNC_M_RD_CAS_RANK5.BANK9", 1598 "PerPkg": "1", 1599 "UMask": "0x9", 1600 "Unit": "iMC" 1601 }, 1602 { 1603 "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", 1604 "Counter": "0,1,2,3", 1605 "EventCode": "0xB5", 1606 "EventName": "UNC_M_RD_CAS_RANK5.BANK10", 1607 "PerPkg": "1", 1608 "UMask": "0xA", 1609 "Unit": "iMC" 1610 }, 1611 { 1612 "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", 1613 "Counter": "0,1,2,3", 1614 "EventCode": "0xB5", 1615 "EventName": "UNC_M_RD_CAS_RANK5.BANK11", 1616 "PerPkg": "1", 1617 "UMask": "0xB", 1618 "Unit": "iMC" 1619 }, 1620 { 1621 "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", 1622 "Counter": "0,1,2,3", 1623 "EventCode": "0xB5", 1624 "EventName": "UNC_M_RD_CAS_RANK5.BANK12", 1625 "PerPkg": "1", 1626 "UMask": "0xC", 1627 "Unit": "iMC" 1628 }, 1629 { 1630 "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", 1631 "Counter": "0,1,2,3", 1632 "EventCode": "0xB5", 1633 "EventName": "UNC_M_RD_CAS_RANK5.BANK13", 1634 "PerPkg": "1", 1635 "UMask": "0xD", 1636 "Unit": "iMC" 1637 }, 1638 { 1639 "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", 1640 "Counter": "0,1,2,3", 1641 "EventCode": "0xB5", 1642 "EventName": "UNC_M_RD_CAS_RANK5.BANK14", 1643 "PerPkg": "1", 1644 "UMask": "0xE", 1645 "Unit": "iMC" 1646 }, 1647 { 1648 "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", 1649 "Counter": "0,1,2,3", 1650 "EventCode": "0xB5", 1651 "EventName": "UNC_M_RD_CAS_RANK5.BANK15", 1652 "PerPkg": "1", 1653 "UMask": "0xF", 1654 "Unit": "iMC" 1655 }, 1656 { 1657 "BriefDescription": "RD_CAS Access to Rank 5; All Banks", 1658 "Counter": "0,1,2,3", 1659 "EventCode": "0xB5", 1660 "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", 1661 "PerPkg": "1", 1662 "UMask": "0x10", 1663 "Unit": "iMC" 1664 }, 1665 { 1666 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)", 1667 "Counter": "0,1,2,3", 1668 "EventCode": "0xB5", 1669 "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", 1670 "PerPkg": "1", 1671 "UMask": "0x11", 1672 "Unit": "iMC" 1673 }, 1674 { 1675 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)", 1676 "Counter": "0,1,2,3", 1677 "EventCode": "0xB5", 1678 "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", 1679 "PerPkg": "1", 1680 "UMask": "0x12", 1681 "Unit": "iMC" 1682 }, 1683 { 1684 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)", 1685 "Counter": "0,1,2,3", 1686 "EventCode": "0xB5", 1687 "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", 1688 "PerPkg": "1", 1689 "UMask": "0x13", 1690 "Unit": "iMC" 1691 }, 1692 { 1693 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)", 1694 "Counter": "0,1,2,3", 1695 "EventCode": "0xB5", 1696 "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", 1697 "PerPkg": "1", 1698 "UMask": "0x14", 1699 "Unit": "iMC" 1700 }, 1701 { 1702 "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", 1703 "Counter": "0,1,2,3", 1704 "EventCode": "0xB6", 1705 "EventName": "UNC_M_RD_CAS_RANK6.BANK0", 1706 "PerPkg": "1", 1707 "Unit": "iMC" 1708 }, 1709 { 1710 "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", 1711 "Counter": "0,1,2,3", 1712 "EventCode": "0xB6", 1713 "EventName": "UNC_M_RD_CAS_RANK6.BANK1", 1714 "PerPkg": "1", 1715 "UMask": "0x1", 1716 "Unit": "iMC" 1717 }, 1718 { 1719 "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", 1720 "Counter": "0,1,2,3", 1721 "EventCode": "0xB6", 1722 "EventName": "UNC_M_RD_CAS_RANK6.BANK2", 1723 "PerPkg": "1", 1724 "UMask": "0x2", 1725 "Unit": "iMC" 1726 }, 1727 { 1728 "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", 1729 "Counter": "0,1,2,3", 1730 "EventCode": "0xB6", 1731 "EventName": "UNC_M_RD_CAS_RANK6.BANK3", 1732 "PerPkg": "1", 1733 "UMask": "0x3", 1734 "Unit": "iMC" 1735 }, 1736 { 1737 "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", 1738 "Counter": "0,1,2,3", 1739 "EventCode": "0xB6", 1740 "EventName": "UNC_M_RD_CAS_RANK6.BANK4", 1741 "PerPkg": "1", 1742 "UMask": "0x4", 1743 "Unit": "iMC" 1744 }, 1745 { 1746 "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", 1747 "Counter": "0,1,2,3", 1748 "EventCode": "0xB6", 1749 "EventName": "UNC_M_RD_CAS_RANK6.BANK5", 1750 "PerPkg": "1", 1751 "UMask": "0x5", 1752 "Unit": "iMC" 1753 }, 1754 { 1755 "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", 1756 "Counter": "0,1,2,3", 1757 "EventCode": "0xB6", 1758 "EventName": "UNC_M_RD_CAS_RANK6.BANK6", 1759 "PerPkg": "1", 1760 "UMask": "0x6", 1761 "Unit": "iMC" 1762 }, 1763 { 1764 "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", 1765 "Counter": "0,1,2,3", 1766 "EventCode": "0xB6", 1767 "EventName": "UNC_M_RD_CAS_RANK6.BANK7", 1768 "PerPkg": "1", 1769 "UMask": "0x7", 1770 "Unit": "iMC" 1771 }, 1772 { 1773 "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", 1774 "Counter": "0,1,2,3", 1775 "EventCode": "0xB6", 1776 "EventName": "UNC_M_RD_CAS_RANK6.BANK8", 1777 "PerPkg": "1", 1778 "UMask": "0x8", 1779 "Unit": "iMC" 1780 }, 1781 { 1782 "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", 1783 "Counter": "0,1,2,3", 1784 "EventCode": "0xB6", 1785 "EventName": "UNC_M_RD_CAS_RANK6.BANK9", 1786 "PerPkg": "1", 1787 "UMask": "0x9", 1788 "Unit": "iMC" 1789 }, 1790 { 1791 "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", 1792 "Counter": "0,1,2,3", 1793 "EventCode": "0xB6", 1794 "EventName": "UNC_M_RD_CAS_RANK6.BANK10", 1795 "PerPkg": "1", 1796 "UMask": "0xA", 1797 "Unit": "iMC" 1798 }, 1799 { 1800 "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", 1801 "Counter": "0,1,2,3", 1802 "EventCode": "0xB6", 1803 "EventName": "UNC_M_RD_CAS_RANK6.BANK11", 1804 "PerPkg": "1", 1805 "UMask": "0xB", 1806 "Unit": "iMC" 1807 }, 1808 { 1809 "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", 1810 "Counter": "0,1,2,3", 1811 "EventCode": "0xB6", 1812 "EventName": "UNC_M_RD_CAS_RANK6.BANK12", 1813 "PerPkg": "1", 1814 "UMask": "0xC", 1815 "Unit": "iMC" 1816 }, 1817 { 1818 "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", 1819 "Counter": "0,1,2,3", 1820 "EventCode": "0xB6", 1821 "EventName": "UNC_M_RD_CAS_RANK6.BANK13", 1822 "PerPkg": "1", 1823 "UMask": "0xD", 1824 "Unit": "iMC" 1825 }, 1826 { 1827 "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", 1828 "Counter": "0,1,2,3", 1829 "EventCode": "0xB6", 1830 "EventName": "UNC_M_RD_CAS_RANK6.BANK14", 1831 "PerPkg": "1", 1832 "UMask": "0xE", 1833 "Unit": "iMC" 1834 }, 1835 { 1836 "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", 1837 "Counter": "0,1,2,3", 1838 "EventCode": "0xB6", 1839 "EventName": "UNC_M_RD_CAS_RANK6.BANK15", 1840 "PerPkg": "1", 1841 "UMask": "0xF", 1842 "Unit": "iMC" 1843 }, 1844 { 1845 "BriefDescription": "RD_CAS Access to Rank 6; All Banks", 1846 "Counter": "0,1,2,3", 1847 "EventCode": "0xB6", 1848 "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", 1849 "PerPkg": "1", 1850 "UMask": "0x10", 1851 "Unit": "iMC" 1852 }, 1853 { 1854 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)", 1855 "Counter": "0,1,2,3", 1856 "EventCode": "0xB6", 1857 "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", 1858 "PerPkg": "1", 1859 "UMask": "0x11", 1860 "Unit": "iMC" 1861 }, 1862 { 1863 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)", 1864 "Counter": "0,1,2,3", 1865 "EventCode": "0xB6", 1866 "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", 1867 "PerPkg": "1", 1868 "UMask": "0x12", 1869 "Unit": "iMC" 1870 }, 1871 { 1872 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)", 1873 "Counter": "0,1,2,3", 1874 "EventCode": "0xB6", 1875 "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", 1876 "PerPkg": "1", 1877 "UMask": "0x13", 1878 "Unit": "iMC" 1879 }, 1880 { 1881 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)", 1882 "Counter": "0,1,2,3", 1883 "EventCode": "0xB6", 1884 "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", 1885 "PerPkg": "1", 1886 "UMask": "0x14", 1887 "Unit": "iMC" 1888 }, 1889 { 1890 "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", 1891 "Counter": "0,1,2,3", 1892 "EventCode": "0xB7", 1893 "EventName": "UNC_M_RD_CAS_RANK7.BANK0", 1894 "PerPkg": "1", 1895 "Unit": "iMC" 1896 }, 1897 { 1898 "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", 1899 "Counter": "0,1,2,3", 1900 "EventCode": "0xB7", 1901 "EventName": "UNC_M_RD_CAS_RANK7.BANK1", 1902 "PerPkg": "1", 1903 "UMask": "0x1", 1904 "Unit": "iMC" 1905 }, 1906 { 1907 "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", 1908 "Counter": "0,1,2,3", 1909 "EventCode": "0xB7", 1910 "EventName": "UNC_M_RD_CAS_RANK7.BANK2", 1911 "PerPkg": "1", 1912 "UMask": "0x2", 1913 "Unit": "iMC" 1914 }, 1915 { 1916 "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", 1917 "Counter": "0,1,2,3", 1918 "EventCode": "0xB7", 1919 "EventName": "UNC_M_RD_CAS_RANK7.BANK3", 1920 "PerPkg": "1", 1921 "UMask": "0x3", 1922 "Unit": "iMC" 1923 }, 1924 { 1925 "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", 1926 "Counter": "0,1,2,3", 1927 "EventCode": "0xB7", 1928 "EventName": "UNC_M_RD_CAS_RANK7.BANK4", 1929 "PerPkg": "1", 1930 "UMask": "0x4", 1931 "Unit": "iMC" 1932 }, 1933 { 1934 "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", 1935 "Counter": "0,1,2,3", 1936 "EventCode": "0xB7", 1937 "EventName": "UNC_M_RD_CAS_RANK7.BANK5", 1938 "PerPkg": "1", 1939 "UMask": "0x5", 1940 "Unit": "iMC" 1941 }, 1942 { 1943 "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", 1944 "Counter": "0,1,2,3", 1945 "EventCode": "0xB7", 1946 "EventName": "UNC_M_RD_CAS_RANK7.BANK6", 1947 "PerPkg": "1", 1948 "UMask": "0x6", 1949 "Unit": "iMC" 1950 }, 1951 { 1952 "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", 1953 "Counter": "0,1,2,3", 1954 "EventCode": "0xB7", 1955 "EventName": "UNC_M_RD_CAS_RANK7.BANK7", 1956 "PerPkg": "1", 1957 "UMask": "0x7", 1958 "Unit": "iMC" 1959 }, 1960 { 1961 "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", 1962 "Counter": "0,1,2,3", 1963 "EventCode": "0xB7", 1964 "EventName": "UNC_M_RD_CAS_RANK7.BANK8", 1965 "PerPkg": "1", 1966 "UMask": "0x8", 1967 "Unit": "iMC" 1968 }, 1969 { 1970 "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", 1971 "Counter": "0,1,2,3", 1972 "EventCode": "0xB7", 1973 "EventName": "UNC_M_RD_CAS_RANK7.BANK9", 1974 "PerPkg": "1", 1975 "UMask": "0x9", 1976 "Unit": "iMC" 1977 }, 1978 { 1979 "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", 1980 "Counter": "0,1,2,3", 1981 "EventCode": "0xB7", 1982 "EventName": "UNC_M_RD_CAS_RANK7.BANK10", 1983 "PerPkg": "1", 1984 "UMask": "0xA", 1985 "Unit": "iMC" 1986 }, 1987 { 1988 "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", 1989 "Counter": "0,1,2,3", 1990 "EventCode": "0xB7", 1991 "EventName": "UNC_M_RD_CAS_RANK7.BANK11", 1992 "PerPkg": "1", 1993 "UMask": "0xB", 1994 "Unit": "iMC" 1995 }, 1996 { 1997 "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", 1998 "Counter": "0,1,2,3", 1999 "EventCode": "0xB7", 2000 "EventName": "UNC_M_RD_CAS_RANK7.BANK12", 2001 "PerPkg": "1", 2002 "UMask": "0xC", 2003 "Unit": "iMC" 2004 }, 2005 { 2006 "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", 2007 "Counter": "0,1,2,3", 2008 "EventCode": "0xB7", 2009 "EventName": "UNC_M_RD_CAS_RANK7.BANK13", 2010 "PerPkg": "1", 2011 "UMask": "0xD", 2012 "Unit": "iMC" 2013 }, 2014 { 2015 "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", 2016 "Counter": "0,1,2,3", 2017 "EventCode": "0xB7", 2018 "EventName": "UNC_M_RD_CAS_RANK7.BANK14", 2019 "PerPkg": "1", 2020 "UMask": "0xE", 2021 "Unit": "iMC" 2022 }, 2023 { 2024 "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", 2025 "Counter": "0,1,2,3", 2026 "EventCode": "0xB7", 2027 "EventName": "UNC_M_RD_CAS_RANK7.BANK15", 2028 "PerPkg": "1", 2029 "UMask": "0xF", 2030 "Unit": "iMC" 2031 }, 2032 { 2033 "BriefDescription": "RD_CAS Access to Rank 7; All Banks", 2034 "Counter": "0,1,2,3", 2035 "EventCode": "0xB7", 2036 "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", 2037 "PerPkg": "1", 2038 "UMask": "0x10", 2039 "Unit": "iMC" 2040 }, 2041 { 2042 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)", 2043 "Counter": "0,1,2,3", 2044 "EventCode": "0xB7", 2045 "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", 2046 "PerPkg": "1", 2047 "UMask": "0x11", 2048 "Unit": "iMC" 2049 }, 2050 { 2051 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)", 2052 "Counter": "0,1,2,3", 2053 "EventCode": "0xB7", 2054 "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", 2055 "PerPkg": "1", 2056 "UMask": "0x12", 2057 "Unit": "iMC" 2058 }, 2059 { 2060 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)", 2061 "Counter": "0,1,2,3", 2062 "EventCode": "0xB7", 2063 "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", 2064 "PerPkg": "1", 2065 "UMask": "0x13", 2066 "Unit": "iMC" 2067 }, 2068 { 2069 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)", 2070 "Counter": "0,1,2,3", 2071 "EventCode": "0xB7", 2072 "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", 2073 "PerPkg": "1", 2074 "UMask": "0x14", 2075 "Unit": "iMC" 2076 }, 2077 { 2078 "BriefDescription": "Read Pending Queue Full Cycles", 2079 "Counter": "0,1,2,3", 2080 "EventCode": "0x12", 2081 "EventName": "UNC_M_RPQ_CYCLES_FULL", 2082 "PerPkg": "1", 2083 "Unit": "iMC" 2084 }, 2085 { 2086 "BriefDescription": "Read Pending Queue Not Empty", 2087 "Counter": "0,1,2,3", 2088 "EventCode": "0x11", 2089 "EventName": "UNC_M_RPQ_CYCLES_NE", 2090 "PerPkg": "1", 2091 "Unit": "iMC" 2092 }, 2093 { 2094 "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter", 2095 "Counter": "0,1,2,3", 2096 "EventCode": "0xC0", 2097 "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", 2098 "PerPkg": "1", 2099 "UMask": "0x1", 2100 "Unit": "iMC" 2101 }, 2102 { 2103 "BriefDescription": "Transition from WMM to RMM because of low threshold", 2104 "Counter": "0,1,2,3", 2105 "EventCode": "0xC0", 2106 "EventName": "UNC_M_WMM_TO_RMM.STARVE", 2107 "PerPkg": "1", 2108 "UMask": "0x2", 2109 "Unit": "iMC" 2110 }, 2111 { 2112 "BriefDescription": "Transition from WMM to RMM because of low threshold", 2113 "Counter": "0,1,2,3", 2114 "EventCode": "0xC0", 2115 "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", 2116 "PerPkg": "1", 2117 "UMask": "0x4", 2118 "Unit": "iMC" 2119 }, 2120 { 2121 "BriefDescription": "Write Pending Queue Full Cycles", 2122 "Counter": "0,1,2,3", 2123 "EventCode": "0x22", 2124 "EventName": "UNC_M_WPQ_CYCLES_FULL", 2125 "PerPkg": "1", 2126 "Unit": "iMC" 2127 }, 2128 { 2129 "BriefDescription": "Write Pending Queue Not Empty", 2130 "Counter": "0,1,2,3", 2131 "EventCode": "0x21", 2132 "EventName": "UNC_M_WPQ_CYCLES_NE", 2133 "PerPkg": "1", 2134 "Unit": "iMC" 2135 }, 2136 { 2137 "BriefDescription": "Write Pending Queue CAM Match", 2138 "Counter": "0,1,2,3", 2139 "EventCode": "0x23", 2140 "EventName": "UNC_M_WPQ_READ_HIT", 2141 "PerPkg": "1", 2142 "Unit": "iMC" 2143 }, 2144 { 2145 "BriefDescription": "Write Pending Queue CAM Match", 2146 "Counter": "0,1,2,3", 2147 "EventCode": "0x24", 2148 "EventName": "UNC_M_WPQ_WRITE_HIT", 2149 "PerPkg": "1", 2150 "Unit": "iMC" 2151 }, 2152 { 2153 "BriefDescription": "Not getting the requested Major Mode", 2154 "Counter": "0,1,2,3", 2155 "EventCode": "0xC1", 2156 "EventName": "UNC_M_WRONG_MM", 2157 "PerPkg": "1", 2158 "Unit": "iMC" 2159 }, 2160 { 2161 "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", 2162 "Counter": "0,1,2,3", 2163 "EventCode": "0xB8", 2164 "EventName": "UNC_M_WR_CAS_RANK0.BANK0", 2165 "PerPkg": "1", 2166 "Unit": "iMC" 2167 }, 2168 { 2169 "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", 2170 "Counter": "0,1,2,3", 2171 "EventCode": "0xB8", 2172 "EventName": "UNC_M_WR_CAS_RANK0.BANK1", 2173 "PerPkg": "1", 2174 "UMask": "0x1", 2175 "Unit": "iMC" 2176 }, 2177 { 2178 "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", 2179 "Counter": "0,1,2,3", 2180 "EventCode": "0xB8", 2181 "EventName": "UNC_M_WR_CAS_RANK0.BANK2", 2182 "PerPkg": "1", 2183 "UMask": "0x2", 2184 "Unit": "iMC" 2185 }, 2186 { 2187 "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", 2188 "Counter": "0,1,2,3", 2189 "EventCode": "0xB8", 2190 "EventName": "UNC_M_WR_CAS_RANK0.BANK3", 2191 "PerPkg": "1", 2192 "UMask": "0x3", 2193 "Unit": "iMC" 2194 }, 2195 { 2196 "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", 2197 "Counter": "0,1,2,3", 2198 "EventCode": "0xB8", 2199 "EventName": "UNC_M_WR_CAS_RANK0.BANK4", 2200 "PerPkg": "1", 2201 "UMask": "0x4", 2202 "Unit": "iMC" 2203 }, 2204 { 2205 "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", 2206 "Counter": "0,1,2,3", 2207 "EventCode": "0xB8", 2208 "EventName": "UNC_M_WR_CAS_RANK0.BANK5", 2209 "PerPkg": "1", 2210 "UMask": "0x5", 2211 "Unit": "iMC" 2212 }, 2213 { 2214 "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", 2215 "Counter": "0,1,2,3", 2216 "EventCode": "0xB8", 2217 "EventName": "UNC_M_WR_CAS_RANK0.BANK6", 2218 "PerPkg": "1", 2219 "UMask": "0x6", 2220 "Unit": "iMC" 2221 }, 2222 { 2223 "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", 2224 "Counter": "0,1,2,3", 2225 "EventCode": "0xB8", 2226 "EventName": "UNC_M_WR_CAS_RANK0.BANK7", 2227 "PerPkg": "1", 2228 "UMask": "0x7", 2229 "Unit": "iMC" 2230 }, 2231 { 2232 "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", 2233 "Counter": "0,1,2,3", 2234 "EventCode": "0xB8", 2235 "EventName": "UNC_M_WR_CAS_RANK0.BANK8", 2236 "PerPkg": "1", 2237 "UMask": "0x8", 2238 "Unit": "iMC" 2239 }, 2240 { 2241 "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", 2242 "Counter": "0,1,2,3", 2243 "EventCode": "0xB8", 2244 "EventName": "UNC_M_WR_CAS_RANK0.BANK9", 2245 "PerPkg": "1", 2246 "UMask": "0x9", 2247 "Unit": "iMC" 2248 }, 2249 { 2250 "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", 2251 "Counter": "0,1,2,3", 2252 "EventCode": "0xB8", 2253 "EventName": "UNC_M_WR_CAS_RANK0.BANK10", 2254 "PerPkg": "1", 2255 "UMask": "0xA", 2256 "Unit": "iMC" 2257 }, 2258 { 2259 "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", 2260 "Counter": "0,1,2,3", 2261 "EventCode": "0xB8", 2262 "EventName": "UNC_M_WR_CAS_RANK0.BANK11", 2263 "PerPkg": "1", 2264 "UMask": "0xB", 2265 "Unit": "iMC" 2266 }, 2267 { 2268 "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", 2269 "Counter": "0,1,2,3", 2270 "EventCode": "0xB8", 2271 "EventName": "UNC_M_WR_CAS_RANK0.BANK12", 2272 "PerPkg": "1", 2273 "UMask": "0xC", 2274 "Unit": "iMC" 2275 }, 2276 { 2277 "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", 2278 "Counter": "0,1,2,3", 2279 "EventCode": "0xB8", 2280 "EventName": "UNC_M_WR_CAS_RANK0.BANK13", 2281 "PerPkg": "1", 2282 "UMask": "0xD", 2283 "Unit": "iMC" 2284 }, 2285 { 2286 "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", 2287 "Counter": "0,1,2,3", 2288 "EventCode": "0xB8", 2289 "EventName": "UNC_M_WR_CAS_RANK0.BANK14", 2290 "PerPkg": "1", 2291 "UMask": "0xE", 2292 "Unit": "iMC" 2293 }, 2294 { 2295 "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", 2296 "Counter": "0,1,2,3", 2297 "EventCode": "0xB8", 2298 "EventName": "UNC_M_WR_CAS_RANK0.BANK15", 2299 "PerPkg": "1", 2300 "UMask": "0xF", 2301 "Unit": "iMC" 2302 }, 2303 { 2304 "BriefDescription": "WR_CAS Access to Rank 0; All Banks", 2305 "Counter": "0,1,2,3", 2306 "EventCode": "0xB8", 2307 "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", 2308 "PerPkg": "1", 2309 "UMask": "0x10", 2310 "Unit": "iMC" 2311 }, 2312 { 2313 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)", 2314 "Counter": "0,1,2,3", 2315 "EventCode": "0xB8", 2316 "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", 2317 "PerPkg": "1", 2318 "UMask": "0x11", 2319 "Unit": "iMC" 2320 }, 2321 { 2322 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)", 2323 "Counter": "0,1,2,3", 2324 "EventCode": "0xB8", 2325 "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", 2326 "PerPkg": "1", 2327 "UMask": "0x12", 2328 "Unit": "iMC" 2329 }, 2330 { 2331 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)", 2332 "Counter": "0,1,2,3", 2333 "EventCode": "0xB8", 2334 "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", 2335 "PerPkg": "1", 2336 "UMask": "0x13", 2337 "Unit": "iMC" 2338 }, 2339 { 2340 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)", 2341 "Counter": "0,1,2,3", 2342 "EventCode": "0xB8", 2343 "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", 2344 "PerPkg": "1", 2345 "UMask": "0x14", 2346 "Unit": "iMC" 2347 }, 2348 { 2349 "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", 2350 "Counter": "0,1,2,3", 2351 "EventCode": "0xB9", 2352 "EventName": "UNC_M_WR_CAS_RANK1.BANK0", 2353 "PerPkg": "1", 2354 "Unit": "iMC" 2355 }, 2356 { 2357 "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", 2358 "Counter": "0,1,2,3", 2359 "EventCode": "0xB9", 2360 "EventName": "UNC_M_WR_CAS_RANK1.BANK1", 2361 "PerPkg": "1", 2362 "UMask": "0x1", 2363 "Unit": "iMC" 2364 }, 2365 { 2366 "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", 2367 "Counter": "0,1,2,3", 2368 "EventCode": "0xB9", 2369 "EventName": "UNC_M_WR_CAS_RANK1.BANK2", 2370 "PerPkg": "1", 2371 "UMask": "0x2", 2372 "Unit": "iMC" 2373 }, 2374 { 2375 "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", 2376 "Counter": "0,1,2,3", 2377 "EventCode": "0xB9", 2378 "EventName": "UNC_M_WR_CAS_RANK1.BANK3", 2379 "PerPkg": "1", 2380 "UMask": "0x3", 2381 "Unit": "iMC" 2382 }, 2383 { 2384 "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", 2385 "Counter": "0,1,2,3", 2386 "EventCode": "0xB9", 2387 "EventName": "UNC_M_WR_CAS_RANK1.BANK4", 2388 "PerPkg": "1", 2389 "UMask": "0x4", 2390 "Unit": "iMC" 2391 }, 2392 { 2393 "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", 2394 "Counter": "0,1,2,3", 2395 "EventCode": "0xB9", 2396 "EventName": "UNC_M_WR_CAS_RANK1.BANK5", 2397 "PerPkg": "1", 2398 "UMask": "0x5", 2399 "Unit": "iMC" 2400 }, 2401 { 2402 "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", 2403 "Counter": "0,1,2,3", 2404 "EventCode": "0xB9", 2405 "EventName": "UNC_M_WR_CAS_RANK1.BANK6", 2406 "PerPkg": "1", 2407 "UMask": "0x6", 2408 "Unit": "iMC" 2409 }, 2410 { 2411 "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", 2412 "Counter": "0,1,2,3", 2413 "EventCode": "0xB9", 2414 "EventName": "UNC_M_WR_CAS_RANK1.BANK7", 2415 "PerPkg": "1", 2416 "UMask": "0x7", 2417 "Unit": "iMC" 2418 }, 2419 { 2420 "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", 2421 "Counter": "0,1,2,3", 2422 "EventCode": "0xB9", 2423 "EventName": "UNC_M_WR_CAS_RANK1.BANK8", 2424 "PerPkg": "1", 2425 "UMask": "0x8", 2426 "Unit": "iMC" 2427 }, 2428 { 2429 "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", 2430 "Counter": "0,1,2,3", 2431 "EventCode": "0xB9", 2432 "EventName": "UNC_M_WR_CAS_RANK1.BANK9", 2433 "PerPkg": "1", 2434 "UMask": "0x9", 2435 "Unit": "iMC" 2436 }, 2437 { 2438 "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", 2439 "Counter": "0,1,2,3", 2440 "EventCode": "0xB9", 2441 "EventName": "UNC_M_WR_CAS_RANK1.BANK10", 2442 "PerPkg": "1", 2443 "UMask": "0xA", 2444 "Unit": "iMC" 2445 }, 2446 { 2447 "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", 2448 "Counter": "0,1,2,3", 2449 "EventCode": "0xB9", 2450 "EventName": "UNC_M_WR_CAS_RANK1.BANK11", 2451 "PerPkg": "1", 2452 "UMask": "0xB", 2453 "Unit": "iMC" 2454 }, 2455 { 2456 "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", 2457 "Counter": "0,1,2,3", 2458 "EventCode": "0xB9", 2459 "EventName": "UNC_M_WR_CAS_RANK1.BANK12", 2460 "PerPkg": "1", 2461 "UMask": "0xC", 2462 "Unit": "iMC" 2463 }, 2464 { 2465 "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", 2466 "Counter": "0,1,2,3", 2467 "EventCode": "0xB9", 2468 "EventName": "UNC_M_WR_CAS_RANK1.BANK13", 2469 "PerPkg": "1", 2470 "UMask": "0xD", 2471 "Unit": "iMC" 2472 }, 2473 { 2474 "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", 2475 "Counter": "0,1,2,3", 2476 "EventCode": "0xB9", 2477 "EventName": "UNC_M_WR_CAS_RANK1.BANK14", 2478 "PerPkg": "1", 2479 "UMask": "0xE", 2480 "Unit": "iMC" 2481 }, 2482 { 2483 "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", 2484 "Counter": "0,1,2,3", 2485 "EventCode": "0xB9", 2486 "EventName": "UNC_M_WR_CAS_RANK1.BANK15", 2487 "PerPkg": "1", 2488 "UMask": "0xF", 2489 "Unit": "iMC" 2490 }, 2491 { 2492 "BriefDescription": "WR_CAS Access to Rank 1; All Banks", 2493 "Counter": "0,1,2,3", 2494 "EventCode": "0xB9", 2495 "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", 2496 "PerPkg": "1", 2497 "UMask": "0x10", 2498 "Unit": "iMC" 2499 }, 2500 { 2501 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)", 2502 "Counter": "0,1,2,3", 2503 "EventCode": "0xB9", 2504 "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", 2505 "PerPkg": "1", 2506 "UMask": "0x11", 2507 "Unit": "iMC" 2508 }, 2509 { 2510 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)", 2511 "Counter": "0,1,2,3", 2512 "EventCode": "0xB9", 2513 "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", 2514 "PerPkg": "1", 2515 "UMask": "0x12", 2516 "Unit": "iMC" 2517 }, 2518 { 2519 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)", 2520 "Counter": "0,1,2,3", 2521 "EventCode": "0xB9", 2522 "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", 2523 "PerPkg": "1", 2524 "UMask": "0x13", 2525 "Unit": "iMC" 2526 }, 2527 { 2528 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)", 2529 "Counter": "0,1,2,3", 2530 "EventCode": "0xB9", 2531 "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", 2532 "PerPkg": "1", 2533 "UMask": "0x14", 2534 "Unit": "iMC" 2535 }, 2536 { 2537 "BriefDescription": "WR_CAS Access to Rank 2; Bank 0", 2538 "Counter": "0,1,2,3", 2539 "EventCode": "0xBA", 2540 "EventName": "UNC_M_WR_CAS_RANK2.BANK0", 2541 "PerPkg": "1", 2542 "Unit": "iMC" 2543 }, 2544 { 2545 "BriefDescription": "WR_CAS Access to Rank 2; Bank 1", 2546 "Counter": "0,1,2,3", 2547 "EventCode": "0xBA", 2548 "EventName": "UNC_M_WR_CAS_RANK2.BANK1", 2549 "PerPkg": "1", 2550 "UMask": "0x1", 2551 "Unit": "iMC" 2552 }, 2553 { 2554 "BriefDescription": "WR_CAS Access to Rank 2; Bank 2", 2555 "Counter": "0,1,2,3", 2556 "EventCode": "0xBA", 2557 "EventName": "UNC_M_WR_CAS_RANK2.BANK2", 2558 "PerPkg": "1", 2559 "UMask": "0x2", 2560 "Unit": "iMC" 2561 }, 2562 { 2563 "BriefDescription": "WR_CAS Access to Rank 2; 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