1[
2    {
3        "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
4        "Counter": "0,1,2,3",
5        "CounterHTOff": "0,1,2,3,4,5,6,7",
6        "EventCode": "0x28",
7        "EventName": "CORE_POWER.THROTTLE",
8        "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
9        "SampleAfterValue": "200003",
10        "UMask": "0x40"
11    },
12    {
13        "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
14        "Counter": "0,1,2,3",
15        "CounterHTOff": "0,1,2,3,4,5,6,7",
16        "EventCode": "0xFE",
17        "EventName": "IDI_MISC.WB_DOWNGRADE",
18        "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
19        "SampleAfterValue": "100003",
20        "UMask": "0x4"
21    },
22    {
23        "BriefDescription": "Number of PREFETCHW instructions executed.",
24        "Counter": "0,1,2,3",
25        "CounterHTOff": "0,1,2,3,4,5,6,7",
26        "EventCode": "0x32",
27        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
28        "SampleAfterValue": "2000003",
29        "UMask": "0x8"
30    },
31    {
32        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
33        "Counter": "0,1,2,3",
34        "CounterHTOff": "0,1,2,3,4,5,6,7",
35        "EventCode": "0x28",
36        "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
37        "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
38        "SampleAfterValue": "200003",
39        "UMask": "0x7"
40    },
41    {
42        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
43        "Counter": "0,1,2,3",
44        "CounterHTOff": "0,1,2,3,4,5,6,7",
45        "EventCode": "0x28",
46        "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
47        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
48        "SampleAfterValue": "200003",
49        "UMask": "0x18"
50    },
51    {
52        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
53        "Counter": "0,1,2,3",
54        "CounterHTOff": "0,1,2,3,4,5,6,7",
55        "EventCode": "0x32",
56        "EventName": "SW_PREFETCH_ACCESS.T0",
57        "SampleAfterValue": "2000003",
58        "UMask": "0x2"
59    },
60    {
61        "BriefDescription": "Number of hardware interrupts received by the processor.",
62        "Counter": "0,1,2,3",
63        "CounterHTOff": "0,1,2,3,4,5,6,7",
64        "EventCode": "0xCB",
65        "EventName": "HW_INTERRUPTS.RECEIVED",
66        "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
67        "SampleAfterValue": "203",
68        "UMask": "0x1"
69    },
70    {
71        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
72        "Counter": "0,1,2,3",
73        "CounterHTOff": "0,1,2,3,4,5,6,7",
74        "EventCode": "0x28",
75        "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
76        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructions.",
77        "SampleAfterValue": "200003",
78        "UMask": "0x20"
79    },
80    {
81        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
82        "Counter": "0,1,2,3",
83        "CounterHTOff": "0,1,2,3,4,5,6,7",
84        "EventCode": "0x32",
85        "EventName": "SW_PREFETCH_ACCESS.NTA",
86        "SampleAfterValue": "2000003",
87        "UMask": "0x1"
88    },
89    {
90        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
91        "Counter": "0,1,2,3",
92        "CounterHTOff": "0,1,2,3,4,5,6,7",
93        "EventCode": "0x32",
94        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
95        "SampleAfterValue": "2000003",
96        "UMask": "0x4"
97    },
98    {
99        "Counter": "0,1,2,3",
100        "CounterHTOff": "0,1,2,3,4,5,6,7",
101        "EventCode": "0x09",
102        "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
103        "SampleAfterValue": "2000003",
104        "UMask": "0x1"
105    },
106    {
107        "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
108        "Counter": "0,1,2,3",
109        "CounterHTOff": "0,1,2,3,4,5,6,7",
110        "EventCode": "0xFE",
111        "EventName": "IDI_MISC.WB_UPGRADE",
112        "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
113        "SampleAfterValue": "100003",
114        "UMask": "0x2"
115    }
116]