1[ 2 { 3 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x28", 7 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 8 "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 9 "SampleAfterValue": "200003", 10 "UMask": "0x7" 11 }, 12 { 13 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "EventCode": "0x28", 17 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 18 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 19 "SampleAfterValue": "200003", 20 "UMask": "0x18" 21 }, 22 { 23 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 24 "Counter": "0,1,2,3", 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "EventCode": "0x28", 27 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 28 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", 29 "SampleAfterValue": "200003", 30 "UMask": "0x20" 31 }, 32 { 33 "BriefDescription": "Core cycles the core was throttled due to a pending power level request.", 34 "Counter": "0,1,2,3", 35 "CounterHTOff": "0,1,2,3,4,5,6,7", 36 "EventCode": "0x28", 37 "EventName": "CORE_POWER.THROTTLE", 38 "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.", 39 "SampleAfterValue": "200003", 40 "UMask": "0x40" 41 }, 42 { 43 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", 44 "Counter": "0,1,2,3", 45 "CounterHTOff": "0,1,2,3,4,5,6,7", 46 "EventCode": "0xEF", 47 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", 48 "SampleAfterValue": "2000003", 49 "UMask": "0x20" 50 }, 51 { 52 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", 53 "Counter": "0,1,2,3", 54 "CounterHTOff": "0,1,2,3,4,5,6,7", 55 "EventCode": "0xEF", 56 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", 57 "SampleAfterValue": "2000003", 58 "UMask": "0x10" 59 }, 60 { 61 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", 62 "Counter": "0,1,2,3", 63 "CounterHTOff": "0,1,2,3,4,5,6,7", 64 "EventCode": "0xEF", 65 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", 66 "SampleAfterValue": "2000003", 67 "UMask": "0x2" 68 }, 69 { 70 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", 71 "Counter": "0,1,2,3", 72 "CounterHTOff": "0,1,2,3,4,5,6,7", 73 "EventCode": "0xEF", 74 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", 75 "SampleAfterValue": "2000003", 76 "UMask": "0x1" 77 }, 78 { 79 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", 80 "Counter": "0,1,2,3", 81 "CounterHTOff": "0,1,2,3,4,5,6,7", 82 "EventCode": "0xEF", 83 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", 84 "SampleAfterValue": "2000003", 85 "UMask": "0x40" 86 }, 87 { 88 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", 89 "Counter": "0,1,2,3", 90 "CounterHTOff": "0,1,2,3,4,5,6,7", 91 "EventCode": "0xEF", 92 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", 93 "SampleAfterValue": "2000003", 94 "UMask": "0x8" 95 }, 96 { 97 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", 98 "Counter": "0,1,2,3", 99 "CounterHTOff": "0,1,2,3,4,5,6,7", 100 "EventCode": "0xEF", 101 "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", 102 "SampleAfterValue": "2000003", 103 "UMask": "0x4" 104 }, 105 { 106 "BriefDescription": "Number of hardware interrupts received by the processor.", 107 "Counter": "0,1,2,3", 108 "CounterHTOff": "0,1,2,3,4,5,6,7", 109 "EventCode": "0xCB", 110 "EventName": "HW_INTERRUPTS.RECEIVED", 111 "PublicDescription": "Counts the number of hardware interruptions received by the processor.", 112 "SampleAfterValue": "203", 113 "UMask": "0x1" 114 }, 115 { 116 "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", 117 "Counter": "0,1,2,3", 118 "CounterHTOff": "0,1,2,3,4,5,6,7", 119 "EventCode": "0xFE", 120 "EventName": "IDI_MISC.WB_DOWNGRADE", 121 "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", 122 "SampleAfterValue": "100003", 123 "UMask": "0x4" 124 }, 125 { 126 "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", 127 "Counter": "0,1,2,3", 128 "CounterHTOff": "0,1,2,3,4,5,6,7", 129 "EventCode": "0xFE", 130 "EventName": "IDI_MISC.WB_UPGRADE", 131 "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", 132 "SampleAfterValue": "100003", 133 "UMask": "0x2" 134 }, 135 { 136 "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", 137 "Counter": "0,1,2,3", 138 "CounterHTOff": "0,1,2,3,4,5,6,7", 139 "EventCode": "0x09", 140 "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", 141 "SampleAfterValue": "2000003", 142 "UMask": "0x1" 143 } 144] 145