1[ 2 { 3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4 "CounterMask": "2", 5 "EventCode": "0xA3", 6 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 7 "SampleAfterValue": "2000003", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 12 "CounterMask": "6", 13 "EventCode": "0xA3", 14 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 15 "SampleAfterValue": "2000003", 16 "UMask": "0x6" 17 }, 18 { 19 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 20 "EventCode": "0xC8", 21 "EventName": "HLE_RETIRED.ABORTED", 22 "PEBS": "1", 23 "PublicDescription": "Number of times HLE abort was triggered.", 24 "SampleAfterValue": "2000003", 25 "UMask": "0x4" 26 }, 27 { 28 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 29 "EventCode": "0xC8", 30 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 31 "SampleAfterValue": "2000003", 32 "UMask": "0x80" 33 }, 34 { 35 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 36 "EventCode": "0xC8", 37 "EventName": "HLE_RETIRED.ABORTED_MEM", 38 "SampleAfterValue": "2000003", 39 "UMask": "0x8" 40 }, 41 { 42 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 43 "EventCode": "0xC8", 44 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 45 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 46 "SampleAfterValue": "2000003", 47 "UMask": "0x40" 48 }, 49 { 50 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 51 "EventCode": "0xC8", 52 "EventName": "HLE_RETIRED.ABORTED_TIMER", 53 "SampleAfterValue": "2000003", 54 "UMask": "0x10" 55 }, 56 { 57 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 58 "EventCode": "0xC8", 59 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 60 "SampleAfterValue": "2000003", 61 "UMask": "0x20" 62 }, 63 { 64 "BriefDescription": "Number of times an HLE execution successfully committed", 65 "EventCode": "0xC8", 66 "EventName": "HLE_RETIRED.COMMIT", 67 "PublicDescription": "Number of times HLE commit succeeded.", 68 "SampleAfterValue": "2000003", 69 "UMask": "0x2" 70 }, 71 { 72 "BriefDescription": "Number of times an HLE execution started.", 73 "EventCode": "0xC8", 74 "EventName": "HLE_RETIRED.START", 75 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 76 "SampleAfterValue": "2000003", 77 "UMask": "0x1" 78 }, 79 { 80 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 81 "Errata": "SKL089", 82 "EventCode": "0xC3", 83 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 84 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 85 "SampleAfterValue": "100003", 86 "UMask": "0x2" 87 }, 88 { 89 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 90 "Data_LA": "1", 91 "EventCode": "0xcd", 92 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 93 "MSRIndex": "0x3F6", 94 "MSRValue": "0x80", 95 "PEBS": "2", 96 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 97 "SampleAfterValue": "1009", 98 "UMask": "0x1" 99 }, 100 { 101 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 102 "Data_LA": "1", 103 "EventCode": "0xcd", 104 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 105 "MSRIndex": "0x3F6", 106 "MSRValue": "0x10", 107 "PEBS": "2", 108 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 109 "SampleAfterValue": "20011", 110 "UMask": "0x1" 111 }, 112 { 113 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 114 "Data_LA": "1", 115 "EventCode": "0xcd", 116 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 117 "MSRIndex": "0x3F6", 118 "MSRValue": "0x100", 119 "PEBS": "2", 120 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 121 "SampleAfterValue": "503", 122 "UMask": "0x1" 123 }, 124 { 125 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 126 "Data_LA": "1", 127 "EventCode": "0xcd", 128 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 129 "MSRIndex": "0x3F6", 130 "MSRValue": "0x20", 131 "PEBS": "2", 132 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 133 "SampleAfterValue": "100007", 134 "UMask": "0x1" 135 }, 136 { 137 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 138 "Data_LA": "1", 139 "EventCode": "0xcd", 140 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 141 "MSRIndex": "0x3F6", 142 "MSRValue": "0x4", 143 "PEBS": "2", 144 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 145 "SampleAfterValue": "100003", 146 "UMask": "0x1" 147 }, 148 { 149 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 150 "Data_LA": "1", 151 "EventCode": "0xcd", 152 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 153 "MSRIndex": "0x3F6", 154 "MSRValue": "0x200", 155 "PEBS": "2", 156 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 157 "SampleAfterValue": "101", 158 "UMask": "0x1" 159 }, 160 { 161 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 162 "Data_LA": "1", 163 "EventCode": "0xcd", 164 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 165 "MSRIndex": "0x3F6", 166 "MSRValue": "0x40", 167 "PEBS": "2", 168 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 169 "SampleAfterValue": "2003", 170 "UMask": "0x1" 171 }, 172 { 173 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 174 "Data_LA": "1", 175 "EventCode": "0xcd", 176 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 177 "MSRIndex": "0x3F6", 178 "MSRValue": "0x8", 179 "PEBS": "2", 180 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 181 "SampleAfterValue": "50021", 182 "UMask": "0x1" 183 }, 184 { 185 "BriefDescription": "Demand Data Read requests who miss L3 cache", 186 "EventCode": "0xB0", 187 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 188 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 189 "SampleAfterValue": "100003", 190 "UMask": "0x10" 191 }, 192 { 193 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 194 "CounterMask": "1", 195 "EventCode": "0x60", 196 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 197 "SampleAfterValue": "2000003", 198 "UMask": "0x10" 199 }, 200 { 201 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 202 "EventCode": "0x60", 203 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 204 "SampleAfterValue": "2000003", 205 "UMask": "0x10" 206 }, 207 { 208 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 209 "CounterMask": "6", 210 "EventCode": "0x60", 211 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 212 "SampleAfterValue": "2000003", 213 "UMask": "0x10" 214 }, 215 { 216 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 217 "EventCode": "0xB7, 0xBB", 218 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 219 "MSRIndex": "0x1a6,0x1a7", 220 "MSRValue": "0x3FBC000491", 221 "SampleAfterValue": "100003", 222 "UMask": "0x1" 223 }, 224 { 225 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 226 "EventCode": "0xB7, 0xBB", 227 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 228 "MSRIndex": "0x1a6,0x1a7", 229 "MSRValue": "0x103FC00491", 230 "SampleAfterValue": "100003", 231 "UMask": "0x1" 232 }, 233 { 234 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 235 "EventCode": "0xB7, 0xBB", 236 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 237 "MSRIndex": "0x1a6,0x1a7", 238 "MSRValue": "0x83FC00491", 239 "SampleAfterValue": "100003", 240 "UMask": "0x1" 241 }, 242 { 243 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 244 "EventCode": "0xB7, 0xBB", 245 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 246 "MSRIndex": "0x1a6,0x1a7", 247 "MSRValue": "0x63FC00491", 248 "SampleAfterValue": "100003", 249 "UMask": "0x1" 250 }, 251 { 252 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", 253 "EventCode": "0xB7, 0xBB", 254 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 255 "MSRIndex": "0x1a6,0x1a7", 256 "MSRValue": "0x604000491", 257 "SampleAfterValue": "100003", 258 "UMask": "0x1" 259 }, 260 { 261 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", 262 "EventCode": "0xB7, 0xBB", 263 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 264 "MSRIndex": "0x1a6,0x1a7", 265 "MSRValue": "0x63B800491", 266 "SampleAfterValue": "100003", 267 "UMask": "0x1" 268 }, 269 { 270 "BriefDescription": "Counts all prefetch data reads that miss in the L3.", 271 "EventCode": "0xB7, 0xBB", 272 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 273 "MSRIndex": "0x1a6,0x1a7", 274 "MSRValue": "0x3FBC000490", 275 "SampleAfterValue": "100003", 276 "UMask": "0x1" 277 }, 278 { 279 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 280 "EventCode": "0xB7, 0xBB", 281 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 282 "MSRIndex": "0x1a6,0x1a7", 283 "MSRValue": "0x103FC00490", 284 "SampleAfterValue": "100003", 285 "UMask": "0x1" 286 }, 287 { 288 "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 289 "EventCode": "0xB7, 0xBB", 290 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 291 "MSRIndex": "0x1a6,0x1a7", 292 "MSRValue": "0x83FC00490", 293 "SampleAfterValue": "100003", 294 "UMask": "0x1" 295 }, 296 { 297 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 298 "EventCode": "0xB7, 0xBB", 299 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 300 "MSRIndex": "0x1a6,0x1a7", 301 "MSRValue": "0x63FC00490", 302 "SampleAfterValue": "100003", 303 "UMask": "0x1" 304 }, 305 { 306 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", 307 "EventCode": "0xB7, 0xBB", 308 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 309 "MSRIndex": "0x1a6,0x1a7", 310 "MSRValue": "0x604000490", 311 "SampleAfterValue": "100003", 312 "UMask": "0x1" 313 }, 314 { 315 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", 316 "EventCode": "0xB7, 0xBB", 317 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 318 "MSRIndex": "0x1a6,0x1a7", 319 "MSRValue": "0x63B800490", 320 "SampleAfterValue": "100003", 321 "UMask": "0x1" 322 }, 323 { 324 "BriefDescription": "Counts prefetch RFOs that miss in the L3.", 325 "EventCode": "0xB7, 0xBB", 326 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 327 "MSRIndex": "0x1a6,0x1a7", 328 "MSRValue": "0x3FBC000120", 329 "SampleAfterValue": "100003", 330 "UMask": "0x1" 331 }, 332 { 333 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 334 "EventCode": "0xB7, 0xBB", 335 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 336 "MSRIndex": "0x1a6,0x1a7", 337 "MSRValue": "0x103FC00120", 338 "SampleAfterValue": "100003", 339 "UMask": "0x1" 340 }, 341 { 342 "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 343 "EventCode": "0xB7, 0xBB", 344 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 345 "MSRIndex": "0x1a6,0x1a7", 346 "MSRValue": "0x83FC00120", 347 "SampleAfterValue": "100003", 348 "UMask": "0x1" 349 }, 350 { 351 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 352 "EventCode": "0xB7, 0xBB", 353 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 354 "MSRIndex": "0x1a6,0x1a7", 355 "MSRValue": "0x63FC00120", 356 "SampleAfterValue": "100003", 357 "UMask": "0x1" 358 }, 359 { 360 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", 361 "EventCode": "0xB7, 0xBB", 362 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 363 "MSRIndex": "0x1a6,0x1a7", 364 "MSRValue": "0x604000120", 365 "SampleAfterValue": "100003", 366 "UMask": "0x1" 367 }, 368 { 369 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", 370 "EventCode": "0xB7, 0xBB", 371 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 372 "MSRIndex": "0x1a6,0x1a7", 373 "MSRValue": "0x63B800120", 374 "SampleAfterValue": "100003", 375 "UMask": "0x1" 376 }, 377 { 378 "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", 379 "EventCode": "0xB7, 0xBB", 380 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", 381 "MSRIndex": "0x1a6,0x1a7", 382 "MSRValue": "0x3FBC000122", 383 "SampleAfterValue": "100003", 384 "UMask": "0x1" 385 }, 386 { 387 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 388 "EventCode": "0xB7, 0xBB", 389 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", 390 "MSRIndex": "0x1a6,0x1a7", 391 "MSRValue": "0x103FC00122", 392 "SampleAfterValue": "100003", 393 "UMask": "0x1" 394 }, 395 { 396 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 397 "EventCode": "0xB7, 0xBB", 398 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 399 "MSRIndex": "0x1a6,0x1a7", 400 "MSRValue": "0x83FC00122", 401 "SampleAfterValue": "100003", 402 "UMask": "0x1" 403 }, 404 { 405 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 406 "EventCode": "0xB7, 0xBB", 407 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 408 "MSRIndex": "0x1a6,0x1a7", 409 "MSRValue": "0x63FC00122", 410 "SampleAfterValue": "100003", 411 "UMask": "0x1" 412 }, 413 { 414 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", 415 "EventCode": "0xB7, 0xBB", 416 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 417 "MSRIndex": "0x1a6,0x1a7", 418 "MSRValue": "0x604000122", 419 "SampleAfterValue": "100003", 420 "UMask": "0x1" 421 }, 422 { 423 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", 424 "EventCode": "0xB7, 0xBB", 425 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 426 "MSRIndex": "0x1a6,0x1a7", 427 "MSRValue": "0x63B800122", 428 "SampleAfterValue": "100003", 429 "UMask": "0x1" 430 }, 431 { 432 "BriefDescription": "Counts all demand code reads that miss in the L3.", 433 "EventCode": "0xB7, 0xBB", 434 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 435 "MSRIndex": "0x1a6,0x1a7", 436 "MSRValue": "0x3FBC000004", 437 "SampleAfterValue": "100003", 438 "UMask": "0x1" 439 }, 440 { 441 "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", 442 "EventCode": "0xB7, 0xBB", 443 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 444 "MSRIndex": "0x1a6,0x1a7", 445 "MSRValue": "0x103FC00004", 446 "SampleAfterValue": "100003", 447 "UMask": "0x1" 448 }, 449 { 450 "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", 451 "EventCode": "0xB7, 0xBB", 452 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 453 "MSRIndex": "0x1a6,0x1a7", 454 "MSRValue": "0x83FC00004", 455 "SampleAfterValue": "100003", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.", 460 "EventCode": "0xB7, 0xBB", 461 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 462 "MSRIndex": "0x1a6,0x1a7", 463 "MSRValue": "0x63FC00004", 464 "SampleAfterValue": "100003", 465 "UMask": "0x1" 466 }, 467 { 468 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.", 469 "EventCode": "0xB7, 0xBB", 470 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 471 "MSRIndex": "0x1a6,0x1a7", 472 "MSRValue": "0x604000004", 473 "SampleAfterValue": "100003", 474 "UMask": "0x1" 475 }, 476 { 477 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", 478 "EventCode": "0xB7, 0xBB", 479 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 480 "MSRIndex": "0x1a6,0x1a7", 481 "MSRValue": "0x63B800004", 482 "SampleAfterValue": "100003", 483 "UMask": "0x1" 484 }, 485 { 486 "BriefDescription": "Counts demand data reads that miss in the L3.", 487 "EventCode": "0xB7, 0xBB", 488 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 489 "MSRIndex": "0x1a6,0x1a7", 490 "MSRValue": "0x3FBC000001", 491 "SampleAfterValue": "100003", 492 "UMask": "0x1" 493 }, 494 { 495 "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", 496 "EventCode": "0xB7, 0xBB", 497 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 498 "MSRIndex": "0x1a6,0x1a7", 499 "MSRValue": "0x103FC00001", 500 "SampleAfterValue": "100003", 501 "UMask": "0x1" 502 }, 503 { 504 "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", 505 "EventCode": "0xB7, 0xBB", 506 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 507 "MSRIndex": "0x1a6,0x1a7", 508 "MSRValue": "0x83FC00001", 509 "SampleAfterValue": "100003", 510 "UMask": "0x1" 511 }, 512 { 513 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", 514 "EventCode": "0xB7, 0xBB", 515 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 516 "MSRIndex": "0x1a6,0x1a7", 517 "MSRValue": "0x63FC00001", 518 "SampleAfterValue": "100003", 519 "UMask": "0x1" 520 }, 521 { 522 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", 523 "EventCode": "0xB7, 0xBB", 524 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 525 "MSRIndex": "0x1a6,0x1a7", 526 "MSRValue": "0x604000001", 527 "SampleAfterValue": "100003", 528 "UMask": "0x1" 529 }, 530 { 531 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", 532 "EventCode": "0xB7, 0xBB", 533 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 534 "MSRIndex": "0x1a6,0x1a7", 535 "MSRValue": "0x63B800001", 536 "SampleAfterValue": "100003", 537 "UMask": "0x1" 538 }, 539 { 540 "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", 541 "EventCode": "0xB7, 0xBB", 542 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 543 "MSRIndex": "0x1a6,0x1a7", 544 "MSRValue": "0x3FBC000002", 545 "SampleAfterValue": "100003", 546 "UMask": "0x1" 547 }, 548 { 549 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", 550 "EventCode": "0xB7, 0xBB", 551 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", 552 "MSRIndex": "0x1a6,0x1a7", 553 "MSRValue": "0x103FC00002", 554 "SampleAfterValue": "100003", 555 "UMask": "0x1" 556 }, 557 { 558 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", 559 "EventCode": "0xB7, 0xBB", 560 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 561 "MSRIndex": "0x1a6,0x1a7", 562 "MSRValue": "0x83FC00002", 563 "SampleAfterValue": "100003", 564 "UMask": "0x1" 565 }, 566 { 567 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", 568 "EventCode": "0xB7, 0xBB", 569 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 570 "MSRIndex": "0x1a6,0x1a7", 571 "MSRValue": "0x63FC00002", 572 "SampleAfterValue": "100003", 573 "UMask": "0x1" 574 }, 575 { 576 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", 577 "EventCode": "0xB7, 0xBB", 578 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 579 "MSRIndex": "0x1a6,0x1a7", 580 "MSRValue": "0x604000002", 581 "SampleAfterValue": "100003", 582 "UMask": "0x1" 583 }, 584 { 585 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", 586 "EventCode": "0xB7, 0xBB", 587 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 588 "MSRIndex": "0x1a6,0x1a7", 589 "MSRValue": "0x63B800002", 590 "SampleAfterValue": "100003", 591 "UMask": "0x1" 592 }, 593 { 594 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", 595 "EventCode": "0xB7, 0xBB", 596 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 597 "MSRIndex": "0x1a6,0x1a7", 598 "MSRValue": "0x3FBC000400", 599 "SampleAfterValue": "100003", 600 "UMask": "0x1" 601 }, 602 { 603 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", 604 "EventCode": "0xB7, 0xBB", 605 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 606 "MSRIndex": "0x1a6,0x1a7", 607 "MSRValue": "0x103FC00400", 608 "SampleAfterValue": "100003", 609 "UMask": "0x1" 610 }, 611 { 612 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", 613 "EventCode": "0xB7, 0xBB", 614 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 615 "MSRIndex": "0x1a6,0x1a7", 616 "MSRValue": "0x83FC00400", 617 "SampleAfterValue": "100003", 618 "UMask": "0x1" 619 }, 620 { 621 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", 622 "EventCode": "0xB7, 0xBB", 623 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", 624 "MSRIndex": "0x1a6,0x1a7", 625 "MSRValue": "0x63FC00400", 626 "SampleAfterValue": "100003", 627 "UMask": "0x1" 628 }, 629 { 630 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", 631 "EventCode": "0xB7, 0xBB", 632 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 633 "MSRIndex": "0x1a6,0x1a7", 634 "MSRValue": "0x604000400", 635 "SampleAfterValue": "100003", 636 "UMask": "0x1" 637 }, 638 { 639 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", 640 "EventCode": "0xB7, 0xBB", 641 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 642 "MSRIndex": "0x1a6,0x1a7", 643 "MSRValue": "0x63B800400", 644 "SampleAfterValue": "100003", 645 "UMask": "0x1" 646 }, 647 { 648 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", 649 "EventCode": "0xB7, 0xBB", 650 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 651 "MSRIndex": "0x1a6,0x1a7", 652 "MSRValue": "0x3FBC000010", 653 "SampleAfterValue": "100003", 654 "UMask": "0x1" 655 }, 656 { 657 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", 658 "EventCode": "0xB7, 0xBB", 659 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 660 "MSRIndex": "0x1a6,0x1a7", 661 "MSRValue": "0x103FC00010", 662 "SampleAfterValue": "100003", 663 "UMask": "0x1" 664 }, 665 { 666 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 667 "EventCode": "0xB7, 0xBB", 668 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 669 "MSRIndex": "0x1a6,0x1a7", 670 "MSRValue": "0x83FC00010", 671 "SampleAfterValue": "100003", 672 "UMask": "0x1" 673 }, 674 { 675 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", 676 "EventCode": "0xB7, 0xBB", 677 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 678 "MSRIndex": "0x1a6,0x1a7", 679 "MSRValue": "0x63FC00010", 680 "SampleAfterValue": "100003", 681 "UMask": "0x1" 682 }, 683 { 684 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", 685 "EventCode": "0xB7, 0xBB", 686 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 687 "MSRIndex": "0x1a6,0x1a7", 688 "MSRValue": "0x604000010", 689 "SampleAfterValue": "100003", 690 "UMask": "0x1" 691 }, 692 { 693 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", 694 "EventCode": "0xB7, 0xBB", 695 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 696 "MSRIndex": "0x1a6,0x1a7", 697 "MSRValue": "0x63B800010", 698 "SampleAfterValue": "100003", 699 "UMask": "0x1" 700 }, 701 { 702 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", 703 "EventCode": "0xB7, 0xBB", 704 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", 705 "MSRIndex": "0x1a6,0x1a7", 706 "MSRValue": "0x3FBC000020", 707 "SampleAfterValue": "100003", 708 "UMask": "0x1" 709 }, 710 { 711 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", 712 "EventCode": "0xB7, 0xBB", 713 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", 714 "MSRIndex": "0x1a6,0x1a7", 715 "MSRValue": "0x103FC00020", 716 "SampleAfterValue": "100003", 717 "UMask": "0x1" 718 }, 719 { 720 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 721 "EventCode": "0xB7, 0xBB", 722 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 723 "MSRIndex": "0x1a6,0x1a7", 724 "MSRValue": "0x83FC00020", 725 "SampleAfterValue": "100003", 726 "UMask": "0x1" 727 }, 728 { 729 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", 730 "EventCode": "0xB7, 0xBB", 731 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 732 "MSRIndex": "0x1a6,0x1a7", 733 "MSRValue": "0x63FC00020", 734 "SampleAfterValue": "100003", 735 "UMask": "0x1" 736 }, 737 { 738 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", 739 "EventCode": "0xB7, 0xBB", 740 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 741 "MSRIndex": "0x1a6,0x1a7", 742 "MSRValue": "0x604000020", 743 "SampleAfterValue": "100003", 744 "UMask": "0x1" 745 }, 746 { 747 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", 748 "EventCode": "0xB7, 0xBB", 749 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 750 "MSRIndex": "0x1a6,0x1a7", 751 "MSRValue": "0x63B800020", 752 "SampleAfterValue": "100003", 753 "UMask": "0x1" 754 }, 755 { 756 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", 757 "EventCode": "0xB7, 0xBB", 758 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 759 "MSRIndex": "0x1a6,0x1a7", 760 "MSRValue": "0x3FBC000080", 761 "SampleAfterValue": "100003", 762 "UMask": "0x1" 763 }, 764 { 765 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", 766 "EventCode": "0xB7, 0xBB", 767 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 768 "MSRIndex": "0x1a6,0x1a7", 769 "MSRValue": "0x103FC00080", 770 "SampleAfterValue": "100003", 771 "UMask": "0x1" 772 }, 773 { 774 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 775 "EventCode": "0xB7, 0xBB", 776 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 777 "MSRIndex": "0x1a6,0x1a7", 778 "MSRValue": "0x83FC00080", 779 "SampleAfterValue": "100003", 780 "UMask": "0x1" 781 }, 782 { 783 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", 784 "EventCode": "0xB7, 0xBB", 785 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 786 "MSRIndex": "0x1a6,0x1a7", 787 "MSRValue": "0x63FC00080", 788 "SampleAfterValue": "100003", 789 "UMask": "0x1" 790 }, 791 { 792 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", 793 "EventCode": "0xB7, 0xBB", 794 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 795 "MSRIndex": "0x1a6,0x1a7", 796 "MSRValue": "0x604000080", 797 "SampleAfterValue": "100003", 798 "UMask": "0x1" 799 }, 800 { 801 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", 802 "EventCode": "0xB7, 0xBB", 803 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 804 "MSRIndex": "0x1a6,0x1a7", 805 "MSRValue": "0x63B800080", 806 "SampleAfterValue": "100003", 807 "UMask": "0x1" 808 }, 809 { 810 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", 811 "EventCode": "0xB7, 0xBB", 812 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", 813 "MSRIndex": "0x1a6,0x1a7", 814 "MSRValue": "0x3FBC000100", 815 "SampleAfterValue": "100003", 816 "UMask": "0x1" 817 }, 818 { 819 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", 820 "EventCode": "0xB7, 0xBB", 821 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", 822 "MSRIndex": "0x1a6,0x1a7", 823 "MSRValue": "0x103FC00100", 824 "SampleAfterValue": "100003", 825 "UMask": "0x1" 826 }, 827 { 828 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 829 "EventCode": "0xB7, 0xBB", 830 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 831 "MSRIndex": "0x1a6,0x1a7", 832 "MSRValue": "0x83FC00100", 833 "SampleAfterValue": "100003", 834 "UMask": "0x1" 835 }, 836 { 837 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", 838 "EventCode": "0xB7, 0xBB", 839 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 840 "MSRIndex": "0x1a6,0x1a7", 841 "MSRValue": "0x63FC00100", 842 "SampleAfterValue": "100003", 843 "UMask": "0x1" 844 }, 845 { 846 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", 847 "EventCode": "0xB7, 0xBB", 848 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 849 "MSRIndex": "0x1a6,0x1a7", 850 "MSRValue": "0x604000100", 851 "SampleAfterValue": "100003", 852 "UMask": "0x1" 853 }, 854 { 855 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", 856 "EventCode": "0xB7, 0xBB", 857 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 858 "MSRIndex": "0x1a6,0x1a7", 859 "MSRValue": "0x63B800100", 860 "SampleAfterValue": "100003", 861 "UMask": "0x1" 862 }, 863 { 864 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 865 "EventCode": "0xC9", 866 "EventName": "RTM_RETIRED.ABORTED", 867 "PEBS": "1", 868 "PublicDescription": "Number of times RTM abort was triggered.", 869 "SampleAfterValue": "2000003", 870 "UMask": "0x4" 871 }, 872 { 873 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 874 "EventCode": "0xC9", 875 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 876 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 877 "SampleAfterValue": "2000003", 878 "UMask": "0x80" 879 }, 880 { 881 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 882 "EventCode": "0xC9", 883 "EventName": "RTM_RETIRED.ABORTED_MEM", 884 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 885 "SampleAfterValue": "2000003", 886 "UMask": "0x8" 887 }, 888 { 889 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 890 "EventCode": "0xC9", 891 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 892 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 893 "SampleAfterValue": "2000003", 894 "UMask": "0x40" 895 }, 896 { 897 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 898 "EventCode": "0xC9", 899 "EventName": "RTM_RETIRED.ABORTED_TIMER", 900 "SampleAfterValue": "2000003", 901 "UMask": "0x10" 902 }, 903 { 904 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 905 "EventCode": "0xC9", 906 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 907 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 908 "SampleAfterValue": "2000003", 909 "UMask": "0x20" 910 }, 911 { 912 "BriefDescription": "Number of times an RTM execution successfully committed", 913 "EventCode": "0xC9", 914 "EventName": "RTM_RETIRED.COMMIT", 915 "PublicDescription": "Number of times RTM commit succeeded.", 916 "SampleAfterValue": "2000003", 917 "UMask": "0x2" 918 }, 919 { 920 "BriefDescription": "Number of times an RTM execution started.", 921 "EventCode": "0xC9", 922 "EventName": "RTM_RETIRED.START", 923 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 924 "SampleAfterValue": "2000003", 925 "UMask": "0x1" 926 }, 927 { 928 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 929 "EventCode": "0x5d", 930 "EventName": "TX_EXEC.MISC1", 931 "SampleAfterValue": "2000003", 932 "UMask": "0x1" 933 }, 934 { 935 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 936 "EventCode": "0x5d", 937 "EventName": "TX_EXEC.MISC2", 938 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 939 "SampleAfterValue": "2000003", 940 "UMask": "0x2" 941 }, 942 { 943 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 944 "EventCode": "0x5d", 945 "EventName": "TX_EXEC.MISC3", 946 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 947 "SampleAfterValue": "2000003", 948 "UMask": "0x4" 949 }, 950 { 951 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 952 "EventCode": "0x5d", 953 "EventName": "TX_EXEC.MISC4", 954 "PublicDescription": "RTM region detected inside HLE.", 955 "SampleAfterValue": "2000003", 956 "UMask": "0x8" 957 }, 958 { 959 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 960 "EventCode": "0x5d", 961 "EventName": "TX_EXEC.MISC5", 962 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 963 "SampleAfterValue": "2000003", 964 "UMask": "0x10" 965 }, 966 { 967 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 968 "EventCode": "0x54", 969 "EventName": "TX_MEM.ABORT_CAPACITY", 970 "SampleAfterValue": "2000003", 971 "UMask": "0x2" 972 }, 973 { 974 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 975 "EventCode": "0x54", 976 "EventName": "TX_MEM.ABORT_CONFLICT", 977 "PublicDescription": "Number of times a TSX line had a cache conflict.", 978 "SampleAfterValue": "2000003", 979 "UMask": "0x1" 980 }, 981 { 982 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 983 "EventCode": "0x54", 984 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 985 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 986 "SampleAfterValue": "2000003", 987 "UMask": "0x10" 988 }, 989 { 990 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 991 "EventCode": "0x54", 992 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 993 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 994 "SampleAfterValue": "2000003", 995 "UMask": "0x8" 996 }, 997 { 998 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 999 "EventCode": "0x54", 1000 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 1001 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 1002 "SampleAfterValue": "2000003", 1003 "UMask": "0x20" 1004 }, 1005 { 1006 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 1007 "EventCode": "0x54", 1008 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 1009 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 1010 "SampleAfterValue": "2000003", 1011 "UMask": "0x4" 1012 }, 1013 { 1014 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 1015 "EventCode": "0x54", 1016 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 1017 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 1018 "SampleAfterValue": "2000003", 1019 "UMask": "0x40" 1020 } 1021] 1022