1[
2    {
3        "EventCode": "0x54",
4        "UMask": "0x1",
5        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
6        "Counter": "0,1,2,3",
7        "EventName": "TX_MEM.ABORT_CONFLICT",
8        "PublicDescription": "Number of times a TSX line had a cache conflict.",
9        "SampleAfterValue": "2000003",
10        "CounterHTOff": "0,1,2,3,4,5,6,7"
11    },
12    {
13        "EventCode": "0x54",
14        "UMask": "0x2",
15        "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
16        "Counter": "0,1,2,3",
17        "EventName": "TX_MEM.ABORT_CAPACITY",
18        "SampleAfterValue": "2000003",
19        "CounterHTOff": "0,1,2,3,4,5,6,7"
20    },
21    {
22        "EventCode": "0x54",
23        "UMask": "0x4",
24        "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
25        "Counter": "0,1,2,3",
26        "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
27        "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
28        "SampleAfterValue": "2000003",
29        "CounterHTOff": "0,1,2,3,4,5,6,7"
30    },
31    {
32        "EventCode": "0x54",
33        "UMask": "0x8",
34        "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
35        "Counter": "0,1,2,3",
36        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
37        "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
38        "SampleAfterValue": "2000003",
39        "CounterHTOff": "0,1,2,3,4,5,6,7"
40    },
41    {
42        "EventCode": "0x54",
43        "UMask": "0x10",
44        "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
45        "Counter": "0,1,2,3",
46        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
47        "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
48        "SampleAfterValue": "2000003",
49        "CounterHTOff": "0,1,2,3,4,5,6,7"
50    },
51    {
52        "EventCode": "0x54",
53        "UMask": "0x20",
54        "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
55        "Counter": "0,1,2,3",
56        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
57        "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
58        "SampleAfterValue": "2000003",
59        "CounterHTOff": "0,1,2,3,4,5,6,7"
60    },
61    {
62        "EventCode": "0x54",
63        "UMask": "0x40",
64        "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
65        "Counter": "0,1,2,3",
66        "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
67        "PublicDescription": "Number of times we could not allocate Lock Buffer.",
68        "SampleAfterValue": "2000003",
69        "CounterHTOff": "0,1,2,3,4,5,6,7"
70    },
71    {
72        "EventCode": "0x5d",
73        "UMask": "0x1",
74        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
75        "Counter": "0,1,2,3",
76        "EventName": "TX_EXEC.MISC1",
77        "SampleAfterValue": "2000003",
78        "CounterHTOff": "0,1,2,3,4,5,6,7"
79    },
80    {
81        "EventCode": "0x5d",
82        "UMask": "0x2",
83        "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
84        "Counter": "0,1,2,3",
85        "EventName": "TX_EXEC.MISC2",
86        "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
87        "SampleAfterValue": "2000003",
88        "CounterHTOff": "0,1,2,3,4,5,6,7"
89    },
90    {
91        "EventCode": "0x5d",
92        "UMask": "0x4",
93        "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
94        "Counter": "0,1,2,3",
95        "EventName": "TX_EXEC.MISC3",
96        "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
97        "SampleAfterValue": "2000003",
98        "CounterHTOff": "0,1,2,3,4,5,6,7"
99    },
100    {
101        "EventCode": "0x5d",
102        "UMask": "0x8",
103        "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
104        "Counter": "0,1,2,3",
105        "EventName": "TX_EXEC.MISC4",
106        "PublicDescription": "RTM region detected inside HLE.",
107        "SampleAfterValue": "2000003",
108        "CounterHTOff": "0,1,2,3,4,5,6,7"
109    },
110    {
111        "EventCode": "0x5d",
112        "UMask": "0x10",
113        "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
114        "Counter": "0,1,2,3",
115        "EventName": "TX_EXEC.MISC5",
116        "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
117        "SampleAfterValue": "2000003",
118        "CounterHTOff": "0,1,2,3,4,5,6,7"
119    },
120    {
121        "EventCode": "0x60",
122        "UMask": "0x10",
123        "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
124        "Counter": "0,1,2,3",
125        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
126        "SampleAfterValue": "2000003",
127        "CounterHTOff": "0,1,2,3,4,5,6,7"
128    },
129    {
130        "EventCode": "0x60",
131        "UMask": "0x10",
132        "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
133        "Counter": "0,1,2,3",
134        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
135        "CounterMask": "1",
136        "SampleAfterValue": "2000003",
137        "CounterHTOff": "0,1,2,3,4,5,6,7"
138    },
139    {
140        "EventCode": "0x60",
141        "UMask": "0x10",
142        "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
143        "Counter": "0,1,2,3",
144        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
145        "CounterMask": "6",
146        "SampleAfterValue": "2000003",
147        "CounterHTOff": "0,1,2,3,4,5,6,7"
148    },
149    {
150        "EventCode": "0xA3",
151        "UMask": "0x2",
152        "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
153        "Counter": "0,1,2,3",
154        "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
155        "CounterMask": "2",
156        "SampleAfterValue": "2000003",
157        "CounterHTOff": "0,1,2,3,4,5,6,7"
158    },
159    {
160        "EventCode": "0xA3",
161        "UMask": "0x6",
162        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
163        "Counter": "0,1,2,3",
164        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
165        "CounterMask": "6",
166        "SampleAfterValue": "2000003",
167        "CounterHTOff": "0,1,2,3,4,5,6,7"
168    },
169    {
170        "EventCode": "0xB0",
171        "UMask": "0x10",
172        "BriefDescription": "Demand Data Read requests who miss L3 cache",
173        "Counter": "0,1,2,3",
174        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
175        "PublicDescription": "Demand Data Read requests who miss L3 cache.",
176        "SampleAfterValue": "100003",
177        "CounterHTOff": "0,1,2,3,4,5,6,7"
178    },
179    {
180        "EventCode": "0xC3",
181        "UMask": "0x2",
182        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
183        "Counter": "0,1,2,3",
184        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
185        "Errata": "SKL089",
186        "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
187        "SampleAfterValue": "100003",
188        "CounterHTOff": "0,1,2,3,4,5,6,7"
189    },
190    {
191        "EventCode": "0xC8",
192        "UMask": "0x1",
193        "BriefDescription": "Number of times an HLE execution started.",
194        "Counter": "0,1,2,3",
195        "EventName": "HLE_RETIRED.START",
196        "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
197        "SampleAfterValue": "2000003",
198        "CounterHTOff": "0,1,2,3,4,5,6,7"
199    },
200    {
201        "EventCode": "0xC8",
202        "UMask": "0x2",
203        "BriefDescription": "Number of times an HLE execution successfully committed",
204        "Counter": "0,1,2,3",
205        "EventName": "HLE_RETIRED.COMMIT",
206        "PublicDescription": "Number of times HLE commit succeeded.",
207        "SampleAfterValue": "2000003",
208        "CounterHTOff": "0,1,2,3,4,5,6,7"
209    },
210    {
211        "EventCode": "0xC8",
212        "UMask": "0x4",
213        "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",
214        "PEBS": "1",
215        "Counter": "0,1,2,3",
216        "EventName": "HLE_RETIRED.ABORTED",
217        "PublicDescription": "Number of times HLE abort was triggered.",
218        "SampleAfterValue": "2000003",
219        "CounterHTOff": "0,1,2,3,4,5,6,7"
220    },
221    {
222        "EventCode": "0xC8",
223        "UMask": "0x8",
224        "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
225        "Counter": "0,1,2,3",
226        "EventName": "HLE_RETIRED.ABORTED_MEM",
227        "SampleAfterValue": "2000003",
228        "CounterHTOff": "0,1,2,3,4,5,6,7"
229    },
230    {
231        "EventCode": "0xC8",
232        "UMask": "0x10",
233        "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
234        "Counter": "0,1,2,3",
235        "EventName": "HLE_RETIRED.ABORTED_TIMER",
236        "SampleAfterValue": "2000003",
237        "CounterHTOff": "0,1,2,3,4,5,6,7"
238    },
239    {
240        "EventCode": "0xC8",
241        "UMask": "0x20",
242        "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.). ",
243        "Counter": "0,1,2,3",
244        "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
245        "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
246        "SampleAfterValue": "2000003",
247        "CounterHTOff": "0,1,2,3,4,5,6,7"
248    },
249    {
250        "EventCode": "0xC8",
251        "UMask": "0x40",
252        "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
253        "Counter": "0,1,2,3",
254        "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
255        "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
256        "SampleAfterValue": "2000003",
257        "CounterHTOff": "0,1,2,3,4,5,6,7"
258    },
259    {
260        "EventCode": "0xC8",
261        "UMask": "0x80",
262        "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
263        "Counter": "0,1,2,3",
264        "EventName": "HLE_RETIRED.ABORTED_EVENTS",
265        "SampleAfterValue": "2000003",
266        "CounterHTOff": "0,1,2,3,4,5,6,7"
267    },
268    {
269        "EventCode": "0xC9",
270        "UMask": "0x1",
271        "BriefDescription": "Number of times an RTM execution started.",
272        "Counter": "0,1,2,3",
273        "EventName": "RTM_RETIRED.START",
274        "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
275        "SampleAfterValue": "2000003",
276        "CounterHTOff": "0,1,2,3,4,5,6,7"
277    },
278    {
279        "EventCode": "0xC9",
280        "UMask": "0x2",
281        "BriefDescription": "Number of times an RTM execution successfully committed",
282        "Counter": "0,1,2,3",
283        "EventName": "RTM_RETIRED.COMMIT",
284        "PublicDescription": "Number of times RTM commit succeeded.",
285        "SampleAfterValue": "2000003",
286        "CounterHTOff": "0,1,2,3,4,5,6,7"
287    },
288    {
289        "EventCode": "0xC9",
290        "UMask": "0x4",
291        "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",
292        "PEBS": "1",
293        "Counter": "0,1,2,3",
294        "EventName": "RTM_RETIRED.ABORTED",
295        "PublicDescription": "Number of times RTM abort was triggered.",
296        "SampleAfterValue": "2000003",
297        "CounterHTOff": "0,1,2,3,4,5,6,7"
298    },
299    {
300        "EventCode": "0xC9",
301        "UMask": "0x8",
302        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
303        "Counter": "0,1,2,3",
304        "EventName": "RTM_RETIRED.ABORTED_MEM",
305        "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
306        "SampleAfterValue": "2000003",
307        "CounterHTOff": "0,1,2,3,4,5,6,7"
308    },
309    {
310        "EventCode": "0xC9",
311        "UMask": "0x10",
312        "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
313        "Counter": "0,1,2,3",
314        "EventName": "RTM_RETIRED.ABORTED_TIMER",
315        "SampleAfterValue": "2000003",
316        "CounterHTOff": "0,1,2,3,4,5,6,7"
317    },
318    {
319        "EventCode": "0xC9",
320        "UMask": "0x20",
321        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
322        "Counter": "0,1,2,3",
323        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
324        "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
325        "SampleAfterValue": "2000003",
326        "CounterHTOff": "0,1,2,3,4,5,6,7"
327    },
328    {
329        "EventCode": "0xC9",
330        "UMask": "0x40",
331        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
332        "Counter": "0,1,2,3",
333        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
334        "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
335        "SampleAfterValue": "2000003",
336        "CounterHTOff": "0,1,2,3,4,5,6,7"
337    },
338    {
339        "EventCode": "0xC9",
340        "UMask": "0x80",
341        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
342        "Counter": "0,1,2,3",
343        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
344        "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
345        "SampleAfterValue": "2000003",
346        "CounterHTOff": "0,1,2,3,4,5,6,7"
347    },
348    {
349        "EventCode": "0xCD",
350        "UMask": "0x1",
351        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.",
352        "PEBS": "2",
353        "MSRValue": "0x4",
354        "Counter": "0,1,2,3",
355        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
356        "MSRIndex": "0x3F6",
357        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
358        "TakenAlone": "1",
359        "SampleAfterValue": "100003",
360        "CounterHTOff": "0,1,2,3"
361    },
362    {
363        "EventCode": "0xCD",
364        "UMask": "0x1",
365        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.",
366        "PEBS": "2",
367        "MSRValue": "0x8",
368        "Counter": "0,1,2,3",
369        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
370        "MSRIndex": "0x3F6",
371        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
372        "TakenAlone": "1",
373        "SampleAfterValue": "50021",
374        "CounterHTOff": "0,1,2,3"
375    },
376    {
377        "EventCode": "0xCD",
378        "UMask": "0x1",
379        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.",
380        "PEBS": "2",
381        "MSRValue": "0x10",
382        "Counter": "0,1,2,3",
383        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
384        "MSRIndex": "0x3F6",
385        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
386        "TakenAlone": "1",
387        "SampleAfterValue": "20011",
388        "CounterHTOff": "0,1,2,3"
389    },
390    {
391        "EventCode": "0xCD",
392        "UMask": "0x1",
393        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.",
394        "PEBS": "2",
395        "MSRValue": "0x20",
396        "Counter": "0,1,2,3",
397        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
398        "MSRIndex": "0x3F6",
399        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
400        "TakenAlone": "1",
401        "SampleAfterValue": "100007",
402        "CounterHTOff": "0,1,2,3"
403    },
404    {
405        "EventCode": "0xCD",
406        "UMask": "0x1",
407        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.",
408        "PEBS": "2",
409        "MSRValue": "0x40",
410        "Counter": "0,1,2,3",
411        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
412        "MSRIndex": "0x3F6",
413        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
414        "TakenAlone": "1",
415        "SampleAfterValue": "2003",
416        "CounterHTOff": "0,1,2,3"
417    },
418    {
419        "EventCode": "0xCD",
420        "UMask": "0x1",
421        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.",
422        "PEBS": "2",
423        "MSRValue": "0x80",
424        "Counter": "0,1,2,3",
425        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
426        "MSRIndex": "0x3F6",
427        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
428        "TakenAlone": "1",
429        "SampleAfterValue": "1009",
430        "CounterHTOff": "0,1,2,3"
431    },
432    {
433        "EventCode": "0xCD",
434        "UMask": "0x1",
435        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.",
436        "PEBS": "2",
437        "MSRValue": "0x100",
438        "Counter": "0,1,2,3",
439        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
440        "MSRIndex": "0x3F6",
441        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
442        "TakenAlone": "1",
443        "SampleAfterValue": "503",
444        "CounterHTOff": "0,1,2,3"
445    },
446    {
447        "EventCode": "0xCD",
448        "UMask": "0x1",
449        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.",
450        "PEBS": "2",
451        "MSRValue": "0x200",
452        "Counter": "0,1,2,3",
453        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
454        "MSRIndex": "0x3F6",
455        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
456        "TakenAlone": "1",
457        "SampleAfterValue": "101",
458        "CounterHTOff": "0,1,2,3"
459    },
460    {
461        "Offcore": "1",
462        "EventCode": "0xB7, 0xBB",
463        "UMask": "0x1",
464        "BriefDescription": "Counts demand data reads that miss in the L3.",
465        "MSRValue": "0x3fbc000001 ",
466        "Counter": "0,1,2,3",
467        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
468        "MSRIndex": "0x1a6,0x1a7",
469        "PublicDescription": "Counts demand data reads that miss in the L3. ",
470        "SampleAfterValue": "100003",
471        "CounterHTOff": "0,1,2,3"
472    },
473    {
474        "Offcore": "1",
475        "EventCode": "0xB7, 0xBB",
476        "UMask": "0x1",
477        "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.",
478        "MSRValue": "0x083fc00001 ",
479        "Counter": "0,1,2,3",
480        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
481        "MSRIndex": "0x1a6,0x1a7",
482        "PublicDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache. ",
483        "SampleAfterValue": "100003",
484        "CounterHTOff": "0,1,2,3"
485    },
486    {
487        "Offcore": "1",
488        "EventCode": "0xB7, 0xBB",
489        "UMask": "0x1",
490        "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.",
491        "MSRValue": "0x103fc00001 ",
492        "Counter": "0,1,2,3",
493        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
494        "MSRIndex": "0x1a6,0x1a7",
495        "PublicDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache. ",
496        "SampleAfterValue": "100003",
497        "CounterHTOff": "0,1,2,3"
498    },
499    {
500        "Offcore": "1",
501        "EventCode": "0xB7, 0xBB",
502        "UMask": "0x1",
503        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.",
504        "MSRValue": "0x063fc00001 ",
505        "Counter": "0,1,2,3",
506        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
507        "MSRIndex": "0x1a6,0x1a7",
508        "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram. ",
509        "SampleAfterValue": "100003",
510        "CounterHTOff": "0,1,2,3"
511    },
512    {
513        "Offcore": "1",
514        "EventCode": "0xB7, 0xBB",
515        "UMask": "0x1",
516        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.",
517        "MSRValue": "0x063b800001 ",
518        "Counter": "0,1,2,3",
519        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
520        "MSRIndex": "0x1a6,0x1a7",
521        "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram. ",
522        "SampleAfterValue": "100003",
523        "CounterHTOff": "0,1,2,3"
524    },
525    {
526        "Offcore": "1",
527        "EventCode": "0xB7, 0xBB",
528        "UMask": "0x1",
529        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.",
530        "MSRValue": "0x0604000001 ",
531        "Counter": "0,1,2,3",
532        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
533        "MSRIndex": "0x1a6,0x1a7",
534        "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram. ",
535        "SampleAfterValue": "100003",
536        "CounterHTOff": "0,1,2,3"
537    },
538    {
539        "Offcore": "1",
540        "EventCode": "0xB7, 0xBB",
541        "UMask": "0x1",
542        "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.",
543        "MSRValue": "0x3fbc000002 ",
544        "Counter": "0,1,2,3",
545        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
546        "MSRIndex": "0x1a6,0x1a7",
547        "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3. ",
548        "SampleAfterValue": "100003",
549        "CounterHTOff": "0,1,2,3"
550    },
551    {
552        "Offcore": "1",
553        "EventCode": "0xB7, 0xBB",
554        "UMask": "0x1",
555        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.",
556        "MSRValue": "0x083fc00002 ",
557        "Counter": "0,1,2,3",
558        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
559        "MSRIndex": "0x1a6,0x1a7",
560        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache. ",
561        "SampleAfterValue": "100003",
562        "CounterHTOff": "0,1,2,3"
563    },
564    {
565        "Offcore": "1",
566        "EventCode": "0xB7, 0xBB",
567        "UMask": "0x1",
568        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.",
569        "MSRValue": "0x103fc00002 ",
570        "Counter": "0,1,2,3",
571        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
572        "MSRIndex": "0x1a6,0x1a7",
573        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache. ",
574        "SampleAfterValue": "100003",
575        "CounterHTOff": "0,1,2,3"
576    },
577    {
578        "Offcore": "1",
579        "EventCode": "0xB7, 0xBB",
580        "UMask": "0x1",
581        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.",
582        "MSRValue": "0x063fc00002 ",
583        "Counter": "0,1,2,3",
584        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
585        "MSRIndex": "0x1a6,0x1a7",
586        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram. ",
587        "SampleAfterValue": "100003",
588        "CounterHTOff": "0,1,2,3"
589    },
590    {
591        "Offcore": "1",
592        "EventCode": "0xB7, 0xBB",
593        "UMask": "0x1",
594        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.",
595        "MSRValue": "0x063b800002 ",
596        "Counter": "0,1,2,3",
597        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
598        "MSRIndex": "0x1a6,0x1a7",
599        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram. ",
600        "SampleAfterValue": "100003",
601        "CounterHTOff": "0,1,2,3"
602    },
603    {
604        "Offcore": "1",
605        "EventCode": "0xB7, 0xBB",
606        "UMask": "0x1",
607        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.",
608        "MSRValue": "0x0604000002 ",
609        "Counter": "0,1,2,3",
610        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
611        "MSRIndex": "0x1a6,0x1a7",
612        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram. ",
613        "SampleAfterValue": "100003",
614        "CounterHTOff": "0,1,2,3"
615    },
616    {
617        "Offcore": "1",
618        "EventCode": "0xB7, 0xBB",
619        "UMask": "0x1",
620        "BriefDescription": "Counts all demand code reads that miss in the L3.",
621        "MSRValue": "0x3fbc000004 ",
622        "Counter": "0,1,2,3",
623        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
624        "MSRIndex": "0x1a6,0x1a7",
625        "PublicDescription": "Counts all demand code reads that miss in the L3. ",
626        "SampleAfterValue": "100003",
627        "CounterHTOff": "0,1,2,3"
628    },
629    {
630        "Offcore": "1",
631        "EventCode": "0xB7, 0xBB",
632        "UMask": "0x1",
633        "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.",
634        "MSRValue": "0x083fc00004 ",
635        "Counter": "0,1,2,3",
636        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
637        "MSRIndex": "0x1a6,0x1a7",
638        "PublicDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache. ",
639        "SampleAfterValue": "100003",
640        "CounterHTOff": "0,1,2,3"
641    },
642    {
643        "Offcore": "1",
644        "EventCode": "0xB7, 0xBB",
645        "UMask": "0x1",
646        "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.",
647        "MSRValue": "0x103fc00004 ",
648        "Counter": "0,1,2,3",
649        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
650        "MSRIndex": "0x1a6,0x1a7",
651        "PublicDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache. ",
652        "SampleAfterValue": "100003",
653        "CounterHTOff": "0,1,2,3"
654    },
655    {
656        "Offcore": "1",
657        "EventCode": "0xB7, 0xBB",
658        "UMask": "0x1",
659        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.",
660        "MSRValue": "0x063fc00004 ",
661        "Counter": "0,1,2,3",
662        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
663        "MSRIndex": "0x1a6,0x1a7",
664        "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram. ",
665        "SampleAfterValue": "100003",
666        "CounterHTOff": "0,1,2,3"
667    },
668    {
669        "Offcore": "1",
670        "EventCode": "0xB7, 0xBB",
671        "UMask": "0x1",
672        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.",
673        "MSRValue": "0x063b800004 ",
674        "Counter": "0,1,2,3",
675        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
676        "MSRIndex": "0x1a6,0x1a7",
677        "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram. ",
678        "SampleAfterValue": "100003",
679        "CounterHTOff": "0,1,2,3"
680    },
681    {
682        "Offcore": "1",
683        "EventCode": "0xB7, 0xBB",
684        "UMask": "0x1",
685        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.",
686        "MSRValue": "0x0604000004 ",
687        "Counter": "0,1,2,3",
688        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
689        "MSRIndex": "0x1a6,0x1a7",
690        "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram. ",
691        "SampleAfterValue": "100003",
692        "CounterHTOff": "0,1,2,3"
693    },
694    {
695        "Offcore": "1",
696        "EventCode": "0xB7, 0xBB",
697        "UMask": "0x1",
698        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.",
699        "MSRValue": "0x3fbc000010 ",
700        "Counter": "0,1,2,3",
701        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
702        "MSRIndex": "0x1a6,0x1a7",
703        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3. ",
704        "SampleAfterValue": "100003",
705        "CounterHTOff": "0,1,2,3"
706    },
707    {
708        "Offcore": "1",
709        "EventCode": "0xB7, 0xBB",
710        "UMask": "0x1",
711        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
712        "MSRValue": "0x083fc00010 ",
713        "Counter": "0,1,2,3",
714        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
715        "MSRIndex": "0x1a6,0x1a7",
716        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache. ",
717        "SampleAfterValue": "100003",
718        "CounterHTOff": "0,1,2,3"
719    },
720    {
721        "Offcore": "1",
722        "EventCode": "0xB7, 0xBB",
723        "UMask": "0x1",
724        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.",
725        "MSRValue": "0x103fc00010 ",
726        "Counter": "0,1,2,3",
727        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
728        "MSRIndex": "0x1a6,0x1a7",
729        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache. ",
730        "SampleAfterValue": "100003",
731        "CounterHTOff": "0,1,2,3"
732    },
733    {
734        "Offcore": "1",
735        "EventCode": "0xB7, 0xBB",
736        "UMask": "0x1",
737        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.",
738        "MSRValue": "0x063fc00010 ",
739        "Counter": "0,1,2,3",
740        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
741        "MSRIndex": "0x1a6,0x1a7",
742        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram. ",
743        "SampleAfterValue": "100003",
744        "CounterHTOff": "0,1,2,3"
745    },
746    {
747        "Offcore": "1",
748        "EventCode": "0xB7, 0xBB",
749        "UMask": "0x1",
750        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.",
751        "MSRValue": "0x063b800010 ",
752        "Counter": "0,1,2,3",
753        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
754        "MSRIndex": "0x1a6,0x1a7",
755        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram. ",
756        "SampleAfterValue": "100003",
757        "CounterHTOff": "0,1,2,3"
758    },
759    {
760        "Offcore": "1",
761        "EventCode": "0xB7, 0xBB",
762        "UMask": "0x1",
763        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.",
764        "MSRValue": "0x0604000010 ",
765        "Counter": "0,1,2,3",
766        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
767        "MSRIndex": "0x1a6,0x1a7",
768        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram. ",
769        "SampleAfterValue": "100003",
770        "CounterHTOff": "0,1,2,3"
771    },
772    {
773        "Offcore": "1",
774        "EventCode": "0xB7, 0xBB",
775        "UMask": "0x1",
776        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.",
777        "MSRValue": "0x3fbc000020 ",
778        "Counter": "0,1,2,3",
779        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
780        "MSRIndex": "0x1a6,0x1a7",
781        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3. ",
782        "SampleAfterValue": "100003",
783        "CounterHTOff": "0,1,2,3"
784    },
785    {
786        "Offcore": "1",
787        "EventCode": "0xB7, 0xBB",
788        "UMask": "0x1",
789        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
790        "MSRValue": "0x083fc00020 ",
791        "Counter": "0,1,2,3",
792        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
793        "MSRIndex": "0x1a6,0x1a7",
794        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache. ",
795        "SampleAfterValue": "100003",
796        "CounterHTOff": "0,1,2,3"
797    },
798    {
799        "Offcore": "1",
800        "EventCode": "0xB7, 0xBB",
801        "UMask": "0x1",
802        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.",
803        "MSRValue": "0x103fc00020 ",
804        "Counter": "0,1,2,3",
805        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
806        "MSRIndex": "0x1a6,0x1a7",
807        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache. ",
808        "SampleAfterValue": "100003",
809        "CounterHTOff": "0,1,2,3"
810    },
811    {
812        "Offcore": "1",
813        "EventCode": "0xB7, 0xBB",
814        "UMask": "0x1",
815        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.",
816        "MSRValue": "0x063fc00020 ",
817        "Counter": "0,1,2,3",
818        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
819        "MSRIndex": "0x1a6,0x1a7",
820        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram. ",
821        "SampleAfterValue": "100003",
822        "CounterHTOff": "0,1,2,3"
823    },
824    {
825        "Offcore": "1",
826        "EventCode": "0xB7, 0xBB",
827        "UMask": "0x1",
828        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.",
829        "MSRValue": "0x063b800020 ",
830        "Counter": "0,1,2,3",
831        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
832        "MSRIndex": "0x1a6,0x1a7",
833        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram. ",
834        "SampleAfterValue": "100003",
835        "CounterHTOff": "0,1,2,3"
836    },
837    {
838        "Offcore": "1",
839        "EventCode": "0xB7, 0xBB",
840        "UMask": "0x1",
841        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.",
842        "MSRValue": "0x0604000020 ",
843        "Counter": "0,1,2,3",
844        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
845        "MSRIndex": "0x1a6,0x1a7",
846        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram. ",
847        "SampleAfterValue": "100003",
848        "CounterHTOff": "0,1,2,3"
849    },
850    {
851        "Offcore": "1",
852        "EventCode": "0xB7, 0xBB",
853        "UMask": "0x1",
854        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.",
855        "MSRValue": "0x3fbc000080 ",
856        "Counter": "0,1,2,3",
857        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
858        "MSRIndex": "0x1a6,0x1a7",
859        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3. ",
860        "SampleAfterValue": "100003",
861        "CounterHTOff": "0,1,2,3"
862    },
863    {
864        "Offcore": "1",
865        "EventCode": "0xB7, 0xBB",
866        "UMask": "0x1",
867        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
868        "MSRValue": "0x083fc00080 ",
869        "Counter": "0,1,2,3",
870        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
871        "MSRIndex": "0x1a6,0x1a7",
872        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache. ",
873        "SampleAfterValue": "100003",
874        "CounterHTOff": "0,1,2,3"
875    },
876    {
877        "Offcore": "1",
878        "EventCode": "0xB7, 0xBB",
879        "UMask": "0x1",
880        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.",
881        "MSRValue": "0x103fc00080 ",
882        "Counter": "0,1,2,3",
883        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
884        "MSRIndex": "0x1a6,0x1a7",
885        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache. ",
886        "SampleAfterValue": "100003",
887        "CounterHTOff": "0,1,2,3"
888    },
889    {
890        "Offcore": "1",
891        "EventCode": "0xB7, 0xBB",
892        "UMask": "0x1",
893        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.",
894        "MSRValue": "0x063fc00080 ",
895        "Counter": "0,1,2,3",
896        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
897        "MSRIndex": "0x1a6,0x1a7",
898        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram. ",
899        "SampleAfterValue": "100003",
900        "CounterHTOff": "0,1,2,3"
901    },
902    {
903        "Offcore": "1",
904        "EventCode": "0xB7, 0xBB",
905        "UMask": "0x1",
906        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.",
907        "MSRValue": "0x063b800080 ",
908        "Counter": "0,1,2,3",
909        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
910        "MSRIndex": "0x1a6,0x1a7",
911        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram. ",
912        "SampleAfterValue": "100003",
913        "CounterHTOff": "0,1,2,3"
914    },
915    {
916        "Offcore": "1",
917        "EventCode": "0xB7, 0xBB",
918        "UMask": "0x1",
919        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.",
920        "MSRValue": "0x0604000080 ",
921        "Counter": "0,1,2,3",
922        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
923        "MSRIndex": "0x1a6,0x1a7",
924        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram. ",
925        "SampleAfterValue": "100003",
926        "CounterHTOff": "0,1,2,3"
927    },
928    {
929        "Offcore": "1",
930        "EventCode": "0xB7, 0xBB",
931        "UMask": "0x1",
932        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.",
933        "MSRValue": "0x3fbc000100 ",
934        "Counter": "0,1,2,3",
935        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
936        "MSRIndex": "0x1a6,0x1a7",
937        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3. ",
938        "SampleAfterValue": "100003",
939        "CounterHTOff": "0,1,2,3"
940    },
941    {
942        "Offcore": "1",
943        "EventCode": "0xB7, 0xBB",
944        "UMask": "0x1",
945        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
946        "MSRValue": "0x083fc00100 ",
947        "Counter": "0,1,2,3",
948        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
949        "MSRIndex": "0x1a6,0x1a7",
950        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache. ",
951        "SampleAfterValue": "100003",
952        "CounterHTOff": "0,1,2,3"
953    },
954    {
955        "Offcore": "1",
956        "EventCode": "0xB7, 0xBB",
957        "UMask": "0x1",
958        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.",
959        "MSRValue": "0x103fc00100 ",
960        "Counter": "0,1,2,3",
961        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
962        "MSRIndex": "0x1a6,0x1a7",
963        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache. ",
964        "SampleAfterValue": "100003",
965        "CounterHTOff": "0,1,2,3"
966    },
967    {
968        "Offcore": "1",
969        "EventCode": "0xB7, 0xBB",
970        "UMask": "0x1",
971        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.",
972        "MSRValue": "0x063fc00100 ",
973        "Counter": "0,1,2,3",
974        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
975        "MSRIndex": "0x1a6,0x1a7",
976        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram. ",
977        "SampleAfterValue": "100003",
978        "CounterHTOff": "0,1,2,3"
979    },
980    {
981        "Offcore": "1",
982        "EventCode": "0xB7, 0xBB",
983        "UMask": "0x1",
984        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.",
985        "MSRValue": "0x063b800100 ",
986        "Counter": "0,1,2,3",
987        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
988        "MSRIndex": "0x1a6,0x1a7",
989        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram. ",
990        "SampleAfterValue": "100003",
991        "CounterHTOff": "0,1,2,3"
992    },
993    {
994        "Offcore": "1",
995        "EventCode": "0xB7, 0xBB",
996        "UMask": "0x1",
997        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.",
998        "MSRValue": "0x0604000100 ",
999        "Counter": "0,1,2,3",
1000        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1001        "MSRIndex": "0x1a6,0x1a7",
1002        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram. ",
1003        "SampleAfterValue": "100003",
1004        "CounterHTOff": "0,1,2,3"
1005    },
1006    {
1007        "Offcore": "1",
1008        "EventCode": "0xB7, 0xBB",
1009        "UMask": "0x1",
1010        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.",
1011        "MSRValue": "0x3fbc000400 ",
1012        "Counter": "0,1,2,3",
1013        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
1014        "MSRIndex": "0x1a6,0x1a7",
1015        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3. ",
1016        "SampleAfterValue": "100003",
1017        "CounterHTOff": "0,1,2,3"
1018    },
1019    {
1020        "Offcore": "1",
1021        "EventCode": "0xB7, 0xBB",
1022        "UMask": "0x1",
1023        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.",
1024        "MSRValue": "0x083fc00400 ",
1025        "Counter": "0,1,2,3",
1026        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
1027        "MSRIndex": "0x1a6,0x1a7",
1028        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache. ",
1029        "SampleAfterValue": "100003",
1030        "CounterHTOff": "0,1,2,3"
1031    },
1032    {
1033        "Offcore": "1",
1034        "EventCode": "0xB7, 0xBB",
1035        "UMask": "0x1",
1036        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.",
1037        "MSRValue": "0x103fc00400 ",
1038        "Counter": "0,1,2,3",
1039        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
1040        "MSRIndex": "0x1a6,0x1a7",
1041        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache. ",
1042        "SampleAfterValue": "100003",
1043        "CounterHTOff": "0,1,2,3"
1044    },
1045    {
1046        "Offcore": "1",
1047        "EventCode": "0xB7, 0xBB",
1048        "UMask": "0x1",
1049        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.",
1050        "MSRValue": "0x063fc00400 ",
1051        "Counter": "0,1,2,3",
1052        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1053        "MSRIndex": "0x1a6,0x1a7",
1054        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram. ",
1055        "SampleAfterValue": "100003",
1056        "CounterHTOff": "0,1,2,3"
1057    },
1058    {
1059        "Offcore": "1",
1060        "EventCode": "0xB7, 0xBB",
1061        "UMask": "0x1",
1062        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.",
1063        "MSRValue": "0x063b800400 ",
1064        "Counter": "0,1,2,3",
1065        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1066        "MSRIndex": "0x1a6,0x1a7",
1067        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram. ",
1068        "SampleAfterValue": "100003",
1069        "CounterHTOff": "0,1,2,3"
1070    },
1071    {
1072        "Offcore": "1",
1073        "EventCode": "0xB7, 0xBB",
1074        "UMask": "0x1",
1075        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.",
1076        "MSRValue": "0x0604000400 ",
1077        "Counter": "0,1,2,3",
1078        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1079        "MSRIndex": "0x1a6,0x1a7",
1080        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram. ",
1081        "SampleAfterValue": "100003",
1082        "CounterHTOff": "0,1,2,3"
1083    },
1084    {
1085        "Offcore": "1",
1086        "EventCode": "0xB7, 0xBB",
1087        "UMask": "0x1",
1088        "BriefDescription": "Counts all prefetch data reads that miss in the L3.",
1089        "MSRValue": "0x3fbc000490 ",
1090        "Counter": "0,1,2,3",
1091        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
1092        "MSRIndex": "0x1a6,0x1a7",
1093        "PublicDescription": "Counts all prefetch data reads that miss in the L3. ",
1094        "SampleAfterValue": "100003",
1095        "CounterHTOff": "0,1,2,3"
1096    },
1097    {
1098        "Offcore": "1",
1099        "EventCode": "0xB7, 0xBB",
1100        "UMask": "0x1",
1101        "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
1102        "MSRValue": "0x083fc00490 ",
1103        "Counter": "0,1,2,3",
1104        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
1105        "MSRIndex": "0x1a6,0x1a7",
1106        "PublicDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache. ",
1107        "SampleAfterValue": "100003",
1108        "CounterHTOff": "0,1,2,3"
1109    },
1110    {
1111        "Offcore": "1",
1112        "EventCode": "0xB7, 0xBB",
1113        "UMask": "0x1",
1114        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
1115        "MSRValue": "0x103fc00490 ",
1116        "Counter": "0,1,2,3",
1117        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
1118        "MSRIndex": "0x1a6,0x1a7",
1119        "PublicDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache. ",
1120        "SampleAfterValue": "100003",
1121        "CounterHTOff": "0,1,2,3"
1122    },
1123    {
1124        "Offcore": "1",
1125        "EventCode": "0xB7, 0xBB",
1126        "UMask": "0x1",
1127        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
1128        "MSRValue": "0x063fc00490 ",
1129        "Counter": "0,1,2,3",
1130        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1131        "MSRIndex": "0x1a6,0x1a7",
1132        "PublicDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram. ",
1133        "SampleAfterValue": "100003",
1134        "CounterHTOff": "0,1,2,3"
1135    },
1136    {
1137        "Offcore": "1",
1138        "EventCode": "0xB7, 0xBB",
1139        "UMask": "0x1",
1140        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.",
1141        "MSRValue": "0x063b800490 ",
1142        "Counter": "0,1,2,3",
1143        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1144        "MSRIndex": "0x1a6,0x1a7",
1145        "PublicDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram. ",
1146        "SampleAfterValue": "100003",
1147        "CounterHTOff": "0,1,2,3"
1148    },
1149    {
1150        "Offcore": "1",
1151        "EventCode": "0xB7, 0xBB",
1152        "UMask": "0x1",
1153        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.",
1154        "MSRValue": "0x0604000490 ",
1155        "Counter": "0,1,2,3",
1156        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1157        "MSRIndex": "0x1a6,0x1a7",
1158        "PublicDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram. ",
1159        "SampleAfterValue": "100003",
1160        "CounterHTOff": "0,1,2,3"
1161    },
1162    {
1163        "Offcore": "1",
1164        "EventCode": "0xB7, 0xBB",
1165        "UMask": "0x1",
1166        "BriefDescription": "Counts prefetch RFOs that miss in the L3.",
1167        "MSRValue": "0x3fbc000120 ",
1168        "Counter": "0,1,2,3",
1169        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
1170        "MSRIndex": "0x1a6,0x1a7",
1171        "PublicDescription": "Counts prefetch RFOs that miss in the L3. ",
1172        "SampleAfterValue": "100003",
1173        "CounterHTOff": "0,1,2,3"
1174    },
1175    {
1176        "Offcore": "1",
1177        "EventCode": "0xB7, 0xBB",
1178        "UMask": "0x1",
1179        "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
1180        "MSRValue": "0x083fc00120 ",
1181        "Counter": "0,1,2,3",
1182        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
1183        "MSRIndex": "0x1a6,0x1a7",
1184        "PublicDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache. ",
1185        "SampleAfterValue": "100003",
1186        "CounterHTOff": "0,1,2,3"
1187    },
1188    {
1189        "Offcore": "1",
1190        "EventCode": "0xB7, 0xBB",
1191        "UMask": "0x1",
1192        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
1193        "MSRValue": "0x103fc00120 ",
1194        "Counter": "0,1,2,3",
1195        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
1196        "MSRIndex": "0x1a6,0x1a7",
1197        "PublicDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache. ",
1198        "SampleAfterValue": "100003",
1199        "CounterHTOff": "0,1,2,3"
1200    },
1201    {
1202        "Offcore": "1",
1203        "EventCode": "0xB7, 0xBB",
1204        "UMask": "0x1",
1205        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
1206        "MSRValue": "0x063fc00120 ",
1207        "Counter": "0,1,2,3",
1208        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1209        "MSRIndex": "0x1a6,0x1a7",
1210        "PublicDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram. ",
1211        "SampleAfterValue": "100003",
1212        "CounterHTOff": "0,1,2,3"
1213    },
1214    {
1215        "Offcore": "1",
1216        "EventCode": "0xB7, 0xBB",
1217        "UMask": "0x1",
1218        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.",
1219        "MSRValue": "0x063b800120 ",
1220        "Counter": "0,1,2,3",
1221        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1222        "MSRIndex": "0x1a6,0x1a7",
1223        "PublicDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram. ",
1224        "SampleAfterValue": "100003",
1225        "CounterHTOff": "0,1,2,3"
1226    },
1227    {
1228        "Offcore": "1",
1229        "EventCode": "0xB7, 0xBB",
1230        "UMask": "0x1",
1231        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.",
1232        "MSRValue": "0x0604000120 ",
1233        "Counter": "0,1,2,3",
1234        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1235        "MSRIndex": "0x1a6,0x1a7",
1236        "PublicDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram. ",
1237        "SampleAfterValue": "100003",
1238        "CounterHTOff": "0,1,2,3"
1239    },
1240    {
1241        "Offcore": "1",
1242        "EventCode": "0xB7, 0xBB",
1243        "UMask": "0x1",
1244        "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
1245        "MSRValue": "0x3fbc000491 ",
1246        "Counter": "0,1,2,3",
1247        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
1248        "MSRIndex": "0x1a6,0x1a7",
1249        "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3. ",
1250        "SampleAfterValue": "100003",
1251        "CounterHTOff": "0,1,2,3"
1252    },
1253    {
1254        "Offcore": "1",
1255        "EventCode": "0xB7, 0xBB",
1256        "UMask": "0x1",
1257        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
1258        "MSRValue": "0x083fc00491 ",
1259        "Counter": "0,1,2,3",
1260        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
1261        "MSRIndex": "0x1a6,0x1a7",
1262        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache. ",
1263        "SampleAfterValue": "100003",
1264        "CounterHTOff": "0,1,2,3"
1265    },
1266    {
1267        "Offcore": "1",
1268        "EventCode": "0xB7, 0xBB",
1269        "UMask": "0x1",
1270        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
1271        "MSRValue": "0x103fc00491 ",
1272        "Counter": "0,1,2,3",
1273        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
1274        "MSRIndex": "0x1a6,0x1a7",
1275        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache. ",
1276        "SampleAfterValue": "100003",
1277        "CounterHTOff": "0,1,2,3"
1278    },
1279    {
1280        "Offcore": "1",
1281        "EventCode": "0xB7, 0xBB",
1282        "UMask": "0x1",
1283        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
1284        "MSRValue": "0x063fc00491 ",
1285        "Counter": "0,1,2,3",
1286        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1287        "MSRIndex": "0x1a6,0x1a7",
1288        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram. ",
1289        "SampleAfterValue": "100003",
1290        "CounterHTOff": "0,1,2,3"
1291    },
1292    {
1293        "Offcore": "1",
1294        "EventCode": "0xB7, 0xBB",
1295        "UMask": "0x1",
1296        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.",
1297        "MSRValue": "0x063b800491 ",
1298        "Counter": "0,1,2,3",
1299        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1300        "MSRIndex": "0x1a6,0x1a7",
1301        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram. ",
1302        "SampleAfterValue": "100003",
1303        "CounterHTOff": "0,1,2,3"
1304    },
1305    {
1306        "Offcore": "1",
1307        "EventCode": "0xB7, 0xBB",
1308        "UMask": "0x1",
1309        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.",
1310        "MSRValue": "0x0604000491 ",
1311        "Counter": "0,1,2,3",
1312        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1313        "MSRIndex": "0x1a6,0x1a7",
1314        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram. ",
1315        "SampleAfterValue": "100003",
1316        "CounterHTOff": "0,1,2,3"
1317    },
1318    {
1319        "Offcore": "1",
1320        "EventCode": "0xB7, 0xBB",
1321        "UMask": "0x1",
1322        "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.",
1323        "MSRValue": "0x3fbc000122 ",
1324        "Counter": "0,1,2,3",
1325        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
1326        "MSRIndex": "0x1a6,0x1a7",
1327        "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3. ",
1328        "SampleAfterValue": "100003",
1329        "CounterHTOff": "0,1,2,3"
1330    },
1331    {
1332        "Offcore": "1",
1333        "EventCode": "0xB7, 0xBB",
1334        "UMask": "0x1",
1335        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
1336        "MSRValue": "0x083fc00122 ",
1337        "Counter": "0,1,2,3",
1338        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
1339        "MSRIndex": "0x1a6,0x1a7",
1340        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache. ",
1341        "SampleAfterValue": "100003",
1342        "CounterHTOff": "0,1,2,3"
1343    },
1344    {
1345        "Offcore": "1",
1346        "EventCode": "0xB7, 0xBB",
1347        "UMask": "0x1",
1348        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
1349        "MSRValue": "0x103fc00122 ",
1350        "Counter": "0,1,2,3",
1351        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
1352        "MSRIndex": "0x1a6,0x1a7",
1353        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache. ",
1354        "SampleAfterValue": "100003",
1355        "CounterHTOff": "0,1,2,3"
1356    },
1357    {
1358        "Offcore": "1",
1359        "EventCode": "0xB7, 0xBB",
1360        "UMask": "0x1",
1361        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
1362        "MSRValue": "0x063fc00122 ",
1363        "Counter": "0,1,2,3",
1364        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1365        "MSRIndex": "0x1a6,0x1a7",
1366        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram. ",
1367        "SampleAfterValue": "100003",
1368        "CounterHTOff": "0,1,2,3"
1369    },
1370    {
1371        "Offcore": "1",
1372        "EventCode": "0xB7, 0xBB",
1373        "UMask": "0x1",
1374        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.",
1375        "MSRValue": "0x063b800122 ",
1376        "Counter": "0,1,2,3",
1377        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1378        "MSRIndex": "0x1a6,0x1a7",
1379        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram. ",
1380        "SampleAfterValue": "100003",
1381        "CounterHTOff": "0,1,2,3"
1382    },
1383    {
1384        "Offcore": "1",
1385        "EventCode": "0xB7, 0xBB",
1386        "UMask": "0x1",
1387        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.",
1388        "MSRValue": "0x0604000122 ",
1389        "Counter": "0,1,2,3",
1390        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1391        "MSRIndex": "0x1a6,0x1a7",
1392        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.",
1393        "SampleAfterValue": "100003",
1394        "CounterHTOff": "0,1,2,3"
1395    }
1396]
1397