1[ 2 { 3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "CounterMask": "2", 7 "EventCode": "0xA3", 8 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x2" 11 }, 12 { 13 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "CounterMask": "6", 17 "EventCode": "0xA3", 18 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 19 "SampleAfterValue": "2000003", 20 "UMask": "0x6" 21 }, 22 { 23 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 24 "Counter": "0,1,2,3", 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "EventCode": "0xC8", 27 "EventName": "HLE_RETIRED.ABORTED", 28 "PEBS": "1", 29 "PublicDescription": "Number of times HLE abort was triggered.", 30 "SampleAfterValue": "2000003", 31 "UMask": "0x4" 32 }, 33 { 34 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 35 "Counter": "0,1,2,3", 36 "CounterHTOff": "0,1,2,3,4,5,6,7", 37 "EventCode": "0xC8", 38 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 39 "SampleAfterValue": "2000003", 40 "UMask": "0x80" 41 }, 42 { 43 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 44 "Counter": "0,1,2,3", 45 "CounterHTOff": "0,1,2,3,4,5,6,7", 46 "EventCode": "0xC8", 47 "EventName": "HLE_RETIRED.ABORTED_MEM", 48 "SampleAfterValue": "2000003", 49 "UMask": "0x8" 50 }, 51 { 52 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 53 "Counter": "0,1,2,3", 54 "CounterHTOff": "0,1,2,3,4,5,6,7", 55 "EventCode": "0xC8", 56 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 57 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 58 "SampleAfterValue": "2000003", 59 "UMask": "0x40" 60 }, 61 { 62 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 63 "Counter": "0,1,2,3", 64 "CounterHTOff": "0,1,2,3,4,5,6,7", 65 "EventCode": "0xC8", 66 "EventName": "HLE_RETIRED.ABORTED_TIMER", 67 "SampleAfterValue": "2000003", 68 "UMask": "0x10" 69 }, 70 { 71 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 72 "Counter": "0,1,2,3", 73 "CounterHTOff": "0,1,2,3,4,5,6,7", 74 "EventCode": "0xC8", 75 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 76 "SampleAfterValue": "2000003", 77 "UMask": "0x20" 78 }, 79 { 80 "BriefDescription": "Number of times an HLE execution successfully committed", 81 "Counter": "0,1,2,3", 82 "CounterHTOff": "0,1,2,3,4,5,6,7", 83 "EventCode": "0xC8", 84 "EventName": "HLE_RETIRED.COMMIT", 85 "PublicDescription": "Number of times HLE commit succeeded.", 86 "SampleAfterValue": "2000003", 87 "UMask": "0x2" 88 }, 89 { 90 "BriefDescription": "Number of times an HLE execution started.", 91 "Counter": "0,1,2,3", 92 "CounterHTOff": "0,1,2,3,4,5,6,7", 93 "EventCode": "0xC8", 94 "EventName": "HLE_RETIRED.START", 95 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 96 "SampleAfterValue": "2000003", 97 "UMask": "0x1" 98 }, 99 { 100 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 101 "Counter": "0,1,2,3", 102 "CounterHTOff": "0,1,2,3,4,5,6,7", 103 "Errata": "SKL089", 104 "EventCode": "0xC3", 105 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 106 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 107 "SampleAfterValue": "100003", 108 "UMask": "0x2" 109 }, 110 { 111 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 112 "Counter": "0,1,2,3", 113 "CounterHTOff": "0,1,2,3", 114 "Data_LA": "1", 115 "EventCode": "0xcd", 116 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 117 "MSRIndex": "0x3F6", 118 "MSRValue": "0x80", 119 "PEBS": "2", 120 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 121 "SampleAfterValue": "1009", 122 "TakenAlone": "1", 123 "UMask": "0x1" 124 }, 125 { 126 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 127 "Counter": "0,1,2,3", 128 "CounterHTOff": "0,1,2,3", 129 "Data_LA": "1", 130 "EventCode": "0xcd", 131 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 132 "MSRIndex": "0x3F6", 133 "MSRValue": "0x10", 134 "PEBS": "2", 135 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 136 "SampleAfterValue": "20011", 137 "TakenAlone": "1", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 142 "Counter": "0,1,2,3", 143 "CounterHTOff": "0,1,2,3", 144 "Data_LA": "1", 145 "EventCode": "0xcd", 146 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 147 "MSRIndex": "0x3F6", 148 "MSRValue": "0x100", 149 "PEBS": "2", 150 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 151 "SampleAfterValue": "503", 152 "TakenAlone": "1", 153 "UMask": "0x1" 154 }, 155 { 156 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 157 "Counter": "0,1,2,3", 158 "CounterHTOff": "0,1,2,3", 159 "Data_LA": "1", 160 "EventCode": "0xcd", 161 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 162 "MSRIndex": "0x3F6", 163 "MSRValue": "0x20", 164 "PEBS": "2", 165 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 166 "SampleAfterValue": "100007", 167 "TakenAlone": "1", 168 "UMask": "0x1" 169 }, 170 { 171 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 172 "Counter": "0,1,2,3", 173 "CounterHTOff": "0,1,2,3", 174 "Data_LA": "1", 175 "EventCode": "0xcd", 176 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 177 "MSRIndex": "0x3F6", 178 "MSRValue": "0x4", 179 "PEBS": "2", 180 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 181 "SampleAfterValue": "100003", 182 "TakenAlone": "1", 183 "UMask": "0x1" 184 }, 185 { 186 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 187 "Counter": "0,1,2,3", 188 "CounterHTOff": "0,1,2,3", 189 "Data_LA": "1", 190 "EventCode": "0xcd", 191 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 192 "MSRIndex": "0x3F6", 193 "MSRValue": "0x200", 194 "PEBS": "2", 195 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 196 "SampleAfterValue": "101", 197 "TakenAlone": "1", 198 "UMask": "0x1" 199 }, 200 { 201 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 202 "Counter": "0,1,2,3", 203 "CounterHTOff": "0,1,2,3", 204 "Data_LA": "1", 205 "EventCode": "0xcd", 206 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 207 "MSRIndex": "0x3F6", 208 "MSRValue": "0x40", 209 "PEBS": "2", 210 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 211 "SampleAfterValue": "2003", 212 "TakenAlone": "1", 213 "UMask": "0x1" 214 }, 215 { 216 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 217 "Counter": "0,1,2,3", 218 "CounterHTOff": "0,1,2,3", 219 "Data_LA": "1", 220 "EventCode": "0xcd", 221 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 222 "MSRIndex": "0x3F6", 223 "MSRValue": "0x8", 224 "PEBS": "2", 225 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 226 "SampleAfterValue": "50021", 227 "TakenAlone": "1", 228 "UMask": "0x1" 229 }, 230 { 231 "BriefDescription": "Demand Data Read requests who miss L3 cache", 232 "Counter": "0,1,2,3", 233 "CounterHTOff": "0,1,2,3,4,5,6,7", 234 "EventCode": "0xB0", 235 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 236 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 237 "SampleAfterValue": "100003", 238 "UMask": "0x10" 239 }, 240 { 241 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 242 "Counter": "0,1,2,3", 243 "CounterHTOff": "0,1,2,3,4,5,6,7", 244 "CounterMask": "1", 245 "EventCode": "0x60", 246 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 247 "SampleAfterValue": "2000003", 248 "UMask": "0x10" 249 }, 250 { 251 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 252 "Counter": "0,1,2,3", 253 "CounterHTOff": "0,1,2,3,4,5,6,7", 254 "EventCode": "0x60", 255 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 256 "SampleAfterValue": "2000003", 257 "UMask": "0x10" 258 }, 259 { 260 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 261 "Counter": "0,1,2,3", 262 "CounterHTOff": "0,1,2,3,4,5,6,7", 263 "CounterMask": "6", 264 "EventCode": "0x60", 265 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 266 "SampleAfterValue": "2000003", 267 "UMask": "0x10" 268 }, 269 { 270 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 271 "Counter": "0,1,2,3", 272 "CounterHTOff": "0,1,2,3", 273 "EventCode": "0xB7, 0xBB", 274 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 275 "MSRIndex": "0x1a6,0x1a7", 276 "MSRValue": "0x3FBC000491", 277 "Offcore": "1", 278 "SampleAfterValue": "100003", 279 "UMask": "0x1" 280 }, 281 { 282 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 283 "Counter": "0,1,2,3", 284 "CounterHTOff": "0,1,2,3", 285 "EventCode": "0xB7, 0xBB", 286 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 287 "MSRIndex": "0x1a6,0x1a7", 288 "MSRValue": "0x103FC00491", 289 "Offcore": "1", 290 "SampleAfterValue": "100003", 291 "UMask": "0x1" 292 }, 293 { 294 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 295 "Counter": "0,1,2,3", 296 "CounterHTOff": "0,1,2,3", 297 "EventCode": "0xB7, 0xBB", 298 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 299 "MSRIndex": "0x1a6,0x1a7", 300 "MSRValue": "0x83FC00491", 301 "Offcore": "1", 302 "SampleAfterValue": "100003", 303 "UMask": "0x1" 304 }, 305 { 306 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 307 "Counter": "0,1,2,3", 308 "CounterHTOff": "0,1,2,3", 309 "EventCode": "0xB7, 0xBB", 310 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 311 "MSRIndex": "0x1a6,0x1a7", 312 "MSRValue": "0x63FC00491", 313 "Offcore": "1", 314 "SampleAfterValue": "100003", 315 "UMask": "0x1" 316 }, 317 { 318 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", 319 "Counter": "0,1,2,3", 320 "CounterHTOff": "0,1,2,3", 321 "EventCode": "0xB7, 0xBB", 322 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 323 "MSRIndex": "0x1a6,0x1a7", 324 "MSRValue": "0x604000491", 325 "Offcore": "1", 326 "SampleAfterValue": "100003", 327 "UMask": "0x1" 328 }, 329 { 330 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", 331 "Counter": "0,1,2,3", 332 "CounterHTOff": "0,1,2,3", 333 "EventCode": "0xB7, 0xBB", 334 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 335 "MSRIndex": "0x1a6,0x1a7", 336 "MSRValue": "0x63B800491", 337 "Offcore": "1", 338 "SampleAfterValue": "100003", 339 "UMask": "0x1" 340 }, 341 { 342 "BriefDescription": "Counts all prefetch data reads that miss in the L3.", 343 "Counter": "0,1,2,3", 344 "CounterHTOff": "0,1,2,3", 345 "EventCode": "0xB7, 0xBB", 346 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 347 "MSRIndex": "0x1a6,0x1a7", 348 "MSRValue": "0x3FBC000490", 349 "Offcore": "1", 350 "SampleAfterValue": "100003", 351 "UMask": "0x1" 352 }, 353 { 354 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 355 "Counter": "0,1,2,3", 356 "CounterHTOff": "0,1,2,3", 357 "EventCode": "0xB7, 0xBB", 358 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 359 "MSRIndex": "0x1a6,0x1a7", 360 "MSRValue": "0x103FC00490", 361 "Offcore": "1", 362 "SampleAfterValue": "100003", 363 "UMask": "0x1" 364 }, 365 { 366 "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 367 "Counter": "0,1,2,3", 368 "CounterHTOff": "0,1,2,3", 369 "EventCode": "0xB7, 0xBB", 370 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 371 "MSRIndex": "0x1a6,0x1a7", 372 "MSRValue": "0x83FC00490", 373 "Offcore": "1", 374 "SampleAfterValue": "100003", 375 "UMask": "0x1" 376 }, 377 { 378 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 379 "Counter": "0,1,2,3", 380 "CounterHTOff": "0,1,2,3", 381 "EventCode": "0xB7, 0xBB", 382 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 383 "MSRIndex": "0x1a6,0x1a7", 384 "MSRValue": "0x63FC00490", 385 "Offcore": "1", 386 "SampleAfterValue": "100003", 387 "UMask": "0x1" 388 }, 389 { 390 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", 391 "Counter": "0,1,2,3", 392 "CounterHTOff": "0,1,2,3", 393 "EventCode": "0xB7, 0xBB", 394 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 395 "MSRIndex": "0x1a6,0x1a7", 396 "MSRValue": "0x604000490", 397 "Offcore": "1", 398 "SampleAfterValue": "100003", 399 "UMask": "0x1" 400 }, 401 { 402 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", 403 "Counter": "0,1,2,3", 404 "CounterHTOff": "0,1,2,3", 405 "EventCode": "0xB7, 0xBB", 406 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 407 "MSRIndex": "0x1a6,0x1a7", 408 "MSRValue": "0x63B800490", 409 "Offcore": "1", 410 "SampleAfterValue": "100003", 411 "UMask": "0x1" 412 }, 413 { 414 "BriefDescription": "Counts prefetch RFOs that miss in the L3.", 415 "Counter": "0,1,2,3", 416 "CounterHTOff": "0,1,2,3", 417 "EventCode": "0xB7, 0xBB", 418 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 419 "MSRIndex": "0x1a6,0x1a7", 420 "MSRValue": "0x3FBC000120", 421 "Offcore": "1", 422 "SampleAfterValue": "100003", 423 "UMask": "0x1" 424 }, 425 { 426 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 427 "Counter": "0,1,2,3", 428 "CounterHTOff": "0,1,2,3", 429 "EventCode": "0xB7, 0xBB", 430 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 431 "MSRIndex": "0x1a6,0x1a7", 432 "MSRValue": "0x103FC00120", 433 "Offcore": "1", 434 "SampleAfterValue": "100003", 435 "UMask": "0x1" 436 }, 437 { 438 "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 439 "Counter": "0,1,2,3", 440 "CounterHTOff": "0,1,2,3", 441 "EventCode": "0xB7, 0xBB", 442 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 443 "MSRIndex": "0x1a6,0x1a7", 444 "MSRValue": "0x83FC00120", 445 "Offcore": "1", 446 "SampleAfterValue": "100003", 447 "UMask": "0x1" 448 }, 449 { 450 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 451 "Counter": "0,1,2,3", 452 "CounterHTOff": "0,1,2,3", 453 "EventCode": "0xB7, 0xBB", 454 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 455 "MSRIndex": "0x1a6,0x1a7", 456 "MSRValue": "0x63FC00120", 457 "Offcore": "1", 458 "SampleAfterValue": "100003", 459 "UMask": "0x1" 460 }, 461 { 462 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", 463 "Counter": "0,1,2,3", 464 "CounterHTOff": "0,1,2,3", 465 "EventCode": "0xB7, 0xBB", 466 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 467 "MSRIndex": "0x1a6,0x1a7", 468 "MSRValue": "0x604000120", 469 "Offcore": "1", 470 "SampleAfterValue": "100003", 471 "UMask": "0x1" 472 }, 473 { 474 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", 475 "Counter": "0,1,2,3", 476 "CounterHTOff": "0,1,2,3", 477 "EventCode": "0xB7, 0xBB", 478 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 479 "MSRIndex": "0x1a6,0x1a7", 480 "MSRValue": "0x63B800120", 481 "Offcore": "1", 482 "SampleAfterValue": "100003", 483 "UMask": "0x1" 484 }, 485 { 486 "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", 487 "Counter": "0,1,2,3", 488 "CounterHTOff": "0,1,2,3", 489 "EventCode": "0xB7, 0xBB", 490 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", 491 "MSRIndex": "0x1a6,0x1a7", 492 "MSRValue": "0x3FBC000122", 493 "Offcore": "1", 494 "SampleAfterValue": "100003", 495 "UMask": "0x1" 496 }, 497 { 498 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 499 "Counter": "0,1,2,3", 500 "CounterHTOff": "0,1,2,3", 501 "EventCode": "0xB7, 0xBB", 502 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", 503 "MSRIndex": "0x1a6,0x1a7", 504 "MSRValue": "0x103FC00122", 505 "Offcore": "1", 506 "SampleAfterValue": "100003", 507 "UMask": "0x1" 508 }, 509 { 510 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 511 "Counter": "0,1,2,3", 512 "CounterHTOff": "0,1,2,3", 513 "EventCode": "0xB7, 0xBB", 514 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 515 "MSRIndex": "0x1a6,0x1a7", 516 "MSRValue": "0x83FC00122", 517 "Offcore": "1", 518 "SampleAfterValue": "100003", 519 "UMask": "0x1" 520 }, 521 { 522 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 523 "Counter": "0,1,2,3", 524 "CounterHTOff": "0,1,2,3", 525 "EventCode": "0xB7, 0xBB", 526 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 527 "MSRIndex": "0x1a6,0x1a7", 528 "MSRValue": "0x63FC00122", 529 "Offcore": "1", 530 "SampleAfterValue": "100003", 531 "UMask": "0x1" 532 }, 533 { 534 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", 535 "Counter": "0,1,2,3", 536 "CounterHTOff": "0,1,2,3", 537 "EventCode": "0xB7, 0xBB", 538 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 539 "MSRIndex": "0x1a6,0x1a7", 540 "MSRValue": "0x604000122", 541 "Offcore": "1", 542 "SampleAfterValue": "100003", 543 "UMask": "0x1" 544 }, 545 { 546 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", 547 "Counter": "0,1,2,3", 548 "CounterHTOff": "0,1,2,3", 549 "EventCode": "0xB7, 0xBB", 550 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 551 "MSRIndex": "0x1a6,0x1a7", 552 "MSRValue": "0x63B800122", 553 "Offcore": "1", 554 "SampleAfterValue": "100003", 555 "UMask": "0x1" 556 }, 557 { 558 "BriefDescription": "Counts all demand code reads that miss in the L3.", 559 "Counter": "0,1,2,3", 560 "CounterHTOff": "0,1,2,3", 561 "EventCode": "0xB7, 0xBB", 562 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 563 "MSRIndex": "0x1a6,0x1a7", 564 "MSRValue": "0x3FBC000004", 565 "Offcore": "1", 566 "SampleAfterValue": "100003", 567 "UMask": "0x1" 568 }, 569 { 570 "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", 571 "Counter": "0,1,2,3", 572 "CounterHTOff": "0,1,2,3", 573 "EventCode": "0xB7, 0xBB", 574 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 575 "MSRIndex": "0x1a6,0x1a7", 576 "MSRValue": "0x103FC00004", 577 "Offcore": "1", 578 "SampleAfterValue": "100003", 579 "UMask": "0x1" 580 }, 581 { 582 "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", 583 "Counter": "0,1,2,3", 584 "CounterHTOff": "0,1,2,3", 585 "EventCode": "0xB7, 0xBB", 586 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 587 "MSRIndex": "0x1a6,0x1a7", 588 "MSRValue": "0x83FC00004", 589 "Offcore": "1", 590 "SampleAfterValue": "100003", 591 "UMask": "0x1" 592 }, 593 { 594 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.", 595 "Counter": "0,1,2,3", 596 "CounterHTOff": "0,1,2,3", 597 "EventCode": "0xB7, 0xBB", 598 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 599 "MSRIndex": "0x1a6,0x1a7", 600 "MSRValue": "0x63FC00004", 601 "Offcore": "1", 602 "SampleAfterValue": "100003", 603 "UMask": "0x1" 604 }, 605 { 606 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.", 607 "Counter": "0,1,2,3", 608 "CounterHTOff": "0,1,2,3", 609 "EventCode": "0xB7, 0xBB", 610 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 611 "MSRIndex": "0x1a6,0x1a7", 612 "MSRValue": "0x604000004", 613 "Offcore": "1", 614 "SampleAfterValue": "100003", 615 "UMask": "0x1" 616 }, 617 { 618 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", 619 "Counter": "0,1,2,3", 620 "CounterHTOff": "0,1,2,3", 621 "EventCode": "0xB7, 0xBB", 622 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 623 "MSRIndex": "0x1a6,0x1a7", 624 "MSRValue": "0x63B800004", 625 "Offcore": "1", 626 "SampleAfterValue": "100003", 627 "UMask": "0x1" 628 }, 629 { 630 "BriefDescription": "Counts demand data reads that miss in the L3.", 631 "Counter": "0,1,2,3", 632 "CounterHTOff": "0,1,2,3", 633 "EventCode": "0xB7, 0xBB", 634 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 635 "MSRIndex": "0x1a6,0x1a7", 636 "MSRValue": "0x3FBC000001", 637 "Offcore": "1", 638 "SampleAfterValue": "100003", 639 "UMask": "0x1" 640 }, 641 { 642 "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", 643 "Counter": "0,1,2,3", 644 "CounterHTOff": "0,1,2,3", 645 "EventCode": "0xB7, 0xBB", 646 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 647 "MSRIndex": "0x1a6,0x1a7", 648 "MSRValue": "0x103FC00001", 649 "Offcore": "1", 650 "SampleAfterValue": "100003", 651 "UMask": "0x1" 652 }, 653 { 654 "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", 655 "Counter": "0,1,2,3", 656 "CounterHTOff": "0,1,2,3", 657 "EventCode": "0xB7, 0xBB", 658 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 659 "MSRIndex": "0x1a6,0x1a7", 660 "MSRValue": "0x83FC00001", 661 "Offcore": "1", 662 "SampleAfterValue": "100003", 663 "UMask": "0x1" 664 }, 665 { 666 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", 667 "Counter": "0,1,2,3", 668 "CounterHTOff": "0,1,2,3", 669 "EventCode": "0xB7, 0xBB", 670 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 671 "MSRIndex": "0x1a6,0x1a7", 672 "MSRValue": "0x63FC00001", 673 "Offcore": "1", 674 "SampleAfterValue": "100003", 675 "UMask": "0x1" 676 }, 677 { 678 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", 679 "Counter": "0,1,2,3", 680 "CounterHTOff": "0,1,2,3", 681 "EventCode": "0xB7, 0xBB", 682 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 683 "MSRIndex": "0x1a6,0x1a7", 684 "MSRValue": "0x604000001", 685 "Offcore": "1", 686 "SampleAfterValue": "100003", 687 "UMask": "0x1" 688 }, 689 { 690 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", 691 "Counter": "0,1,2,3", 692 "CounterHTOff": "0,1,2,3", 693 "EventCode": "0xB7, 0xBB", 694 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 695 "MSRIndex": "0x1a6,0x1a7", 696 "MSRValue": "0x63B800001", 697 "Offcore": "1", 698 "SampleAfterValue": "100003", 699 "UMask": "0x1" 700 }, 701 { 702 "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", 703 "Counter": "0,1,2,3", 704 "CounterHTOff": "0,1,2,3", 705 "EventCode": "0xB7, 0xBB", 706 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 707 "MSRIndex": "0x1a6,0x1a7", 708 "MSRValue": "0x3FBC000002", 709 "Offcore": "1", 710 "SampleAfterValue": "100003", 711 "UMask": "0x1" 712 }, 713 { 714 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", 715 "Counter": "0,1,2,3", 716 "CounterHTOff": "0,1,2,3", 717 "EventCode": "0xB7, 0xBB", 718 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", 719 "MSRIndex": "0x1a6,0x1a7", 720 "MSRValue": "0x103FC00002", 721 "Offcore": "1", 722 "SampleAfterValue": "100003", 723 "UMask": "0x1" 724 }, 725 { 726 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", 727 "Counter": "0,1,2,3", 728 "CounterHTOff": "0,1,2,3", 729 "EventCode": "0xB7, 0xBB", 730 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 731 "MSRIndex": "0x1a6,0x1a7", 732 "MSRValue": "0x83FC00002", 733 "Offcore": "1", 734 "SampleAfterValue": "100003", 735 "UMask": "0x1" 736 }, 737 { 738 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", 739 "Counter": "0,1,2,3", 740 "CounterHTOff": "0,1,2,3", 741 "EventCode": "0xB7, 0xBB", 742 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 743 "MSRIndex": "0x1a6,0x1a7", 744 "MSRValue": "0x63FC00002", 745 "Offcore": "1", 746 "SampleAfterValue": "100003", 747 "UMask": "0x1" 748 }, 749 { 750 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", 751 "Counter": "0,1,2,3", 752 "CounterHTOff": "0,1,2,3", 753 "EventCode": "0xB7, 0xBB", 754 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 755 "MSRIndex": "0x1a6,0x1a7", 756 "MSRValue": "0x604000002", 757 "Offcore": "1", 758 "SampleAfterValue": "100003", 759 "UMask": "0x1" 760 }, 761 { 762 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", 763 "Counter": "0,1,2,3", 764 "CounterHTOff": "0,1,2,3", 765 "EventCode": "0xB7, 0xBB", 766 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 767 "MSRIndex": "0x1a6,0x1a7", 768 "MSRValue": "0x63B800002", 769 "Offcore": "1", 770 "SampleAfterValue": "100003", 771 "UMask": "0x1" 772 }, 773 { 774 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", 775 "Counter": "0,1,2,3", 776 "CounterHTOff": "0,1,2,3", 777 "EventCode": "0xB7, 0xBB", 778 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 779 "MSRIndex": "0x1a6,0x1a7", 780 "MSRValue": "0x3FBC000400", 781 "Offcore": "1", 782 "SampleAfterValue": "100003", 783 "UMask": "0x1" 784 }, 785 { 786 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", 787 "Counter": "0,1,2,3", 788 "CounterHTOff": "0,1,2,3", 789 "EventCode": "0xB7, 0xBB", 790 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 791 "MSRIndex": "0x1a6,0x1a7", 792 "MSRValue": "0x103FC00400", 793 "Offcore": "1", 794 "SampleAfterValue": "100003", 795 "UMask": "0x1" 796 }, 797 { 798 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", 799 "Counter": "0,1,2,3", 800 "CounterHTOff": "0,1,2,3", 801 "EventCode": "0xB7, 0xBB", 802 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 803 "MSRIndex": "0x1a6,0x1a7", 804 "MSRValue": "0x83FC00400", 805 "Offcore": "1", 806 "SampleAfterValue": "100003", 807 "UMask": "0x1" 808 }, 809 { 810 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", 811 "Counter": "0,1,2,3", 812 "CounterHTOff": "0,1,2,3", 813 "EventCode": "0xB7, 0xBB", 814 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", 815 "MSRIndex": "0x1a6,0x1a7", 816 "MSRValue": "0x63FC00400", 817 "Offcore": "1", 818 "SampleAfterValue": "100003", 819 "UMask": "0x1" 820 }, 821 { 822 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", 823 "Counter": "0,1,2,3", 824 "CounterHTOff": "0,1,2,3", 825 "EventCode": "0xB7, 0xBB", 826 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 827 "MSRIndex": "0x1a6,0x1a7", 828 "MSRValue": "0x604000400", 829 "Offcore": "1", 830 "SampleAfterValue": "100003", 831 "UMask": "0x1" 832 }, 833 { 834 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", 835 "Counter": "0,1,2,3", 836 "CounterHTOff": "0,1,2,3", 837 "EventCode": "0xB7, 0xBB", 838 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 839 "MSRIndex": "0x1a6,0x1a7", 840 "MSRValue": "0x63B800400", 841 "Offcore": "1", 842 "SampleAfterValue": "100003", 843 "UMask": "0x1" 844 }, 845 { 846 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", 847 "Counter": "0,1,2,3", 848 "CounterHTOff": "0,1,2,3", 849 "EventCode": "0xB7, 0xBB", 850 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 851 "MSRIndex": "0x1a6,0x1a7", 852 "MSRValue": "0x3FBC000010", 853 "Offcore": "1", 854 "SampleAfterValue": "100003", 855 "UMask": "0x1" 856 }, 857 { 858 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", 859 "Counter": "0,1,2,3", 860 "CounterHTOff": "0,1,2,3", 861 "EventCode": "0xB7, 0xBB", 862 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 863 "MSRIndex": "0x1a6,0x1a7", 864 "MSRValue": "0x103FC00010", 865 "Offcore": "1", 866 "SampleAfterValue": "100003", 867 "UMask": "0x1" 868 }, 869 { 870 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 871 "Counter": "0,1,2,3", 872 "CounterHTOff": "0,1,2,3", 873 "EventCode": "0xB7, 0xBB", 874 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 875 "MSRIndex": "0x1a6,0x1a7", 876 "MSRValue": "0x83FC00010", 877 "Offcore": "1", 878 "SampleAfterValue": "100003", 879 "UMask": "0x1" 880 }, 881 { 882 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", 883 "Counter": "0,1,2,3", 884 "CounterHTOff": "0,1,2,3", 885 "EventCode": "0xB7, 0xBB", 886 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 887 "MSRIndex": "0x1a6,0x1a7", 888 "MSRValue": "0x63FC00010", 889 "Offcore": "1", 890 "SampleAfterValue": "100003", 891 "UMask": "0x1" 892 }, 893 { 894 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", 895 "Counter": "0,1,2,3", 896 "CounterHTOff": "0,1,2,3", 897 "EventCode": "0xB7, 0xBB", 898 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 899 "MSRIndex": "0x1a6,0x1a7", 900 "MSRValue": "0x604000010", 901 "Offcore": "1", 902 "SampleAfterValue": "100003", 903 "UMask": "0x1" 904 }, 905 { 906 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", 907 "Counter": "0,1,2,3", 908 "CounterHTOff": "0,1,2,3", 909 "EventCode": "0xB7, 0xBB", 910 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 911 "MSRIndex": "0x1a6,0x1a7", 912 "MSRValue": "0x63B800010", 913 "Offcore": "1", 914 "SampleAfterValue": "100003", 915 "UMask": "0x1" 916 }, 917 { 918 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", 919 "Counter": "0,1,2,3", 920 "CounterHTOff": "0,1,2,3", 921 "EventCode": "0xB7, 0xBB", 922 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", 923 "MSRIndex": "0x1a6,0x1a7", 924 "MSRValue": "0x3FBC000020", 925 "Offcore": "1", 926 "SampleAfterValue": "100003", 927 "UMask": "0x1" 928 }, 929 { 930 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", 931 "Counter": "0,1,2,3", 932 "CounterHTOff": "0,1,2,3", 933 "EventCode": "0xB7, 0xBB", 934 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", 935 "MSRIndex": "0x1a6,0x1a7", 936 "MSRValue": "0x103FC00020", 937 "Offcore": "1", 938 "SampleAfterValue": "100003", 939 "UMask": "0x1" 940 }, 941 { 942 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 943 "Counter": "0,1,2,3", 944 "CounterHTOff": "0,1,2,3", 945 "EventCode": "0xB7, 0xBB", 946 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 947 "MSRIndex": "0x1a6,0x1a7", 948 "MSRValue": "0x83FC00020", 949 "Offcore": "1", 950 "SampleAfterValue": "100003", 951 "UMask": "0x1" 952 }, 953 { 954 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", 955 "Counter": "0,1,2,3", 956 "CounterHTOff": "0,1,2,3", 957 "EventCode": "0xB7, 0xBB", 958 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 959 "MSRIndex": "0x1a6,0x1a7", 960 "MSRValue": "0x63FC00020", 961 "Offcore": "1", 962 "SampleAfterValue": "100003", 963 "UMask": "0x1" 964 }, 965 { 966 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", 967 "Counter": "0,1,2,3", 968 "CounterHTOff": "0,1,2,3", 969 "EventCode": "0xB7, 0xBB", 970 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 971 "MSRIndex": "0x1a6,0x1a7", 972 "MSRValue": "0x604000020", 973 "Offcore": "1", 974 "SampleAfterValue": "100003", 975 "UMask": "0x1" 976 }, 977 { 978 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", 979 "Counter": "0,1,2,3", 980 "CounterHTOff": "0,1,2,3", 981 "EventCode": "0xB7, 0xBB", 982 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 983 "MSRIndex": "0x1a6,0x1a7", 984 "MSRValue": "0x63B800020", 985 "Offcore": "1", 986 "SampleAfterValue": "100003", 987 "UMask": "0x1" 988 }, 989 { 990 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", 991 "Counter": "0,1,2,3", 992 "CounterHTOff": "0,1,2,3", 993 "EventCode": "0xB7, 0xBB", 994 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 995 "MSRIndex": "0x1a6,0x1a7", 996 "MSRValue": "0x3FBC000080", 997 "Offcore": "1", 998 "SampleAfterValue": "100003", 999 "UMask": "0x1" 1000 }, 1001 { 1002 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", 1003 "Counter": "0,1,2,3", 1004 "CounterHTOff": "0,1,2,3", 1005 "EventCode": "0xB7, 0xBB", 1006 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 1007 "MSRIndex": "0x1a6,0x1a7", 1008 "MSRValue": "0x103FC00080", 1009 "Offcore": "1", 1010 "SampleAfterValue": "100003", 1011 "UMask": "0x1" 1012 }, 1013 { 1014 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 1015 "Counter": "0,1,2,3", 1016 "CounterHTOff": "0,1,2,3", 1017 "EventCode": "0xB7, 0xBB", 1018 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 1019 "MSRIndex": "0x1a6,0x1a7", 1020 "MSRValue": "0x83FC00080", 1021 "Offcore": "1", 1022 "SampleAfterValue": "100003", 1023 "UMask": "0x1" 1024 }, 1025 { 1026 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", 1027 "Counter": "0,1,2,3", 1028 "CounterHTOff": "0,1,2,3", 1029 "EventCode": "0xB7, 0xBB", 1030 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1031 "MSRIndex": "0x1a6,0x1a7", 1032 "MSRValue": "0x63FC00080", 1033 "Offcore": "1", 1034 "SampleAfterValue": "100003", 1035 "UMask": "0x1" 1036 }, 1037 { 1038 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", 1039 "Counter": "0,1,2,3", 1040 "CounterHTOff": "0,1,2,3", 1041 "EventCode": "0xB7, 0xBB", 1042 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1043 "MSRIndex": "0x1a6,0x1a7", 1044 "MSRValue": "0x604000080", 1045 "Offcore": "1", 1046 "SampleAfterValue": "100003", 1047 "UMask": "0x1" 1048 }, 1049 { 1050 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", 1051 "Counter": "0,1,2,3", 1052 "CounterHTOff": "0,1,2,3", 1053 "EventCode": "0xB7, 0xBB", 1054 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1055 "MSRIndex": "0x1a6,0x1a7", 1056 "MSRValue": "0x63B800080", 1057 "Offcore": "1", 1058 "SampleAfterValue": "100003", 1059 "UMask": "0x1" 1060 }, 1061 { 1062 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", 1063 "Counter": "0,1,2,3", 1064 "CounterHTOff": "0,1,2,3", 1065 "EventCode": "0xB7, 0xBB", 1066 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", 1067 "MSRIndex": "0x1a6,0x1a7", 1068 "MSRValue": "0x3FBC000100", 1069 "Offcore": "1", 1070 "SampleAfterValue": "100003", 1071 "UMask": "0x1" 1072 }, 1073 { 1074 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", 1075 "Counter": "0,1,2,3", 1076 "CounterHTOff": "0,1,2,3", 1077 "EventCode": "0xB7, 0xBB", 1078 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", 1079 "MSRIndex": "0x1a6,0x1a7", 1080 "MSRValue": "0x103FC00100", 1081 "Offcore": "1", 1082 "SampleAfterValue": "100003", 1083 "UMask": "0x1" 1084 }, 1085 { 1086 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 1087 "Counter": "0,1,2,3", 1088 "CounterHTOff": "0,1,2,3", 1089 "EventCode": "0xB7, 0xBB", 1090 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 1091 "MSRIndex": "0x1a6,0x1a7", 1092 "MSRValue": "0x83FC00100", 1093 "Offcore": "1", 1094 "SampleAfterValue": "100003", 1095 "UMask": "0x1" 1096 }, 1097 { 1098 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", 1099 "Counter": "0,1,2,3", 1100 "CounterHTOff": "0,1,2,3", 1101 "EventCode": "0xB7, 0xBB", 1102 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1103 "MSRIndex": "0x1a6,0x1a7", 1104 "MSRValue": "0x63FC00100", 1105 "Offcore": "1", 1106 "SampleAfterValue": "100003", 1107 "UMask": "0x1" 1108 }, 1109 { 1110 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", 1111 "Counter": "0,1,2,3", 1112 "CounterHTOff": "0,1,2,3", 1113 "EventCode": "0xB7, 0xBB", 1114 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1115 "MSRIndex": "0x1a6,0x1a7", 1116 "MSRValue": "0x604000100", 1117 "Offcore": "1", 1118 "SampleAfterValue": "100003", 1119 "UMask": "0x1" 1120 }, 1121 { 1122 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", 1123 "Counter": "0,1,2,3", 1124 "CounterHTOff": "0,1,2,3", 1125 "EventCode": "0xB7, 0xBB", 1126 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1127 "MSRIndex": "0x1a6,0x1a7", 1128 "MSRValue": "0x63B800100", 1129 "Offcore": "1", 1130 "SampleAfterValue": "100003", 1131 "UMask": "0x1" 1132 }, 1133 { 1134 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 1135 "Counter": "0,1,2,3", 1136 "CounterHTOff": "0,1,2,3,4,5,6,7", 1137 "EventCode": "0xC9", 1138 "EventName": "RTM_RETIRED.ABORTED", 1139 "PEBS": "1", 1140 "PublicDescription": "Number of times RTM abort was triggered.", 1141 "SampleAfterValue": "2000003", 1142 "UMask": "0x4" 1143 }, 1144 { 1145 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 1146 "Counter": "0,1,2,3", 1147 "CounterHTOff": "0,1,2,3,4,5,6,7", 1148 "EventCode": "0xC9", 1149 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 1150 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 1151 "SampleAfterValue": "2000003", 1152 "UMask": "0x80" 1153 }, 1154 { 1155 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 1156 "Counter": "0,1,2,3", 1157 "CounterHTOff": "0,1,2,3,4,5,6,7", 1158 "EventCode": "0xC9", 1159 "EventName": "RTM_RETIRED.ABORTED_MEM", 1160 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 1161 "SampleAfterValue": "2000003", 1162 "UMask": "0x8" 1163 }, 1164 { 1165 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 1166 "Counter": "0,1,2,3", 1167 "CounterHTOff": "0,1,2,3,4,5,6,7", 1168 "EventCode": "0xC9", 1169 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 1170 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 1171 "SampleAfterValue": "2000003", 1172 "UMask": "0x40" 1173 }, 1174 { 1175 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 1176 "Counter": "0,1,2,3", 1177 "CounterHTOff": "0,1,2,3,4,5,6,7", 1178 "EventCode": "0xC9", 1179 "EventName": "RTM_RETIRED.ABORTED_TIMER", 1180 "SampleAfterValue": "2000003", 1181 "UMask": "0x10" 1182 }, 1183 { 1184 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 1185 "Counter": "0,1,2,3", 1186 "CounterHTOff": "0,1,2,3,4,5,6,7", 1187 "EventCode": "0xC9", 1188 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 1189 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 1190 "SampleAfterValue": "2000003", 1191 "UMask": "0x20" 1192 }, 1193 { 1194 "BriefDescription": "Number of times an RTM execution successfully committed", 1195 "Counter": "0,1,2,3", 1196 "CounterHTOff": "0,1,2,3,4,5,6,7", 1197 "EventCode": "0xC9", 1198 "EventName": "RTM_RETIRED.COMMIT", 1199 "PublicDescription": "Number of times RTM commit succeeded.", 1200 "SampleAfterValue": "2000003", 1201 "UMask": "0x2" 1202 }, 1203 { 1204 "BriefDescription": "Number of times an RTM execution started.", 1205 "Counter": "0,1,2,3", 1206 "CounterHTOff": "0,1,2,3,4,5,6,7", 1207 "EventCode": "0xC9", 1208 "EventName": "RTM_RETIRED.START", 1209 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 1210 "SampleAfterValue": "2000003", 1211 "UMask": "0x1" 1212 }, 1213 { 1214 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 1215 "Counter": "0,1,2,3", 1216 "CounterHTOff": "0,1,2,3,4,5,6,7", 1217 "EventCode": "0x5d", 1218 "EventName": "TX_EXEC.MISC1", 1219 "SampleAfterValue": "2000003", 1220 "UMask": "0x1" 1221 }, 1222 { 1223 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 1224 "Counter": "0,1,2,3", 1225 "CounterHTOff": "0,1,2,3,4,5,6,7", 1226 "EventCode": "0x5d", 1227 "EventName": "TX_EXEC.MISC2", 1228 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 1229 "SampleAfterValue": "2000003", 1230 "UMask": "0x2" 1231 }, 1232 { 1233 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 1234 "Counter": "0,1,2,3", 1235 "CounterHTOff": "0,1,2,3,4,5,6,7", 1236 "EventCode": "0x5d", 1237 "EventName": "TX_EXEC.MISC3", 1238 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 1239 "SampleAfterValue": "2000003", 1240 "UMask": "0x4" 1241 }, 1242 { 1243 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 1244 "Counter": "0,1,2,3", 1245 "CounterHTOff": "0,1,2,3,4,5,6,7", 1246 "EventCode": "0x5d", 1247 "EventName": "TX_EXEC.MISC4", 1248 "PublicDescription": "RTM region detected inside HLE.", 1249 "SampleAfterValue": "2000003", 1250 "UMask": "0x8" 1251 }, 1252 { 1253 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 1254 "Counter": "0,1,2,3", 1255 "CounterHTOff": "0,1,2,3,4,5,6,7", 1256 "EventCode": "0x5d", 1257 "EventName": "TX_EXEC.MISC5", 1258 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 1259 "SampleAfterValue": "2000003", 1260 "UMask": "0x10" 1261 }, 1262 { 1263 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 1264 "Counter": "0,1,2,3", 1265 "CounterHTOff": "0,1,2,3,4,5,6,7", 1266 "EventCode": "0x54", 1267 "EventName": "TX_MEM.ABORT_CAPACITY", 1268 "SampleAfterValue": "2000003", 1269 "UMask": "0x2" 1270 }, 1271 { 1272 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 1273 "Counter": "0,1,2,3", 1274 "CounterHTOff": "0,1,2,3,4,5,6,7", 1275 "EventCode": "0x54", 1276 "EventName": "TX_MEM.ABORT_CONFLICT", 1277 "PublicDescription": "Number of times a TSX line had a cache conflict.", 1278 "SampleAfterValue": "2000003", 1279 "UMask": "0x1" 1280 }, 1281 { 1282 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 1283 "Counter": "0,1,2,3", 1284 "CounterHTOff": "0,1,2,3,4,5,6,7", 1285 "EventCode": "0x54", 1286 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 1287 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 1288 "SampleAfterValue": "2000003", 1289 "UMask": "0x10" 1290 }, 1291 { 1292 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 1293 "Counter": "0,1,2,3", 1294 "CounterHTOff": "0,1,2,3,4,5,6,7", 1295 "EventCode": "0x54", 1296 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 1297 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 1298 "SampleAfterValue": "2000003", 1299 "UMask": "0x8" 1300 }, 1301 { 1302 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 1303 "Counter": "0,1,2,3", 1304 "CounterHTOff": "0,1,2,3,4,5,6,7", 1305 "EventCode": "0x54", 1306 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 1307 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 1308 "SampleAfterValue": "2000003", 1309 "UMask": "0x20" 1310 }, 1311 { 1312 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 1313 "Counter": "0,1,2,3", 1314 "CounterHTOff": "0,1,2,3,4,5,6,7", 1315 "EventCode": "0x54", 1316 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 1317 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 1318 "SampleAfterValue": "2000003", 1319 "UMask": "0x4" 1320 }, 1321 { 1322 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 1323 "Counter": "0,1,2,3", 1324 "CounterHTOff": "0,1,2,3,4,5,6,7", 1325 "EventCode": "0x54", 1326 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 1327 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 1328 "SampleAfterValue": "2000003", 1329 "UMask": "0x40" 1330 } 1331] 1332