1[ 2 { 3 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3", 6 "EventCode": "0xB7, 0xBB", 7 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8 "MSRIndex": "0x1a6,0x1a7", 9 "MSRValue": "0x063B800122", 10 "Offcore": "1", 11 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 12 "SampleAfterValue": "100003", 13 "UMask": "0x1" 14 }, 15 { 16 "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", 17 "Counter": "0,1,2,3", 18 "CounterHTOff": "0,1,2,3", 19 "EventCode": "0xB7, 0xBB", 20 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", 21 "MSRIndex": "0x1a6,0x1a7", 22 "MSRValue": "0x3FBC000122", 23 "Offcore": "1", 24 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 25 "SampleAfterValue": "100003", 26 "UMask": "0x1" 27 }, 28 { 29 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 30 "Counter": "0,1,2,3", 31 "CounterHTOff": "0,1,2,3,4,5,6,7", 32 "CounterMask": "6", 33 "EventCode": "0x60", 34 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 35 "SampleAfterValue": "2000003", 36 "UMask": "0x10" 37 }, 38 { 39 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", 40 "Counter": "0,1,2,3", 41 "CounterHTOff": "0,1,2,3", 42 "EventCode": "0xB7, 0xBB", 43 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 44 "MSRIndex": "0x1a6,0x1a7", 45 "MSRValue": "0x063B800020", 46 "Offcore": "1", 47 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 48 "SampleAfterValue": "100003", 49 "UMask": "0x1" 50 }, 51 { 52 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", 53 "Counter": "0,1,2,3", 54 "CounterHTOff": "0,1,2,3", 55 "EventCode": "0xB7, 0xBB", 56 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", 57 "MSRIndex": "0x1a6,0x1a7", 58 "MSRValue": "0x3FBC000100", 59 "Offcore": "1", 60 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 61 "SampleAfterValue": "100003", 62 "UMask": "0x1" 63 }, 64 { 65 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", 66 "Counter": "0,1,2,3", 67 "CounterHTOff": "0,1,2,3", 68 "EventCode": "0xB7, 0xBB", 69 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", 70 "MSRIndex": "0x1a6,0x1a7", 71 "MSRValue": "0x103FC00002", 72 "Offcore": "1", 73 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 74 "SampleAfterValue": "100003", 75 "UMask": "0x1" 76 }, 77 { 78 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 79 "Counter": "0,1,2,3", 80 "CounterHTOff": "0,1,2,3,4,5,6,7", 81 "EventCode": "0xC8", 82 "EventName": "HLE_RETIRED.ABORTED_TIMER", 83 "SampleAfterValue": "2000003", 84 "UMask": "0x10" 85 }, 86 { 87 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", 88 "Counter": "0,1,2,3", 89 "CounterHTOff": "0,1,2,3", 90 "EventCode": "0xB7, 0xBB", 91 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 92 "MSRIndex": "0x1a6,0x1a7", 93 "MSRValue": "0x063B800490", 94 "Offcore": "1", 95 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 96 "SampleAfterValue": "100003", 97 "UMask": "0x1" 98 }, 99 { 100 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 101 "Counter": "0,1,2,3", 102 "CounterHTOff": "0,1,2,3,4,5,6,7", 103 "EventCode": "0xC9", 104 "EventName": "RTM_RETIRED.ABORTED_MEM", 105 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 106 "SampleAfterValue": "2000003", 107 "UMask": "0x8" 108 }, 109 { 110 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", 111 "Counter": "0,1,2,3", 112 "CounterHTOff": "0,1,2,3", 113 "EventCode": "0xB7, 0xBB", 114 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 115 "MSRIndex": "0x1a6,0x1a7", 116 "MSRValue": "0x063B800004", 117 "Offcore": "1", 118 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 119 "SampleAfterValue": "100003", 120 "UMask": "0x1" 121 }, 122 { 123 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 124 "Counter": "0,1,2,3", 125 "CounterHTOff": "0,1,2,3,4,5,6,7", 126 "EventCode": "0xC9", 127 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 128 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 129 "SampleAfterValue": "2000003", 130 "UMask": "0x40" 131 }, 132 { 133 "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", 134 "Counter": "0,1,2,3", 135 "CounterHTOff": "0,1,2,3", 136 "EventCode": "0xB7, 0xBB", 137 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 138 "MSRIndex": "0x1a6,0x1a7", 139 "MSRValue": "0x3FBC000002", 140 "Offcore": "1", 141 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 142 "SampleAfterValue": "100003", 143 "UMask": "0x1" 144 }, 145 { 146 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 147 "Counter": "0,1,2,3", 148 "CounterHTOff": "0,1,2,3", 149 "EventCode": "0xB7, 0xBB", 150 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 151 "MSRIndex": "0x1a6,0x1a7", 152 "MSRValue": "0x063FC00120", 153 "Offcore": "1", 154 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 155 "SampleAfterValue": "100003", 156 "UMask": "0x1" 157 }, 158 { 159 "BriefDescription": "Counts all prefetch data reads that miss in the L3.", 160 "Counter": "0,1,2,3", 161 "CounterHTOff": "0,1,2,3", 162 "EventCode": "0xB7, 0xBB", 163 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 164 "MSRIndex": "0x1a6,0x1a7", 165 "MSRValue": "0x3FBC000490", 166 "Offcore": "1", 167 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 168 "SampleAfterValue": "100003", 169 "UMask": "0x1" 170 }, 171 { 172 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", 173 "Counter": "0,1,2,3", 174 "CounterHTOff": "0,1,2,3", 175 "EventCode": "0xB7, 0xBB", 176 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 177 "MSRIndex": "0x1a6,0x1a7", 178 "MSRValue": "0x0604000120", 179 "Offcore": "1", 180 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 181 "SampleAfterValue": "100003", 182 "UMask": "0x1" 183 }, 184 { 185 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", 186 "Counter": "0,1,2,3", 187 "CounterHTOff": "0,1,2,3", 188 "EventCode": "0xB7, 0xBB", 189 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 190 "MSRIndex": "0x1a6,0x1a7", 191 "MSRValue": "0x0604000490", 192 "Offcore": "1", 193 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 194 "SampleAfterValue": "100003", 195 "UMask": "0x1" 196 }, 197 { 198 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 199 "Counter": "0,1,2,3", 200 "CounterHTOff": "0,1,2,3,4,5,6,7", 201 "CounterMask": "2", 202 "EventCode": "0xA3", 203 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 204 "SampleAfterValue": "2000003", 205 "UMask": "0x2" 206 }, 207 { 208 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", 209 "Counter": "0,1,2,3", 210 "CounterHTOff": "0,1,2,3", 211 "EventCode": "0xB7, 0xBB", 212 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 213 "MSRIndex": "0x1a6,0x1a7", 214 "MSRValue": "0x0604000491", 215 "Offcore": "1", 216 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 217 "SampleAfterValue": "100003", 218 "UMask": "0x1" 219 }, 220 { 221 "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", 222 "Counter": "0,1,2,3", 223 "CounterHTOff": "0,1,2,3", 224 "EventCode": "0xB7, 0xBB", 225 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 226 "MSRIndex": "0x1a6,0x1a7", 227 "MSRValue": "0x083FC00004", 228 "Offcore": "1", 229 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 230 "SampleAfterValue": "100003", 231 "UMask": "0x1" 232 }, 233 { 234 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.", 235 "Counter": "0,1,2,3", 236 "CounterHTOff": "0,1,2,3", 237 "EventCode": "0xB7, 0xBB", 238 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 239 "MSRIndex": "0x1a6,0x1a7", 240 "MSRValue": "0x063FC00004", 241 "Offcore": "1", 242 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 243 "SampleAfterValue": "100003", 244 "UMask": "0x1" 245 }, 246 { 247 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 248 "Counter": "0,1,2,3", 249 "CounterHTOff": "0,1,2,3", 250 "Data_LA": "1", 251 "EventCode": "0xcd", 252 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 253 "MSRIndex": "0x3F6", 254 "MSRValue": "0x20", 255 "PEBS": "2", 256 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 257 "SampleAfterValue": "100007", 258 "TakenAlone": "1", 259 "UMask": "0x1" 260 }, 261 { 262 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", 263 "Counter": "0,1,2,3", 264 "CounterHTOff": "0,1,2,3", 265 "EventCode": "0xB7, 0xBB", 266 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", 267 "MSRIndex": "0x1a6,0x1a7", 268 "MSRValue": "0x103FC00020", 269 "Offcore": "1", 270 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 271 "SampleAfterValue": "100003", 272 "UMask": "0x1" 273 }, 274 { 275 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 276 "Counter": "0,1,2,3", 277 "CounterHTOff": "0,1,2,3", 278 "EventCode": "0xB7, 0xBB", 279 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 280 "MSRIndex": "0x1a6,0x1a7", 281 "MSRValue": "0x103FC00490", 282 "Offcore": "1", 283 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 284 "SampleAfterValue": "100003", 285 "UMask": "0x1" 286 }, 287 { 288 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", 289 "Counter": "0,1,2,3", 290 "CounterHTOff": "0,1,2,3", 291 "EventCode": "0xB7, 0xBB", 292 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", 293 "MSRIndex": "0x1a6,0x1a7", 294 "MSRValue": "0x3FBC000020", 295 "Offcore": "1", 296 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 297 "SampleAfterValue": "100003", 298 "UMask": "0x1" 299 }, 300 { 301 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 302 "Counter": "0,1,2,3", 303 "CounterHTOff": "0,1,2,3,4,5,6,7", 304 "EventCode": "0x54", 305 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 306 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 307 "SampleAfterValue": "2000003", 308 "UMask": "0x4" 309 }, 310 { 311 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 312 "Counter": "0,1,2,3", 313 "CounterHTOff": "0,1,2,3,4,5,6,7", 314 "EventCode": "0x54", 315 "EventName": "TX_MEM.ABORT_CONFLICT", 316 "PublicDescription": "Number of times a TSX line had a cache conflict.", 317 "SampleAfterValue": "2000003", 318 "UMask": "0x1" 319 }, 320 { 321 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", 322 "Counter": "0,1,2,3", 323 "CounterHTOff": "0,1,2,3", 324 "EventCode": "0xB7, 0xBB", 325 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 326 "MSRIndex": "0x1a6,0x1a7", 327 "MSRValue": "0x3FBC000400", 328 "Offcore": "1", 329 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 330 "SampleAfterValue": "100003", 331 "UMask": "0x1" 332 }, 333 { 334 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 335 "Counter": "0,1,2,3", 336 "CounterHTOff": "0,1,2,3", 337 "Data_LA": "1", 338 "EventCode": "0xcd", 339 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 340 "MSRIndex": "0x3F6", 341 "MSRValue": "0x40", 342 "PEBS": "2", 343 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 344 "SampleAfterValue": "2003", 345 "TakenAlone": "1", 346 "UMask": "0x1" 347 }, 348 { 349 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", 350 "Counter": "0,1,2,3", 351 "CounterHTOff": "0,1,2,3", 352 "EventCode": "0xB7, 0xBB", 353 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 354 "MSRIndex": "0x1a6,0x1a7", 355 "MSRValue": "0x083FC00002", 356 "Offcore": "1", 357 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 358 "SampleAfterValue": "100003", 359 "UMask": "0x1" 360 }, 361 { 362 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 363 "Counter": "0,1,2,3", 364 "CounterHTOff": "0,1,2,3,4,5,6,7", 365 "EventCode": "0xC8", 366 "EventName": "HLE_RETIRED.ABORTED_MEM", 367 "SampleAfterValue": "2000003", 368 "UMask": "0x8" 369 }, 370 { 371 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 372 "Counter": "0,1,2,3", 373 "CounterHTOff": "0,1,2,3,4,5,6,7", 374 "EventCode": "0x54", 375 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 376 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 377 "SampleAfterValue": "2000003", 378 "UMask": "0x8" 379 }, 380 { 381 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", 382 "Counter": "0,1,2,3", 383 "CounterHTOff": "0,1,2,3", 384 "EventCode": "0xB7, 0xBB", 385 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 386 "MSRIndex": "0x1a6,0x1a7", 387 "MSRValue": "0x103FC00080", 388 "Offcore": "1", 389 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 390 "SampleAfterValue": "100003", 391 "UMask": "0x1" 392 }, 393 { 394 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 395 "Counter": "0,1,2,3", 396 "CounterHTOff": "0,1,2,3,4,5,6,7", 397 "EventCode": "0x5d", 398 "EventName": "TX_EXEC.MISC5", 399 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 400 "SampleAfterValue": "2000003", 401 "UMask": "0x10" 402 }, 403 { 404 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 405 "Counter": "0,1,2,3", 406 "CounterHTOff": "0,1,2,3,4,5,6,7", 407 "EventCode": "0x5d", 408 "EventName": "TX_EXEC.MISC4", 409 "PublicDescription": "RTM region detected inside HLE.", 410 "SampleAfterValue": "2000003", 411 "UMask": "0x8" 412 }, 413 { 414 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 415 "Counter": "0,1,2,3", 416 "CounterHTOff": "0,1,2,3,4,5,6,7", 417 "EventCode": "0x5d", 418 "EventName": "TX_EXEC.MISC3", 419 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 420 "SampleAfterValue": "2000003", 421 "UMask": "0x4" 422 }, 423 { 424 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 425 "Counter": "0,1,2,3", 426 "CounterHTOff": "0,1,2,3,4,5,6,7", 427 "EventCode": "0x5d", 428 "EventName": "TX_EXEC.MISC2", 429 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 430 "SampleAfterValue": "2000003", 431 "UMask": "0x2" 432 }, 433 { 434 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 435 "Counter": "0,1,2,3", 436 "CounterHTOff": "0,1,2,3,4,5,6,7", 437 "EventCode": "0x5d", 438 "EventName": "TX_EXEC.MISC1", 439 "SampleAfterValue": "2000003", 440 "UMask": "0x1" 441 }, 442 { 443 "BriefDescription": "Number of times an RTM execution successfully committed", 444 "Counter": "0,1,2,3", 445 "CounterHTOff": "0,1,2,3,4,5,6,7", 446 "EventCode": "0xC9", 447 "EventName": "RTM_RETIRED.COMMIT", 448 "PublicDescription": "Number of times RTM commit succeeded.", 449 "SampleAfterValue": "2000003", 450 "UMask": "0x2" 451 }, 452 { 453 "BriefDescription": "Counts prefetch RFOs that miss in the L3.", 454 "Counter": "0,1,2,3", 455 "CounterHTOff": "0,1,2,3", 456 "EventCode": "0xB7, 0xBB", 457 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 458 "MSRIndex": "0x1a6,0x1a7", 459 "MSRValue": "0x3FBC000120", 460 "Offcore": "1", 461 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 462 "SampleAfterValue": "100003", 463 "UMask": "0x1" 464 }, 465 { 466 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 467 "Counter": "0,1,2,3", 468 "CounterHTOff": "0,1,2,3,4,5,6,7", 469 "EventCode": "0x60", 470 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 471 "SampleAfterValue": "2000003", 472 "UMask": "0x10" 473 }, 474 { 475 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", 476 "Counter": "0,1,2,3", 477 "CounterHTOff": "0,1,2,3", 478 "EventCode": "0xB7, 0xBB", 479 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 480 "MSRIndex": "0x1a6,0x1a7", 481 "MSRValue": "0x063B800491", 482 "Offcore": "1", 483 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 484 "SampleAfterValue": "100003", 485 "UMask": "0x1" 486 }, 487 { 488 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", 489 "Counter": "0,1,2,3", 490 "CounterHTOff": "0,1,2,3", 491 "EventCode": "0xB7, 0xBB", 492 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 493 "MSRIndex": "0x1a6,0x1a7", 494 "MSRValue": "0x063B800080", 495 "Offcore": "1", 496 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 497 "SampleAfterValue": "100003", 498 "UMask": "0x1" 499 }, 500 { 501 "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 502 "Counter": "0,1,2,3", 503 "CounterHTOff": "0,1,2,3", 504 "EventCode": "0xB7, 0xBB", 505 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 506 "MSRIndex": "0x1a6,0x1a7", 507 "MSRValue": "0x083FC00490", 508 "Offcore": "1", 509 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 510 "SampleAfterValue": "100003", 511 "UMask": "0x1" 512 }, 513 { 514 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", 515 "Counter": "0,1,2,3", 516 "CounterHTOff": "0,1,2,3", 517 "EventCode": "0xB7, 0xBB", 518 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 519 "MSRIndex": "0x1a6,0x1a7", 520 "MSRValue": "0x0604000010", 521 "Offcore": "1", 522 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 523 "SampleAfterValue": "100003", 524 "UMask": "0x1" 525 }, 526 { 527 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 528 "Counter": "0,1,2,3", 529 "CounterHTOff": "0,1,2,3,4,5,6,7", 530 "EventCode": "0xC9", 531 "EventName": "RTM_RETIRED.ABORTED_TIMER", 532 "SampleAfterValue": "2000003", 533 "UMask": "0x10" 534 }, 535 { 536 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", 537 "Counter": "0,1,2,3", 538 "CounterHTOff": "0,1,2,3", 539 "EventCode": "0xB7, 0xBB", 540 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 541 "MSRIndex": "0x1a6,0x1a7", 542 "MSRValue": "0x063FC00020", 543 "Offcore": "1", 544 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 545 "SampleAfterValue": "100003", 546 "UMask": "0x1" 547 }, 548 { 549 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", 550 "Counter": "0,1,2,3", 551 "CounterHTOff": "0,1,2,3", 552 "EventCode": "0xB7, 0xBB", 553 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 554 "MSRIndex": "0x1a6,0x1a7", 555 "MSRValue": "0x063FC00002", 556 "Offcore": "1", 557 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 558 "SampleAfterValue": "100003", 559 "UMask": "0x1" 560 }, 561 { 562 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 563 "Counter": "0,1,2,3", 564 "CounterHTOff": "0,1,2,3", 565 "EventCode": "0xB7, 0xBB", 566 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 567 "MSRIndex": "0x1a6,0x1a7", 568 "MSRValue": "0x063FC00490", 569 "Offcore": "1", 570 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 571 "SampleAfterValue": "100003", 572 "UMask": "0x1" 573 }, 574 { 575 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", 576 "Counter": "0,1,2,3", 577 "CounterHTOff": "0,1,2,3", 578 "EventCode": "0xB7, 0xBB", 579 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 580 "MSRIndex": "0x1a6,0x1a7", 581 "MSRValue": "0x063B800100", 582 "Offcore": "1", 583 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 584 "SampleAfterValue": "100003", 585 "UMask": "0x1" 586 }, 587 { 588 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", 589 "Counter": "0,1,2,3", 590 "CounterHTOff": "0,1,2,3", 591 "EventCode": "0xB7, 0xBB", 592 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 593 "MSRIndex": "0x1a6,0x1a7", 594 "MSRValue": "0x103FC00010", 595 "Offcore": "1", 596 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 597 "SampleAfterValue": "100003", 598 "UMask": "0x1" 599 }, 600 { 601 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", 602 "Counter": "0,1,2,3", 603 "CounterHTOff": "0,1,2,3", 604 "EventCode": "0xB7, 0xBB", 605 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 606 "MSRIndex": "0x1a6,0x1a7", 607 "MSRValue": "0x063FC00010", 608 "Offcore": "1", 609 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 610 "SampleAfterValue": "100003", 611 "UMask": "0x1" 612 }, 613 { 614 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 615 "Counter": "0,1,2,3", 616 "CounterHTOff": "0,1,2,3,4,5,6,7", 617 "EventCode": "0xC8", 618 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 619 "SampleAfterValue": "2000003", 620 "UMask": "0x20" 621 }, 622 { 623 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", 624 "Counter": "0,1,2,3", 625 "CounterHTOff": "0,1,2,3", 626 "EventCode": "0xB7, 0xBB", 627 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 628 "MSRIndex": "0x1a6,0x1a7", 629 "MSRValue": "0x063B800400", 630 "Offcore": "1", 631 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 632 "SampleAfterValue": "100003", 633 "UMask": "0x1" 634 }, 635 { 636 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 637 "Counter": "0,1,2,3", 638 "CounterHTOff": "0,1,2,3", 639 "EventCode": "0xB7, 0xBB", 640 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 641 "MSRIndex": "0x1a6,0x1a7", 642 "MSRValue": "0x083FC00122", 643 "Offcore": "1", 644 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 645 "SampleAfterValue": "100003", 646 "UMask": "0x1" 647 }, 648 { 649 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 650 "Counter": "0,1,2,3", 651 "CounterHTOff": "0,1,2,3", 652 "EventCode": "0xB7, 0xBB", 653 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", 654 "MSRIndex": "0x1a6,0x1a7", 655 "MSRValue": "0x103FC00122", 656 "Offcore": "1", 657 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 658 "SampleAfterValue": "100003", 659 "UMask": "0x1" 660 }, 661 { 662 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", 663 "Counter": "0,1,2,3", 664 "CounterHTOff": "0,1,2,3", 665 "EventCode": "0xB7, 0xBB", 666 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 667 "MSRIndex": "0x1a6,0x1a7", 668 "MSRValue": "0x063B800001", 669 "Offcore": "1", 670 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 671 "SampleAfterValue": "100003", 672 "UMask": "0x1" 673 }, 674 { 675 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", 676 "Counter": "0,1,2,3", 677 "CounterHTOff": "0,1,2,3", 678 "EventCode": "0xB7, 0xBB", 679 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 680 "MSRIndex": "0x1a6,0x1a7", 681 "MSRValue": "0x0604000001", 682 "Offcore": "1", 683 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 684 "SampleAfterValue": "100003", 685 "UMask": "0x1" 686 }, 687 { 688 "BriefDescription": "Number of times an HLE execution successfully committed", 689 "Counter": "0,1,2,3", 690 "CounterHTOff": "0,1,2,3,4,5,6,7", 691 "EventCode": "0xC8", 692 "EventName": "HLE_RETIRED.COMMIT", 693 "PublicDescription": "Number of times HLE commit succeeded.", 694 "SampleAfterValue": "2000003", 695 "UMask": "0x2" 696 }, 697 { 698 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 699 "Counter": "0,1,2,3", 700 "CounterHTOff": "0,1,2,3,4,5,6,7", 701 "EventCode": "0x54", 702 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 703 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 704 "SampleAfterValue": "2000003", 705 "UMask": "0x40" 706 }, 707 { 708 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 709 "Counter": "0,1,2,3", 710 "CounterHTOff": "0,1,2,3", 711 "EventCode": "0xB7, 0xBB", 712 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 713 "MSRIndex": "0x1a6,0x1a7", 714 "MSRValue": "0x083FC00100", 715 "Offcore": "1", 716 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 717 "SampleAfterValue": "100003", 718 "UMask": "0x1" 719 }, 720 { 721 "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", 722 "Counter": "0,1,2,3", 723 "CounterHTOff": "0,1,2,3", 724 "EventCode": "0xB7, 0xBB", 725 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 726 "MSRIndex": "0x1a6,0x1a7", 727 "MSRValue": "0x103FC00001", 728 "Offcore": "1", 729 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 730 "SampleAfterValue": "100003", 731 "UMask": "0x1" 732 }, 733 { 734 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", 735 "Counter": "0,1,2,3", 736 "CounterHTOff": "0,1,2,3", 737 "EventCode": "0xB7, 0xBB", 738 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 739 "MSRIndex": "0x1a6,0x1a7", 740 "MSRValue": "0x0604000020", 741 "Offcore": "1", 742 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 743 "SampleAfterValue": "100003", 744 "UMask": "0x1" 745 }, 746 { 747 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 748 "Counter": "0,1,2,3", 749 "CounterHTOff": "0,1,2,3", 750 "EventCode": "0xB7, 0xBB", 751 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 752 "MSRIndex": "0x1a6,0x1a7", 753 "MSRValue": "0x083FC00080", 754 "Offcore": "1", 755 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 756 "SampleAfterValue": "100003", 757 "UMask": "0x1" 758 }, 759 { 760 "BriefDescription": "Demand Data Read requests who miss L3 cache", 761 "Counter": "0,1,2,3", 762 "CounterHTOff": "0,1,2,3,4,5,6,7", 763 "EventCode": "0xB0", 764 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 765 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 766 "SampleAfterValue": "100003", 767 "UMask": "0x10" 768 }, 769 { 770 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", 771 "Counter": "0,1,2,3", 772 "CounterHTOff": "0,1,2,3", 773 "EventCode": "0xB7, 0xBB", 774 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 775 "MSRIndex": "0x1a6,0x1a7", 776 "MSRValue": "0x063FC00080", 777 "Offcore": "1", 778 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 779 "SampleAfterValue": "100003", 780 "UMask": "0x1" 781 }, 782 { 783 "BriefDescription": "Counts demand data reads that miss in the L3.", 784 "Counter": "0,1,2,3", 785 "CounterHTOff": "0,1,2,3", 786 "EventCode": "0xB7, 0xBB", 787 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 788 "MSRIndex": "0x1a6,0x1a7", 789 "MSRValue": "0x3FBC000001", 790 "Offcore": "1", 791 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 792 "SampleAfterValue": "100003", 793 "UMask": "0x1" 794 }, 795 { 796 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 797 "Counter": "0,1,2,3", 798 "CounterHTOff": "0,1,2,3,4,5,6,7", 799 "EventCode": "0xC9", 800 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 801 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 802 "SampleAfterValue": "2000003", 803 "UMask": "0x20" 804 }, 805 { 806 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 807 "Counter": "0,1,2,3", 808 "CounterHTOff": "0,1,2,3", 809 "EventCode": "0xB7, 0xBB", 810 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 811 "MSRIndex": "0x1a6,0x1a7", 812 "MSRValue": "0x083FC00010", 813 "Offcore": "1", 814 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 815 "SampleAfterValue": "100003", 816 "UMask": "0x1" 817 }, 818 { 819 "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 820 "Counter": "0,1,2,3", 821 "CounterHTOff": "0,1,2,3", 822 "EventCode": "0xB7, 0xBB", 823 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 824 "MSRIndex": "0x1a6,0x1a7", 825 "MSRValue": "0x083FC00120", 826 "Offcore": "1", 827 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 828 "SampleAfterValue": "100003", 829 "UMask": "0x1" 830 }, 831 { 832 "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", 833 "Counter": "0,1,2,3", 834 "CounterHTOff": "0,1,2,3", 835 "EventCode": "0xB7, 0xBB", 836 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 837 "MSRIndex": "0x1a6,0x1a7", 838 "MSRValue": "0x103FC00004", 839 "Offcore": "1", 840 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 841 "SampleAfterValue": "100003", 842 "UMask": "0x1" 843 }, 844 { 845 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", 846 "Counter": "0,1,2,3", 847 "CounterHTOff": "0,1,2,3", 848 "EventCode": "0xB7, 0xBB", 849 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", 850 "MSRIndex": "0x1a6,0x1a7", 851 "MSRValue": "0x103FC00100", 852 "Offcore": "1", 853 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 854 "SampleAfterValue": "100003", 855 "UMask": "0x1" 856 }, 857 { 858 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 859 "Counter": "0,1,2,3", 860 "CounterHTOff": "0,1,2,3", 861 "Data_LA": "1", 862 "EventCode": "0xcd", 863 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 864 "MSRIndex": "0x3F6", 865 "MSRValue": "0x100", 866 "PEBS": "2", 867 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 868 "SampleAfterValue": "503", 869 "TakenAlone": "1", 870 "UMask": "0x1" 871 }, 872 { 873 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 874 "Counter": "0,1,2,3", 875 "CounterHTOff": "0,1,2,3", 876 "EventCode": "0xB7, 0xBB", 877 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 878 "MSRIndex": "0x1a6,0x1a7", 879 "MSRValue": "0x063FC00122", 880 "Offcore": "1", 881 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 882 "SampleAfterValue": "100003", 883 "UMask": "0x1" 884 }, 885 { 886 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", 887 "Counter": "0,1,2,3", 888 "CounterHTOff": "0,1,2,3", 889 "EventCode": "0xB7, 0xBB", 890 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 891 "MSRIndex": "0x1a6,0x1a7", 892 "MSRValue": "0x063FC00001", 893 "Offcore": "1", 894 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 895 "SampleAfterValue": "100003", 896 "UMask": "0x1" 897 }, 898 { 899 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 900 "Counter": "0,1,2,3", 901 "CounterHTOff": "0,1,2,3", 902 "EventCode": "0xB7, 0xBB", 903 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 904 "MSRIndex": "0x1a6,0x1a7", 905 "MSRValue": "0x083FC00020", 906 "Offcore": "1", 907 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 908 "SampleAfterValue": "100003", 909 "UMask": "0x1" 910 }, 911 { 912 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", 913 "Counter": "0,1,2,3", 914 "CounterHTOff": "0,1,2,3", 915 "EventCode": "0xB7, 0xBB", 916 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 917 "MSRIndex": "0x1a6,0x1a7", 918 "MSRValue": "0x063B800002", 919 "Offcore": "1", 920 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 921 "SampleAfterValue": "100003", 922 "UMask": "0x1" 923 }, 924 { 925 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 926 "Counter": "0,1,2,3", 927 "CounterHTOff": "0,1,2,3", 928 "EventCode": "0xB7, 0xBB", 929 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 930 "MSRIndex": "0x1a6,0x1a7", 931 "MSRValue": "0x103FC00491", 932 "Offcore": "1", 933 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 934 "SampleAfterValue": "100003", 935 "UMask": "0x1" 936 }, 937 { 938 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 939 "Counter": "0,1,2,3", 940 "CounterHTOff": "0,1,2,3,4,5,6,7", 941 "EventCode": "0xC9", 942 "EventName": "RTM_RETIRED.ABORTED", 943 "PEBS": "1", 944 "PublicDescription": "Number of times RTM abort was triggered.", 945 "SampleAfterValue": "2000003", 946 "UMask": "0x4" 947 }, 948 { 949 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", 950 "Counter": "0,1,2,3", 951 "CounterHTOff": "0,1,2,3", 952 "EventCode": "0xB7, 0xBB", 953 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", 954 "MSRIndex": "0x1a6,0x1a7", 955 "MSRValue": "0x063FC00400", 956 "Offcore": "1", 957 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 958 "SampleAfterValue": "100003", 959 "UMask": "0x1" 960 }, 961 { 962 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 963 "Counter": "0,1,2,3", 964 "CounterHTOff": "0,1,2,3,4,5,6,7", 965 "EventCode": "0xC8", 966 "EventName": "HLE_RETIRED.ABORTED", 967 "PEBS": "1", 968 "PublicDescription": "Number of times HLE abort was triggered.", 969 "SampleAfterValue": "2000003", 970 "UMask": "0x4" 971 }, 972 { 973 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 974 "Counter": "0,1,2,3", 975 "CounterHTOff": "0,1,2,3", 976 "Data_LA": "1", 977 "EventCode": "0xcd", 978 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 979 "MSRIndex": "0x3F6", 980 "MSRValue": "0x10", 981 "PEBS": "2", 982 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 983 "SampleAfterValue": "20011", 984 "TakenAlone": "1", 985 "UMask": "0x1" 986 }, 987 { 988 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 989 "Counter": "0,1,2,3", 990 "CounterHTOff": "0,1,2,3,4,5,6,7", 991 "EventCode": "0x54", 992 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 993 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 994 "SampleAfterValue": "2000003", 995 "UMask": "0x20" 996 }, 997 { 998 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", 999 "Counter": "0,1,2,3", 1000 "CounterHTOff": "0,1,2,3", 1001 "EventCode": "0xB7, 0xBB", 1002 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 1003 "MSRIndex": "0x1a6,0x1a7", 1004 "MSRValue": "0x083FC00400", 1005 "Offcore": "1", 1006 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1007 "SampleAfterValue": "100003", 1008 "UMask": "0x1" 1009 }, 1010 { 1011 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", 1012 "Counter": "0,1,2,3", 1013 "CounterHTOff": "0,1,2,3", 1014 "EventCode": "0xB7, 0xBB", 1015 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1016 "MSRIndex": "0x1a6,0x1a7", 1017 "MSRValue": "0x063B800010", 1018 "Offcore": "1", 1019 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1020 "SampleAfterValue": "100003", 1021 "UMask": "0x1" 1022 }, 1023 { 1024 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 1025 "Counter": "0,1,2,3", 1026 "CounterHTOff": "0,1,2,3,4,5,6,7", 1027 "CounterMask": "1", 1028 "EventCode": "0x60", 1029 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 1030 "SampleAfterValue": "2000003", 1031 "UMask": "0x10" 1032 }, 1033 { 1034 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", 1035 "Counter": "0,1,2,3", 1036 "CounterHTOff": "0,1,2,3", 1037 "EventCode": "0xB7, 0xBB", 1038 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1039 "MSRIndex": "0x1a6,0x1a7", 1040 "MSRValue": "0x0604000002", 1041 "Offcore": "1", 1042 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1043 "SampleAfterValue": "100003", 1044 "UMask": "0x1" 1045 }, 1046 { 1047 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 1048 "Counter": "0,1,2,3", 1049 "CounterHTOff": "0,1,2,3", 1050 "Data_LA": "1", 1051 "EventCode": "0xcd", 1052 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 1053 "MSRIndex": "0x3F6", 1054 "MSRValue": "0x200", 1055 "PEBS": "2", 1056 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 1057 "SampleAfterValue": "101", 1058 "TakenAlone": "1", 1059 "UMask": "0x1" 1060 }, 1061 { 1062 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", 1063 "Counter": "0,1,2,3", 1064 "CounterHTOff": "0,1,2,3", 1065 "EventCode": "0xB7, 0xBB", 1066 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 1067 "MSRIndex": "0x1a6,0x1a7", 1068 "MSRValue": "0x103FC00400", 1069 "Offcore": "1", 1070 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1071 "SampleAfterValue": "100003", 1072 "UMask": "0x1" 1073 }, 1074 { 1075 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", 1076 "Counter": "0,1,2,3", 1077 "CounterHTOff": "0,1,2,3", 1078 "EventCode": "0xB7, 0xBB", 1079 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 1080 "MSRIndex": "0x1a6,0x1a7", 1081 "MSRValue": "0x3FBC000010", 1082 "Offcore": "1", 1083 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1084 "SampleAfterValue": "100003", 1085 "UMask": "0x1" 1086 }, 1087 { 1088 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.", 1089 "Counter": "0,1,2,3", 1090 "CounterHTOff": "0,1,2,3", 1091 "EventCode": "0xB7, 0xBB", 1092 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1093 "MSRIndex": "0x1a6,0x1a7", 1094 "MSRValue": "0x0604000004", 1095 "Offcore": "1", 1096 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1097 "SampleAfterValue": "100003", 1098 "UMask": "0x1" 1099 }, 1100 { 1101 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 1102 "Counter": "0,1,2,3", 1103 "CounterHTOff": "0,1,2,3,4,5,6,7", 1104 "EventCode": "0x54", 1105 "EventName": "TX_MEM.ABORT_CAPACITY", 1106 "SampleAfterValue": "2000003", 1107 "UMask": "0x2" 1108 }, 1109 { 1110 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", 1111 "Counter": "0,1,2,3", 1112 "CounterHTOff": "0,1,2,3", 1113 "EventCode": "0xB7, 0xBB", 1114 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1115 "MSRIndex": "0x1a6,0x1a7", 1116 "MSRValue": "0x063B800120", 1117 "Offcore": "1", 1118 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1119 "SampleAfterValue": "100003", 1120 "UMask": "0x1" 1121 }, 1122 { 1123 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 1124 "Counter": "0,1,2,3", 1125 "CounterHTOff": "0,1,2,3,4,5,6,7", 1126 "EventCode": "0xC8", 1127 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 1128 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 1129 "SampleAfterValue": "2000003", 1130 "UMask": "0x40" 1131 }, 1132 { 1133 "BriefDescription": "Number of times an RTM execution started.", 1134 "Counter": "0,1,2,3", 1135 "CounterHTOff": "0,1,2,3,4,5,6,7", 1136 "EventCode": "0xC9", 1137 "EventName": "RTM_RETIRED.START", 1138 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 1139 "SampleAfterValue": "2000003", 1140 "UMask": "0x1" 1141 }, 1142 { 1143 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 1144 "Counter": "0,1,2,3", 1145 "CounterHTOff": "0,1,2,3,4,5,6,7", 1146 "Errata": "SKL089", 1147 "EventCode": "0xC3", 1148 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 1149 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 1150 "SampleAfterValue": "100003", 1151 "UMask": "0x2" 1152 }, 1153 { 1154 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 1155 "Counter": "0,1,2,3", 1156 "CounterHTOff": "0,1,2,3,4,5,6,7", 1157 "EventCode": "0x54", 1158 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 1159 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 1160 "SampleAfterValue": "2000003", 1161 "UMask": "0x10" 1162 }, 1163 { 1164 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 1165 "Counter": "0,1,2,3", 1166 "CounterHTOff": "0,1,2,3", 1167 "EventCode": "0xB7, 0xBB", 1168 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1169 "MSRIndex": "0x1a6,0x1a7", 1170 "MSRValue": "0x063FC00491", 1171 "Offcore": "1", 1172 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1173 "SampleAfterValue": "100003", 1174 "UMask": "0x1" 1175 }, 1176 { 1177 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 1178 "Counter": "0,1,2,3", 1179 "CounterHTOff": "0,1,2,3", 1180 "EventCode": "0xB7, 0xBB", 1181 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 1182 "MSRIndex": "0x1a6,0x1a7", 1183 "MSRValue": "0x3FBC000491", 1184 "Offcore": "1", 1185 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1186 "SampleAfterValue": "100003", 1187 "UMask": "0x1" 1188 }, 1189 { 1190 "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", 1191 "Counter": "0,1,2,3", 1192 "CounterHTOff": "0,1,2,3", 1193 "EventCode": "0xB7, 0xBB", 1194 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 1195 "MSRIndex": "0x1a6,0x1a7", 1196 "MSRValue": "0x083FC00001", 1197 "Offcore": "1", 1198 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1199 "SampleAfterValue": "100003", 1200 "UMask": "0x1" 1201 }, 1202 { 1203 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", 1204 "Counter": "0,1,2,3", 1205 "CounterHTOff": "0,1,2,3", 1206 "EventCode": "0xB7, 0xBB", 1207 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 1208 "MSRIndex": "0x1a6,0x1a7", 1209 "MSRValue": "0x3FBC000080", 1210 "Offcore": "1", 1211 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1212 "SampleAfterValue": "100003", 1213 "UMask": "0x1" 1214 }, 1215 { 1216 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", 1217 "Counter": "0,1,2,3", 1218 "CounterHTOff": "0,1,2,3", 1219 "EventCode": "0xB7, 0xBB", 1220 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1221 "MSRIndex": "0x1a6,0x1a7", 1222 "MSRValue": "0x0604000100", 1223 "Offcore": "1", 1224 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1225 "SampleAfterValue": "100003", 1226 "UMask": "0x1" 1227 }, 1228 { 1229 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", 1230 "Counter": "0,1,2,3", 1231 "CounterHTOff": "0,1,2,3", 1232 "EventCode": "0xB7, 0xBB", 1233 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1234 "MSRIndex": "0x1a6,0x1a7", 1235 "MSRValue": "0x0604000080", 1236 "Offcore": "1", 1237 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1238 "SampleAfterValue": "100003", 1239 "UMask": "0x1" 1240 }, 1241 { 1242 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 1243 "Counter": "0,1,2,3", 1244 "CounterHTOff": "0,1,2,3,4,5,6,7", 1245 "EventCode": "0xC9", 1246 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 1247 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 1248 "SampleAfterValue": "2000003", 1249 "UMask": "0x80" 1250 }, 1251 { 1252 "BriefDescription": "Number of times an HLE execution started.", 1253 "Counter": "0,1,2,3", 1254 "CounterHTOff": "0,1,2,3,4,5,6,7", 1255 "EventCode": "0xC8", 1256 "EventName": "HLE_RETIRED.START", 1257 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 1258 "SampleAfterValue": "2000003", 1259 "UMask": "0x1" 1260 }, 1261 { 1262 "BriefDescription": "Counts all demand code reads that miss in the L3.", 1263 "Counter": "0,1,2,3", 1264 "CounterHTOff": "0,1,2,3", 1265 "EventCode": "0xB7, 0xBB", 1266 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 1267 "MSRIndex": "0x1a6,0x1a7", 1268 "MSRValue": "0x3FBC000004", 1269 "Offcore": "1", 1270 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1271 "SampleAfterValue": "100003", 1272 "UMask": "0x1" 1273 }, 1274 { 1275 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 1276 "Counter": "0,1,2,3", 1277 "CounterHTOff": "0,1,2,3", 1278 "Data_LA": "1", 1279 "EventCode": "0xcd", 1280 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 1281 "MSRIndex": "0x3F6", 1282 "MSRValue": "0x80", 1283 "PEBS": "2", 1284 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 1285 "SampleAfterValue": "1009", 1286 "TakenAlone": "1", 1287 "UMask": "0x1" 1288 }, 1289 { 1290 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 1291 "Counter": "0,1,2,3", 1292 "CounterHTOff": "0,1,2,3", 1293 "EventCode": "0xB7, 0xBB", 1294 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 1295 "MSRIndex": "0x1a6,0x1a7", 1296 "MSRValue": "0x083FC00491", 1297 "Offcore": "1", 1298 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1299 "SampleAfterValue": "100003", 1300 "UMask": "0x1" 1301 }, 1302 { 1303 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 1304 "Counter": "0,1,2,3", 1305 "CounterHTOff": "0,1,2,3", 1306 "EventCode": "0xB7, 0xBB", 1307 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 1308 "MSRIndex": "0x1a6,0x1a7", 1309 "MSRValue": "0x103FC00120", 1310 "Offcore": "1", 1311 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1312 "SampleAfterValue": "100003", 1313 "UMask": "0x1" 1314 }, 1315 { 1316 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", 1317 "Counter": "0,1,2,3", 1318 "CounterHTOff": "0,1,2,3", 1319 "EventCode": "0xB7, 0xBB", 1320 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1321 "MSRIndex": "0x1a6,0x1a7", 1322 "MSRValue": "0x063FC00100", 1323 "Offcore": "1", 1324 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1325 "SampleAfterValue": "100003", 1326 "UMask": "0x1" 1327 }, 1328 { 1329 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 1330 "Counter": "0,1,2,3", 1331 "CounterHTOff": "0,1,2,3,4,5,6,7", 1332 "CounterMask": "6", 1333 "EventCode": "0xA3", 1334 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 1335 "SampleAfterValue": "2000003", 1336 "UMask": "0x6" 1337 }, 1338 { 1339 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 1340 "Counter": "0,1,2,3", 1341 "CounterHTOff": "0,1,2,3,4,5,6,7", 1342 "EventCode": "0xC8", 1343 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 1344 "SampleAfterValue": "2000003", 1345 "UMask": "0x80" 1346 }, 1347 { 1348 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", 1349 "Counter": "0,1,2,3", 1350 "CounterHTOff": "0,1,2,3", 1351 "EventCode": "0xB7, 0xBB", 1352 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1353 "MSRIndex": "0x1a6,0x1a7", 1354 "MSRValue": "0x0604000122", 1355 "Offcore": "1", 1356 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1357 "SampleAfterValue": "100003", 1358 "UMask": "0x1" 1359 }, 1360 { 1361 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 1362 "Counter": "0,1,2,3", 1363 "CounterHTOff": "0,1,2,3", 1364 "Data_LA": "1", 1365 "EventCode": "0xcd", 1366 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 1367 "MSRIndex": "0x3F6", 1368 "MSRValue": "0x4", 1369 "PEBS": "2", 1370 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 1371 "SampleAfterValue": "100003", 1372 "TakenAlone": "1", 1373 "UMask": "0x1" 1374 }, 1375 { 1376 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 1377 "Counter": "0,1,2,3", 1378 "CounterHTOff": "0,1,2,3", 1379 "Data_LA": "1", 1380 "EventCode": "0xcd", 1381 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 1382 "MSRIndex": "0x3F6", 1383 "MSRValue": "0x8", 1384 "PEBS": "2", 1385 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 1386 "SampleAfterValue": "50021", 1387 "TakenAlone": "1", 1388 "UMask": "0x1" 1389 }, 1390 { 1391 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", 1392 "Counter": "0,1,2,3", 1393 "CounterHTOff": "0,1,2,3", 1394 "EventCode": "0xB7, 0xBB", 1395 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1396 "MSRIndex": "0x1a6,0x1a7", 1397 "MSRValue": "0x0604000400", 1398 "Offcore": "1", 1399 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1400 "SampleAfterValue": "100003", 1401 "UMask": "0x1" 1402 } 1403]