1630171d4SAndi Kleen[ 2630171d4SAndi Kleen { 3b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", 4630171d4SAndi Kleen "Counter": "0,1,2,3", 5b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 6b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 7b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 9b5ff7f27SJin Yao "MSRValue": "0x063B800122", 10b5ff7f27SJin Yao "Offcore": "1", 11b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 12b5ff7f27SJin Yao "SampleAfterValue": "100003", 13b5ff7f27SJin Yao "UMask": "0x1" 14630171d4SAndi Kleen }, 15630171d4SAndi Kleen { 16b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", 17630171d4SAndi Kleen "Counter": "0,1,2,3", 18b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 19b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 20b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", 21b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 22b5ff7f27SJin Yao "MSRValue": "0x3FBC000122", 23b5ff7f27SJin Yao "Offcore": "1", 24b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 25b5ff7f27SJin Yao "SampleAfterValue": "100003", 26b5ff7f27SJin Yao "UMask": "0x1" 27630171d4SAndi Kleen }, 28630171d4SAndi Kleen { 2919f2d40cSAndi Kleen "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 30630171d4SAndi Kleen "Counter": "0,1,2,3", 31b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 3219f2d40cSAndi Kleen "CounterMask": "6", 33630171d4SAndi Kleen "EventCode": "0x60", 34b5ff7f27SJin Yao "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 35630171d4SAndi Kleen "SampleAfterValue": "2000003", 36b5ff7f27SJin Yao "UMask": "0x10" 37630171d4SAndi Kleen }, 38630171d4SAndi Kleen { 39b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", 40630171d4SAndi Kleen "Counter": "0,1,2,3", 41b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 42b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 43b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 44b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 45b5ff7f27SJin Yao "MSRValue": "0x063B800020", 46b5ff7f27SJin Yao "Offcore": "1", 47b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 48630171d4SAndi Kleen "SampleAfterValue": "100003", 49b5ff7f27SJin Yao "UMask": "0x1" 50630171d4SAndi Kleen }, 51630171d4SAndi Kleen { 52b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", 53630171d4SAndi Kleen "Counter": "0,1,2,3", 54b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 55b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 56b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", 57b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 58b5ff7f27SJin Yao "MSRValue": "0x3FBC000100", 59b5ff7f27SJin Yao "Offcore": "1", 60b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 61630171d4SAndi Kleen "SampleAfterValue": "100003", 62b5ff7f27SJin Yao "UMask": "0x1" 63630171d4SAndi Kleen }, 64630171d4SAndi Kleen { 65b5ff7f27SJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", 66630171d4SAndi Kleen "Counter": "0,1,2,3", 67b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 68b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 69b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", 70b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 71b5ff7f27SJin Yao "MSRValue": "0x103FC00002", 72b5ff7f27SJin Yao "Offcore": "1", 73b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 74b5ff7f27SJin Yao "SampleAfterValue": "100003", 75b5ff7f27SJin Yao "UMask": "0x1" 76630171d4SAndi Kleen }, 77630171d4SAndi Kleen { 78630171d4SAndi Kleen "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 79630171d4SAndi Kleen "Counter": "0,1,2,3", 80b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 81b5ff7f27SJin Yao "EventCode": "0xC8", 82630171d4SAndi Kleen "EventName": "HLE_RETIRED.ABORTED_TIMER", 83630171d4SAndi Kleen "SampleAfterValue": "2000003", 84b5ff7f27SJin Yao "UMask": "0x10" 85630171d4SAndi Kleen }, 86630171d4SAndi Kleen { 87b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", 88630171d4SAndi Kleen "Counter": "0,1,2,3", 89b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 90b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 91b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 92b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 93b5ff7f27SJin Yao "MSRValue": "0x063B800490", 94b5ff7f27SJin Yao "Offcore": "1", 95b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 96b5ff7f27SJin Yao "SampleAfterValue": "100003", 97b5ff7f27SJin Yao "UMask": "0x1" 98630171d4SAndi Kleen }, 99630171d4SAndi Kleen { 100630171d4SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 101630171d4SAndi Kleen "Counter": "0,1,2,3", 102b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 103b5ff7f27SJin Yao "EventCode": "0xC9", 104630171d4SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MEM", 105630171d4SAndi Kleen "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 106630171d4SAndi Kleen "SampleAfterValue": "2000003", 107b5ff7f27SJin Yao "UMask": "0x8" 108630171d4SAndi Kleen }, 109630171d4SAndi Kleen { 110b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", 111630171d4SAndi Kleen "Counter": "0,1,2,3", 112b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 113b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 114b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 115b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 116b5ff7f27SJin Yao "MSRValue": "0x063B800004", 117b5ff7f27SJin Yao "Offcore": "1", 118b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 119b5ff7f27SJin Yao "SampleAfterValue": "100003", 120b5ff7f27SJin Yao "UMask": "0x1" 121630171d4SAndi Kleen }, 122630171d4SAndi Kleen { 123630171d4SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 124630171d4SAndi Kleen "Counter": "0,1,2,3", 125b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 126b5ff7f27SJin Yao "EventCode": "0xC9", 127630171d4SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 128630171d4SAndi Kleen "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 129630171d4SAndi Kleen "SampleAfterValue": "2000003", 130b5ff7f27SJin Yao "UMask": "0x40" 131630171d4SAndi Kleen }, 132630171d4SAndi Kleen { 133b5ff7f27SJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", 134b5ff7f27SJin Yao "Counter": "0,1,2,3", 135b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 136b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 137b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 138b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 139b5ff7f27SJin Yao "MSRValue": "0x3FBC000002", 140b5ff7f27SJin Yao "Offcore": "1", 141b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 142b5ff7f27SJin Yao "SampleAfterValue": "100003", 143b5ff7f27SJin Yao "UMask": "0x1" 144b5ff7f27SJin Yao }, 145b5ff7f27SJin Yao { 146b5ff7f27SJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 147b5ff7f27SJin Yao "Counter": "0,1,2,3", 148b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 149b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 150b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 151b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 152b5ff7f27SJin Yao "MSRValue": "0x063FC00120", 153b5ff7f27SJin Yao "Offcore": "1", 154b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 155b5ff7f27SJin Yao "SampleAfterValue": "100003", 156b5ff7f27SJin Yao "UMask": "0x1" 157b5ff7f27SJin Yao }, 158b5ff7f27SJin Yao { 159b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss in the L3.", 160b5ff7f27SJin Yao "Counter": "0,1,2,3", 161b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 162b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 163b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 164b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 165b5ff7f27SJin Yao "MSRValue": "0x3FBC000490", 166b5ff7f27SJin Yao "Offcore": "1", 167b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 168b5ff7f27SJin Yao "SampleAfterValue": "100003", 169b5ff7f27SJin Yao "UMask": "0x1" 170b5ff7f27SJin Yao }, 171b5ff7f27SJin Yao { 172b5ff7f27SJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", 173b5ff7f27SJin Yao "Counter": "0,1,2,3", 174b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 175b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 176b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 177b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 178b5ff7f27SJin Yao "MSRValue": "0x0604000120", 179b5ff7f27SJin Yao "Offcore": "1", 180b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 181b5ff7f27SJin Yao "SampleAfterValue": "100003", 182b5ff7f27SJin Yao "UMask": "0x1" 183b5ff7f27SJin Yao }, 184b5ff7f27SJin Yao { 185b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", 186b5ff7f27SJin Yao "Counter": "0,1,2,3", 187b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 188b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 189b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 190b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 191b5ff7f27SJin Yao "MSRValue": "0x0604000490", 192b5ff7f27SJin Yao "Offcore": "1", 193b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 194b5ff7f27SJin Yao "SampleAfterValue": "100003", 195b5ff7f27SJin Yao "UMask": "0x1" 196b5ff7f27SJin Yao }, 197b5ff7f27SJin Yao { 198b5ff7f27SJin Yao "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 199b5ff7f27SJin Yao "Counter": "0,1,2,3", 200b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 201b5ff7f27SJin Yao "CounterMask": "2", 202b5ff7f27SJin Yao "EventCode": "0xA3", 203b5ff7f27SJin Yao "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 204b5ff7f27SJin Yao "SampleAfterValue": "2000003", 205b5ff7f27SJin Yao "UMask": "0x2" 206b5ff7f27SJin Yao }, 207b5ff7f27SJin Yao { 208b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", 209b5ff7f27SJin Yao "Counter": "0,1,2,3", 210b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 211b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 212b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 213b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 214b5ff7f27SJin Yao "MSRValue": "0x0604000491", 215b5ff7f27SJin Yao "Offcore": "1", 216b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 217b5ff7f27SJin Yao "SampleAfterValue": "100003", 218b5ff7f27SJin Yao "UMask": "0x1" 219b5ff7f27SJin Yao }, 220b5ff7f27SJin Yao { 221b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", 222b5ff7f27SJin Yao "Counter": "0,1,2,3", 223b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 224b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 225b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 226b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 227b5ff7f27SJin Yao "MSRValue": "0x083FC00004", 228b5ff7f27SJin Yao "Offcore": "1", 229b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 230b5ff7f27SJin Yao "SampleAfterValue": "100003", 231b5ff7f27SJin Yao "UMask": "0x1" 232b5ff7f27SJin Yao }, 233b5ff7f27SJin Yao { 234b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.", 235b5ff7f27SJin Yao "Counter": "0,1,2,3", 236b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 237b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 238b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 239b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 240b5ff7f27SJin Yao "MSRValue": "0x063FC00004", 241b5ff7f27SJin Yao "Offcore": "1", 242b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 243b5ff7f27SJin Yao "SampleAfterValue": "100003", 244b5ff7f27SJin Yao "UMask": "0x1" 245b5ff7f27SJin Yao }, 246b5ff7f27SJin Yao { 247b5ff7f27SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 248b5ff7f27SJin Yao "Counter": "0,1,2,3", 249b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 250b5ff7f27SJin Yao "Data_LA": "1", 251b5ff7f27SJin Yao "EventCode": "0xcd", 252b5ff7f27SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 253b5ff7f27SJin Yao "MSRIndex": "0x3F6", 254b5ff7f27SJin Yao "MSRValue": "0x20", 255b5ff7f27SJin Yao "PEBS": "2", 256b5ff7f27SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 257b5ff7f27SJin Yao "SampleAfterValue": "100007", 258b5ff7f27SJin Yao "TakenAlone": "1", 259b5ff7f27SJin Yao "UMask": "0x1" 260b5ff7f27SJin Yao }, 261b5ff7f27SJin Yao { 262b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", 263b5ff7f27SJin Yao "Counter": "0,1,2,3", 264b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 265b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 266b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", 267b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 268b5ff7f27SJin Yao "MSRValue": "0x103FC00020", 269b5ff7f27SJin Yao "Offcore": "1", 270b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 271b5ff7f27SJin Yao "SampleAfterValue": "100003", 272b5ff7f27SJin Yao "UMask": "0x1" 273b5ff7f27SJin Yao }, 274b5ff7f27SJin Yao { 275b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 276b5ff7f27SJin Yao "Counter": "0,1,2,3", 277b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 278b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 279b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 280b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 281b5ff7f27SJin Yao "MSRValue": "0x103FC00490", 282b5ff7f27SJin Yao "Offcore": "1", 283b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 284b5ff7f27SJin Yao "SampleAfterValue": "100003", 285b5ff7f27SJin Yao "UMask": "0x1" 286b5ff7f27SJin Yao }, 287b5ff7f27SJin Yao { 288b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", 289b5ff7f27SJin Yao "Counter": "0,1,2,3", 290b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 291b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 292b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", 293b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 294b5ff7f27SJin Yao "MSRValue": "0x3FBC000020", 295b5ff7f27SJin Yao "Offcore": "1", 296b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 297b5ff7f27SJin Yao "SampleAfterValue": "100003", 298b5ff7f27SJin Yao "UMask": "0x1" 299b5ff7f27SJin Yao }, 300b5ff7f27SJin Yao { 301b5ff7f27SJin Yao "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 302b5ff7f27SJin Yao "Counter": "0,1,2,3", 303b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 304b5ff7f27SJin Yao "EventCode": "0x54", 305b5ff7f27SJin Yao "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 306b5ff7f27SJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 307b5ff7f27SJin Yao "SampleAfterValue": "2000003", 308b5ff7f27SJin Yao "UMask": "0x4" 309b5ff7f27SJin Yao }, 310b5ff7f27SJin Yao { 311b5ff7f27SJin Yao "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 312b5ff7f27SJin Yao "Counter": "0,1,2,3", 313b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 314b5ff7f27SJin Yao "EventCode": "0x54", 315b5ff7f27SJin Yao "EventName": "TX_MEM.ABORT_CONFLICT", 316b5ff7f27SJin Yao "PublicDescription": "Number of times a TSX line had a cache conflict.", 317b5ff7f27SJin Yao "SampleAfterValue": "2000003", 318b5ff7f27SJin Yao "UMask": "0x1" 319b5ff7f27SJin Yao }, 320b5ff7f27SJin Yao { 321b5ff7f27SJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", 322b5ff7f27SJin Yao "Counter": "0,1,2,3", 323b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 324b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 325b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 326b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 327b5ff7f27SJin Yao "MSRValue": "0x3FBC000400", 328b5ff7f27SJin Yao "Offcore": "1", 329b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 330b5ff7f27SJin Yao "SampleAfterValue": "100003", 331b5ff7f27SJin Yao "UMask": "0x1" 332b5ff7f27SJin Yao }, 333b5ff7f27SJin Yao { 334b5ff7f27SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 335b5ff7f27SJin Yao "Counter": "0,1,2,3", 336b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 337b5ff7f27SJin Yao "Data_LA": "1", 338b5ff7f27SJin Yao "EventCode": "0xcd", 339b5ff7f27SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 340b5ff7f27SJin Yao "MSRIndex": "0x3F6", 341b5ff7f27SJin Yao "MSRValue": "0x40", 342b5ff7f27SJin Yao "PEBS": "2", 343b5ff7f27SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 344b5ff7f27SJin Yao "SampleAfterValue": "2003", 345b5ff7f27SJin Yao "TakenAlone": "1", 346b5ff7f27SJin Yao "UMask": "0x1" 347b5ff7f27SJin Yao }, 348b5ff7f27SJin Yao { 349b5ff7f27SJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", 350b5ff7f27SJin Yao "Counter": "0,1,2,3", 351b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 352b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 353b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 354b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 355b5ff7f27SJin Yao "MSRValue": "0x083FC00002", 356b5ff7f27SJin Yao "Offcore": "1", 357b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 358b5ff7f27SJin Yao "SampleAfterValue": "100003", 359b5ff7f27SJin Yao "UMask": "0x1" 360b5ff7f27SJin Yao }, 361b5ff7f27SJin Yao { 362b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 363b5ff7f27SJin Yao "Counter": "0,1,2,3", 364b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 365b5ff7f27SJin Yao "EventCode": "0xC8", 366b5ff7f27SJin Yao "EventName": "HLE_RETIRED.ABORTED_MEM", 367b5ff7f27SJin Yao "SampleAfterValue": "2000003", 368b5ff7f27SJin Yao "UMask": "0x8" 369b5ff7f27SJin Yao }, 370b5ff7f27SJin Yao { 371b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 372b5ff7f27SJin Yao "Counter": "0,1,2,3", 373b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 374b5ff7f27SJin Yao "EventCode": "0x54", 375b5ff7f27SJin Yao "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 376b5ff7f27SJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 377b5ff7f27SJin Yao "SampleAfterValue": "2000003", 378b5ff7f27SJin Yao "UMask": "0x8" 379b5ff7f27SJin Yao }, 380b5ff7f27SJin Yao { 381b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", 382b5ff7f27SJin Yao "Counter": "0,1,2,3", 383b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 384b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 385b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 386b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 387b5ff7f27SJin Yao "MSRValue": "0x103FC00080", 388b5ff7f27SJin Yao "Offcore": "1", 389b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 390b5ff7f27SJin Yao "SampleAfterValue": "100003", 391b5ff7f27SJin Yao "UMask": "0x1" 392b5ff7f27SJin Yao }, 393b5ff7f27SJin Yao { 394b5ff7f27SJin Yao "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 395b5ff7f27SJin Yao "Counter": "0,1,2,3", 396b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 397b5ff7f27SJin Yao "EventCode": "0x5d", 398b5ff7f27SJin Yao "EventName": "TX_EXEC.MISC5", 399b5ff7f27SJin Yao "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 400b5ff7f27SJin Yao "SampleAfterValue": "2000003", 401b5ff7f27SJin Yao "UMask": "0x10" 402b5ff7f27SJin Yao }, 403b5ff7f27SJin Yao { 404b5ff7f27SJin Yao "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 405b5ff7f27SJin Yao "Counter": "0,1,2,3", 406b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 407b5ff7f27SJin Yao "EventCode": "0x5d", 408b5ff7f27SJin Yao "EventName": "TX_EXEC.MISC4", 409b5ff7f27SJin Yao "PublicDescription": "RTM region detected inside HLE.", 410b5ff7f27SJin Yao "SampleAfterValue": "2000003", 411b5ff7f27SJin Yao "UMask": "0x8" 412b5ff7f27SJin Yao }, 413b5ff7f27SJin Yao { 414b5ff7f27SJin Yao "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 415b5ff7f27SJin Yao "Counter": "0,1,2,3", 416b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 417b5ff7f27SJin Yao "EventCode": "0x5d", 418b5ff7f27SJin Yao "EventName": "TX_EXEC.MISC3", 419b5ff7f27SJin Yao "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 420b5ff7f27SJin Yao "SampleAfterValue": "2000003", 421b5ff7f27SJin Yao "UMask": "0x4" 422b5ff7f27SJin Yao }, 423b5ff7f27SJin Yao { 424b5ff7f27SJin Yao "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 425b5ff7f27SJin Yao "Counter": "0,1,2,3", 426b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 427b5ff7f27SJin Yao "EventCode": "0x5d", 428b5ff7f27SJin Yao "EventName": "TX_EXEC.MISC2", 429b5ff7f27SJin Yao "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 430b5ff7f27SJin Yao "SampleAfterValue": "2000003", 431b5ff7f27SJin Yao "UMask": "0x2" 432b5ff7f27SJin Yao }, 433b5ff7f27SJin Yao { 434b5ff7f27SJin Yao "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 435b5ff7f27SJin Yao "Counter": "0,1,2,3", 436b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 437b5ff7f27SJin Yao "EventCode": "0x5d", 438b5ff7f27SJin Yao "EventName": "TX_EXEC.MISC1", 439b5ff7f27SJin Yao "SampleAfterValue": "2000003", 440b5ff7f27SJin Yao "UMask": "0x1" 441b5ff7f27SJin Yao }, 442b5ff7f27SJin Yao { 443b5ff7f27SJin Yao "BriefDescription": "Number of times an RTM execution successfully committed", 444b5ff7f27SJin Yao "Counter": "0,1,2,3", 445b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 446630171d4SAndi Kleen "EventCode": "0xC9", 447b5ff7f27SJin Yao "EventName": "RTM_RETIRED.COMMIT", 448b5ff7f27SJin Yao "PublicDescription": "Number of times RTM commit succeeded.", 449b5ff7f27SJin Yao "SampleAfterValue": "2000003", 450b5ff7f27SJin Yao "UMask": "0x2" 451b5ff7f27SJin Yao }, 452b5ff7f27SJin Yao { 453b5ff7f27SJin Yao "BriefDescription": "Counts prefetch RFOs that miss in the L3.", 454b5ff7f27SJin Yao "Counter": "0,1,2,3", 455b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 456b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 457b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 458b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 459b5ff7f27SJin Yao "MSRValue": "0x3FBC000120", 460b5ff7f27SJin Yao "Offcore": "1", 461b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 462b5ff7f27SJin Yao "SampleAfterValue": "100003", 463b5ff7f27SJin Yao "UMask": "0x1" 464b5ff7f27SJin Yao }, 465b5ff7f27SJin Yao { 466b5ff7f27SJin Yao "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 467b5ff7f27SJin Yao "Counter": "0,1,2,3", 468b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 469b5ff7f27SJin Yao "EventCode": "0x60", 470b5ff7f27SJin Yao "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 471b5ff7f27SJin Yao "SampleAfterValue": "2000003", 472b5ff7f27SJin Yao "UMask": "0x10" 473b5ff7f27SJin Yao }, 474b5ff7f27SJin Yao { 475b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", 476b5ff7f27SJin Yao "Counter": "0,1,2,3", 477b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 478b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 479b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 480b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 481b5ff7f27SJin Yao "MSRValue": "0x063B800491", 482b5ff7f27SJin Yao "Offcore": "1", 483b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 484b5ff7f27SJin Yao "SampleAfterValue": "100003", 485b5ff7f27SJin Yao "UMask": "0x1" 486b5ff7f27SJin Yao }, 487b5ff7f27SJin Yao { 488b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", 489b5ff7f27SJin Yao "Counter": "0,1,2,3", 490b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 491b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 492b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 493b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 494b5ff7f27SJin Yao "MSRValue": "0x063B800080", 495b5ff7f27SJin Yao "Offcore": "1", 496b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 497b5ff7f27SJin Yao "SampleAfterValue": "100003", 498b5ff7f27SJin Yao "UMask": "0x1" 499b5ff7f27SJin Yao }, 500b5ff7f27SJin Yao { 501b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 502b5ff7f27SJin Yao "Counter": "0,1,2,3", 503b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 504b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 505b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 506b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 507b5ff7f27SJin Yao "MSRValue": "0x083FC00490", 508b5ff7f27SJin Yao "Offcore": "1", 509b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 510b5ff7f27SJin Yao "SampleAfterValue": "100003", 511b5ff7f27SJin Yao "UMask": "0x1" 512b5ff7f27SJin Yao }, 513b5ff7f27SJin Yao { 514b5ff7f27SJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", 515b5ff7f27SJin Yao "Counter": "0,1,2,3", 516b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 517b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 518b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 519b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 520b5ff7f27SJin Yao "MSRValue": "0x0604000010", 521b5ff7f27SJin Yao "Offcore": "1", 522b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 523b5ff7f27SJin Yao "SampleAfterValue": "100003", 524b5ff7f27SJin Yao "UMask": "0x1" 525b5ff7f27SJin Yao }, 526b5ff7f27SJin Yao { 527b5ff7f27SJin Yao "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 528b5ff7f27SJin Yao "Counter": "0,1,2,3", 529b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 530b5ff7f27SJin Yao "EventCode": "0xC9", 531b5ff7f27SJin Yao "EventName": "RTM_RETIRED.ABORTED_TIMER", 532b5ff7f27SJin Yao "SampleAfterValue": "2000003", 533b5ff7f27SJin Yao "UMask": "0x10" 534b5ff7f27SJin Yao }, 535b5ff7f27SJin Yao { 536b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", 537b5ff7f27SJin Yao "Counter": "0,1,2,3", 538b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 539b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 540b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 541b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 542b5ff7f27SJin Yao "MSRValue": "0x063FC00020", 543b5ff7f27SJin Yao "Offcore": "1", 544b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 545b5ff7f27SJin Yao "SampleAfterValue": "100003", 546b5ff7f27SJin Yao "UMask": "0x1" 547b5ff7f27SJin Yao }, 548b5ff7f27SJin Yao { 549b5ff7f27SJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", 550b5ff7f27SJin Yao "Counter": "0,1,2,3", 551b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 552b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 553b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 554b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 555b5ff7f27SJin Yao "MSRValue": "0x063FC00002", 556b5ff7f27SJin Yao "Offcore": "1", 557b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 558b5ff7f27SJin Yao "SampleAfterValue": "100003", 559b5ff7f27SJin Yao "UMask": "0x1" 560b5ff7f27SJin Yao }, 561b5ff7f27SJin Yao { 562b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 563b5ff7f27SJin Yao "Counter": "0,1,2,3", 564b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 565b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 566b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 567b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 568b5ff7f27SJin Yao "MSRValue": "0x063FC00490", 569b5ff7f27SJin Yao "Offcore": "1", 570b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 571b5ff7f27SJin Yao "SampleAfterValue": "100003", 572b5ff7f27SJin Yao "UMask": "0x1" 573b5ff7f27SJin Yao }, 574b5ff7f27SJin Yao { 575b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", 576b5ff7f27SJin Yao "Counter": "0,1,2,3", 577b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 578b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 579b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 580b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 581b5ff7f27SJin Yao "MSRValue": "0x063B800100", 582b5ff7f27SJin Yao "Offcore": "1", 583b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 584b5ff7f27SJin Yao "SampleAfterValue": "100003", 585b5ff7f27SJin Yao "UMask": "0x1" 586b5ff7f27SJin Yao }, 587b5ff7f27SJin Yao { 588b5ff7f27SJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", 589b5ff7f27SJin Yao "Counter": "0,1,2,3", 590b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 591b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 592b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 593b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 594b5ff7f27SJin Yao "MSRValue": "0x103FC00010", 595b5ff7f27SJin Yao "Offcore": "1", 596b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 597b5ff7f27SJin Yao "SampleAfterValue": "100003", 598b5ff7f27SJin Yao "UMask": "0x1" 599b5ff7f27SJin Yao }, 600b5ff7f27SJin Yao { 601b5ff7f27SJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", 602b5ff7f27SJin Yao "Counter": "0,1,2,3", 603b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 604b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 605b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 606b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 607b5ff7f27SJin Yao "MSRValue": "0x063FC00010", 608b5ff7f27SJin Yao "Offcore": "1", 609b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 610b5ff7f27SJin Yao "SampleAfterValue": "100003", 611b5ff7f27SJin Yao "UMask": "0x1" 612b5ff7f27SJin Yao }, 613b5ff7f27SJin Yao { 614b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 615b5ff7f27SJin Yao "Counter": "0,1,2,3", 616b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 617b5ff7f27SJin Yao "EventCode": "0xC8", 618b5ff7f27SJin Yao "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 619b5ff7f27SJin Yao "SampleAfterValue": "2000003", 620b5ff7f27SJin Yao "UMask": "0x20" 621b5ff7f27SJin Yao }, 622b5ff7f27SJin Yao { 623b5ff7f27SJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", 624b5ff7f27SJin Yao "Counter": "0,1,2,3", 625b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 626b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 627b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 628b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 629b5ff7f27SJin Yao "MSRValue": "0x063B800400", 630b5ff7f27SJin Yao "Offcore": "1", 631b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 632b5ff7f27SJin Yao "SampleAfterValue": "100003", 633b5ff7f27SJin Yao "UMask": "0x1" 634b5ff7f27SJin Yao }, 635b5ff7f27SJin Yao { 636b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 637b5ff7f27SJin Yao "Counter": "0,1,2,3", 638b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 639b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 640b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 641b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 642b5ff7f27SJin Yao "MSRValue": "0x083FC00122", 643b5ff7f27SJin Yao "Offcore": "1", 644b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 645b5ff7f27SJin Yao "SampleAfterValue": "100003", 646b5ff7f27SJin Yao "UMask": "0x1" 647b5ff7f27SJin Yao }, 648b5ff7f27SJin Yao { 649b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 650b5ff7f27SJin Yao "Counter": "0,1,2,3", 651b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 652b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 653b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", 654b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 655b5ff7f27SJin Yao "MSRValue": "0x103FC00122", 656b5ff7f27SJin Yao "Offcore": "1", 657b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 658b5ff7f27SJin Yao "SampleAfterValue": "100003", 659b5ff7f27SJin Yao "UMask": "0x1" 660b5ff7f27SJin Yao }, 661b5ff7f27SJin Yao { 662b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", 663b5ff7f27SJin Yao "Counter": "0,1,2,3", 664b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 665b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 666b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 667b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 668b5ff7f27SJin Yao "MSRValue": "0x063B800001", 669b5ff7f27SJin Yao "Offcore": "1", 670b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 671b5ff7f27SJin Yao "SampleAfterValue": "100003", 672b5ff7f27SJin Yao "UMask": "0x1" 673b5ff7f27SJin Yao }, 674b5ff7f27SJin Yao { 675b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", 676b5ff7f27SJin Yao "Counter": "0,1,2,3", 677b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 678b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 679b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 680b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 681b5ff7f27SJin Yao "MSRValue": "0x0604000001", 682b5ff7f27SJin Yao "Offcore": "1", 683b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 684b5ff7f27SJin Yao "SampleAfterValue": "100003", 685b5ff7f27SJin Yao "UMask": "0x1" 686b5ff7f27SJin Yao }, 687b5ff7f27SJin Yao { 688b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE execution successfully committed", 689b5ff7f27SJin Yao "Counter": "0,1,2,3", 690b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 691b5ff7f27SJin Yao "EventCode": "0xC8", 692b5ff7f27SJin Yao "EventName": "HLE_RETIRED.COMMIT", 693b5ff7f27SJin Yao "PublicDescription": "Number of times HLE commit succeeded.", 694b5ff7f27SJin Yao "SampleAfterValue": "2000003", 695b5ff7f27SJin Yao "UMask": "0x2" 696b5ff7f27SJin Yao }, 697b5ff7f27SJin Yao { 698b5ff7f27SJin Yao "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 699b5ff7f27SJin Yao "Counter": "0,1,2,3", 700b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 701b5ff7f27SJin Yao "EventCode": "0x54", 702b5ff7f27SJin Yao "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 703b5ff7f27SJin Yao "PublicDescription": "Number of times we could not allocate Lock Buffer.", 704b5ff7f27SJin Yao "SampleAfterValue": "2000003", 705b5ff7f27SJin Yao "UMask": "0x40" 706b5ff7f27SJin Yao }, 707b5ff7f27SJin Yao { 708b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 709b5ff7f27SJin Yao "Counter": "0,1,2,3", 710b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 711b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 712b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 713b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 714b5ff7f27SJin Yao "MSRValue": "0x083FC00100", 715b5ff7f27SJin Yao "Offcore": "1", 716b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 717b5ff7f27SJin Yao "SampleAfterValue": "100003", 718b5ff7f27SJin Yao "UMask": "0x1" 719b5ff7f27SJin Yao }, 720b5ff7f27SJin Yao { 721b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", 722b5ff7f27SJin Yao "Counter": "0,1,2,3", 723b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 724b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 725b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 726b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 727b5ff7f27SJin Yao "MSRValue": "0x103FC00001", 728b5ff7f27SJin Yao "Offcore": "1", 729b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 730b5ff7f27SJin Yao "SampleAfterValue": "100003", 731b5ff7f27SJin Yao "UMask": "0x1" 732b5ff7f27SJin Yao }, 733b5ff7f27SJin Yao { 734b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", 735b5ff7f27SJin Yao "Counter": "0,1,2,3", 736b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 737b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 738b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 739b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 740b5ff7f27SJin Yao "MSRValue": "0x0604000020", 741b5ff7f27SJin Yao "Offcore": "1", 742b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 743b5ff7f27SJin Yao "SampleAfterValue": "100003", 744b5ff7f27SJin Yao "UMask": "0x1" 745b5ff7f27SJin Yao }, 746b5ff7f27SJin Yao { 747b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 748b5ff7f27SJin Yao "Counter": "0,1,2,3", 749b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 750b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 751b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 752b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 753b5ff7f27SJin Yao "MSRValue": "0x083FC00080", 754b5ff7f27SJin Yao "Offcore": "1", 755b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 756b5ff7f27SJin Yao "SampleAfterValue": "100003", 757b5ff7f27SJin Yao "UMask": "0x1" 758b5ff7f27SJin Yao }, 759b5ff7f27SJin Yao { 760b5ff7f27SJin Yao "BriefDescription": "Demand Data Read requests who miss L3 cache", 761b5ff7f27SJin Yao "Counter": "0,1,2,3", 762b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 763b5ff7f27SJin Yao "EventCode": "0xB0", 764b5ff7f27SJin Yao "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 765b5ff7f27SJin Yao "PublicDescription": "Demand Data Read requests who miss L3 cache.", 766b5ff7f27SJin Yao "SampleAfterValue": "100003", 767b5ff7f27SJin Yao "UMask": "0x10" 768b5ff7f27SJin Yao }, 769b5ff7f27SJin Yao { 770b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", 771b5ff7f27SJin Yao "Counter": "0,1,2,3", 772b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 773b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 774b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 775b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 776b5ff7f27SJin Yao "MSRValue": "0x063FC00080", 777b5ff7f27SJin Yao "Offcore": "1", 778b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 779b5ff7f27SJin Yao "SampleAfterValue": "100003", 780b5ff7f27SJin Yao "UMask": "0x1" 781b5ff7f27SJin Yao }, 782b5ff7f27SJin Yao { 783b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss in the L3.", 784b5ff7f27SJin Yao "Counter": "0,1,2,3", 785b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 786b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 787b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 788b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 789b5ff7f27SJin Yao "MSRValue": "0x3FBC000001", 790b5ff7f27SJin Yao "Offcore": "1", 791b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 792b5ff7f27SJin Yao "SampleAfterValue": "100003", 793b5ff7f27SJin Yao "UMask": "0x1" 794b5ff7f27SJin Yao }, 795b5ff7f27SJin Yao { 796b5ff7f27SJin Yao "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 797b5ff7f27SJin Yao "Counter": "0,1,2,3", 798b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 799b5ff7f27SJin Yao "EventCode": "0xC9", 800b5ff7f27SJin Yao "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 801b5ff7f27SJin Yao "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 802b5ff7f27SJin Yao "SampleAfterValue": "2000003", 803b5ff7f27SJin Yao "UMask": "0x20" 804b5ff7f27SJin Yao }, 805b5ff7f27SJin Yao { 806b5ff7f27SJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 807b5ff7f27SJin Yao "Counter": "0,1,2,3", 808b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 809b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 810b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 811b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 812b5ff7f27SJin Yao "MSRValue": "0x083FC00010", 813b5ff7f27SJin Yao "Offcore": "1", 814b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 815b5ff7f27SJin Yao "SampleAfterValue": "100003", 816b5ff7f27SJin Yao "UMask": "0x1" 817b5ff7f27SJin Yao }, 818b5ff7f27SJin Yao { 819b5ff7f27SJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 820b5ff7f27SJin Yao "Counter": "0,1,2,3", 821b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 822b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 823b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 824b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 825b5ff7f27SJin Yao "MSRValue": "0x083FC00120", 826b5ff7f27SJin Yao "Offcore": "1", 827b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 828b5ff7f27SJin Yao "SampleAfterValue": "100003", 829b5ff7f27SJin Yao "UMask": "0x1" 830b5ff7f27SJin Yao }, 831b5ff7f27SJin Yao { 832b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", 833b5ff7f27SJin Yao "Counter": "0,1,2,3", 834b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 835b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 836b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 837b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 838b5ff7f27SJin Yao "MSRValue": "0x103FC00004", 839b5ff7f27SJin Yao "Offcore": "1", 840b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 841b5ff7f27SJin Yao "SampleAfterValue": "100003", 842b5ff7f27SJin Yao "UMask": "0x1" 843b5ff7f27SJin Yao }, 844b5ff7f27SJin Yao { 845b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", 846b5ff7f27SJin Yao "Counter": "0,1,2,3", 847b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 848b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 849b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", 850b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 851b5ff7f27SJin Yao "MSRValue": "0x103FC00100", 852b5ff7f27SJin Yao "Offcore": "1", 853b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 854b5ff7f27SJin Yao "SampleAfterValue": "100003", 855b5ff7f27SJin Yao "UMask": "0x1" 856b5ff7f27SJin Yao }, 857b5ff7f27SJin Yao { 858b5ff7f27SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 859b5ff7f27SJin Yao "Counter": "0,1,2,3", 860b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 861b5ff7f27SJin Yao "Data_LA": "1", 862b5ff7f27SJin Yao "EventCode": "0xcd", 863b5ff7f27SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 864b5ff7f27SJin Yao "MSRIndex": "0x3F6", 865b5ff7f27SJin Yao "MSRValue": "0x100", 866b5ff7f27SJin Yao "PEBS": "2", 867b5ff7f27SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 868b5ff7f27SJin Yao "SampleAfterValue": "503", 869b5ff7f27SJin Yao "TakenAlone": "1", 870b5ff7f27SJin Yao "UMask": "0x1" 871b5ff7f27SJin Yao }, 872b5ff7f27SJin Yao { 873b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 874b5ff7f27SJin Yao "Counter": "0,1,2,3", 875b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 876b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 877b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 878b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 879b5ff7f27SJin Yao "MSRValue": "0x063FC00122", 880b5ff7f27SJin Yao "Offcore": "1", 881b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 882b5ff7f27SJin Yao "SampleAfterValue": "100003", 883b5ff7f27SJin Yao "UMask": "0x1" 884b5ff7f27SJin Yao }, 885b5ff7f27SJin Yao { 886b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", 887b5ff7f27SJin Yao "Counter": "0,1,2,3", 888b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 889b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 890b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 891b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 892b5ff7f27SJin Yao "MSRValue": "0x063FC00001", 893b5ff7f27SJin Yao "Offcore": "1", 894b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 895b5ff7f27SJin Yao "SampleAfterValue": "100003", 896b5ff7f27SJin Yao "UMask": "0x1" 897b5ff7f27SJin Yao }, 898b5ff7f27SJin Yao { 899b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 900b5ff7f27SJin Yao "Counter": "0,1,2,3", 901b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 902b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 903b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 904b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 905b5ff7f27SJin Yao "MSRValue": "0x083FC00020", 906b5ff7f27SJin Yao "Offcore": "1", 907b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 908b5ff7f27SJin Yao "SampleAfterValue": "100003", 909b5ff7f27SJin Yao "UMask": "0x1" 910b5ff7f27SJin Yao }, 911b5ff7f27SJin Yao { 912b5ff7f27SJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", 913b5ff7f27SJin Yao "Counter": "0,1,2,3", 914b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 915b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 916b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 917b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 918b5ff7f27SJin Yao "MSRValue": "0x063B800002", 919b5ff7f27SJin Yao "Offcore": "1", 920b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 921b5ff7f27SJin Yao "SampleAfterValue": "100003", 922b5ff7f27SJin Yao "UMask": "0x1" 923b5ff7f27SJin Yao }, 924b5ff7f27SJin Yao { 925b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 926b5ff7f27SJin Yao "Counter": "0,1,2,3", 927b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 928b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 929b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 930b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 931b5ff7f27SJin Yao "MSRValue": "0x103FC00491", 932b5ff7f27SJin Yao "Offcore": "1", 933b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 934b5ff7f27SJin Yao "SampleAfterValue": "100003", 935b5ff7f27SJin Yao "UMask": "0x1" 936b5ff7f27SJin Yao }, 937b5ff7f27SJin Yao { 938b5ff7f27SJin Yao "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 939b5ff7f27SJin Yao "Counter": "0,1,2,3", 940b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 941b5ff7f27SJin Yao "EventCode": "0xC9", 942b5ff7f27SJin Yao "EventName": "RTM_RETIRED.ABORTED", 943b5ff7f27SJin Yao "PEBS": "1", 944b5ff7f27SJin Yao "PublicDescription": "Number of times RTM abort was triggered.", 945b5ff7f27SJin Yao "SampleAfterValue": "2000003", 946b5ff7f27SJin Yao "UMask": "0x4" 947b5ff7f27SJin Yao }, 948b5ff7f27SJin Yao { 949b5ff7f27SJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", 950b5ff7f27SJin Yao "Counter": "0,1,2,3", 951b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 952b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 953b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", 954b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 955b5ff7f27SJin Yao "MSRValue": "0x063FC00400", 956b5ff7f27SJin Yao "Offcore": "1", 957b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 958b5ff7f27SJin Yao "SampleAfterValue": "100003", 959b5ff7f27SJin Yao "UMask": "0x1" 960b5ff7f27SJin Yao }, 961b5ff7f27SJin Yao { 962b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 963b5ff7f27SJin Yao "Counter": "0,1,2,3", 964b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 965b5ff7f27SJin Yao "EventCode": "0xC8", 966b5ff7f27SJin Yao "EventName": "HLE_RETIRED.ABORTED", 967b5ff7f27SJin Yao "PEBS": "1", 968b5ff7f27SJin Yao "PublicDescription": "Number of times HLE abort was triggered.", 969b5ff7f27SJin Yao "SampleAfterValue": "2000003", 970b5ff7f27SJin Yao "UMask": "0x4" 971b5ff7f27SJin Yao }, 972b5ff7f27SJin Yao { 973b5ff7f27SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 974b5ff7f27SJin Yao "Counter": "0,1,2,3", 975b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 976b5ff7f27SJin Yao "Data_LA": "1", 977b5ff7f27SJin Yao "EventCode": "0xcd", 978b5ff7f27SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 979b5ff7f27SJin Yao "MSRIndex": "0x3F6", 980b5ff7f27SJin Yao "MSRValue": "0x10", 981b5ff7f27SJin Yao "PEBS": "2", 982b5ff7f27SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 983b5ff7f27SJin Yao "SampleAfterValue": "20011", 984b5ff7f27SJin Yao "TakenAlone": "1", 985b5ff7f27SJin Yao "UMask": "0x1" 986b5ff7f27SJin Yao }, 987b5ff7f27SJin Yao { 988b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 989b5ff7f27SJin Yao "Counter": "0,1,2,3", 990b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 991b5ff7f27SJin Yao "EventCode": "0x54", 992b5ff7f27SJin Yao "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 993b5ff7f27SJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 994b5ff7f27SJin Yao "SampleAfterValue": "2000003", 995b5ff7f27SJin Yao "UMask": "0x20" 996b5ff7f27SJin Yao }, 997b5ff7f27SJin Yao { 998b5ff7f27SJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", 999b5ff7f27SJin Yao "Counter": "0,1,2,3", 1000b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1001b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1002b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 1003b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1004b5ff7f27SJin Yao "MSRValue": "0x083FC00400", 1005b5ff7f27SJin Yao "Offcore": "1", 1006b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1007b5ff7f27SJin Yao "SampleAfterValue": "100003", 1008b5ff7f27SJin Yao "UMask": "0x1" 1009b5ff7f27SJin Yao }, 1010b5ff7f27SJin Yao { 1011b5ff7f27SJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", 1012b5ff7f27SJin Yao "Counter": "0,1,2,3", 1013b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1014b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1015b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1016b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1017b5ff7f27SJin Yao "MSRValue": "0x063B800010", 1018b5ff7f27SJin Yao "Offcore": "1", 1019b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1020b5ff7f27SJin Yao "SampleAfterValue": "100003", 1021b5ff7f27SJin Yao "UMask": "0x1" 1022b5ff7f27SJin Yao }, 1023b5ff7f27SJin Yao { 1024b5ff7f27SJin Yao "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 1025b5ff7f27SJin Yao "Counter": "0,1,2,3", 1026b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1027b5ff7f27SJin Yao "CounterMask": "1", 1028b5ff7f27SJin Yao "EventCode": "0x60", 1029b5ff7f27SJin Yao "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 1030b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1031b5ff7f27SJin Yao "UMask": "0x10" 1032b5ff7f27SJin Yao }, 1033b5ff7f27SJin Yao { 1034b5ff7f27SJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", 1035b5ff7f27SJin Yao "Counter": "0,1,2,3", 1036b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1037b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1038b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1039b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1040b5ff7f27SJin Yao "MSRValue": "0x0604000002", 1041b5ff7f27SJin Yao "Offcore": "1", 1042b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1043b5ff7f27SJin Yao "SampleAfterValue": "100003", 1044b5ff7f27SJin Yao "UMask": "0x1" 1045b5ff7f27SJin Yao }, 1046b5ff7f27SJin Yao { 1047b5ff7f27SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 1048b5ff7f27SJin Yao "Counter": "0,1,2,3", 1049b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1050b5ff7f27SJin Yao "Data_LA": "1", 1051b5ff7f27SJin Yao "EventCode": "0xcd", 1052b5ff7f27SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 1053b5ff7f27SJin Yao "MSRIndex": "0x3F6", 1054b5ff7f27SJin Yao "MSRValue": "0x200", 1055b5ff7f27SJin Yao "PEBS": "2", 1056b5ff7f27SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 1057b5ff7f27SJin Yao "SampleAfterValue": "101", 1058b5ff7f27SJin Yao "TakenAlone": "1", 1059b5ff7f27SJin Yao "UMask": "0x1" 1060b5ff7f27SJin Yao }, 1061b5ff7f27SJin Yao { 1062b5ff7f27SJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", 1063b5ff7f27SJin Yao "Counter": "0,1,2,3", 1064b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1065b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1066b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 1067b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1068b5ff7f27SJin Yao "MSRValue": "0x103FC00400", 1069b5ff7f27SJin Yao "Offcore": "1", 1070b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1071b5ff7f27SJin Yao "SampleAfterValue": "100003", 1072b5ff7f27SJin Yao "UMask": "0x1" 1073b5ff7f27SJin Yao }, 1074b5ff7f27SJin Yao { 1075b5ff7f27SJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", 1076b5ff7f27SJin Yao "Counter": "0,1,2,3", 1077b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1078b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1079b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 1080b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1081b5ff7f27SJin Yao "MSRValue": "0x3FBC000010", 1082b5ff7f27SJin Yao "Offcore": "1", 1083b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1084b5ff7f27SJin Yao "SampleAfterValue": "100003", 1085b5ff7f27SJin Yao "UMask": "0x1" 1086b5ff7f27SJin Yao }, 1087b5ff7f27SJin Yao { 1088b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.", 1089b5ff7f27SJin Yao "Counter": "0,1,2,3", 1090b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1091b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1092b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1093b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1094b5ff7f27SJin Yao "MSRValue": "0x0604000004", 1095b5ff7f27SJin Yao "Offcore": "1", 1096b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1097b5ff7f27SJin Yao "SampleAfterValue": "100003", 1098b5ff7f27SJin Yao "UMask": "0x1" 1099b5ff7f27SJin Yao }, 1100b5ff7f27SJin Yao { 1101b5ff7f27SJin Yao "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 1102b5ff7f27SJin Yao "Counter": "0,1,2,3", 1103b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1104b5ff7f27SJin Yao "EventCode": "0x54", 1105b5ff7f27SJin Yao "EventName": "TX_MEM.ABORT_CAPACITY", 1106b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1107b5ff7f27SJin Yao "UMask": "0x2" 1108b5ff7f27SJin Yao }, 1109b5ff7f27SJin Yao { 1110b5ff7f27SJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", 1111b5ff7f27SJin Yao "Counter": "0,1,2,3", 1112b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1113b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1114b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1115b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1116b5ff7f27SJin Yao "MSRValue": "0x063B800120", 1117b5ff7f27SJin Yao "Offcore": "1", 1118b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1119b5ff7f27SJin Yao "SampleAfterValue": "100003", 1120b5ff7f27SJin Yao "UMask": "0x1" 1121b5ff7f27SJin Yao }, 1122b5ff7f27SJin Yao { 1123b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 1124b5ff7f27SJin Yao "Counter": "0,1,2,3", 1125b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1126b5ff7f27SJin Yao "EventCode": "0xC8", 1127b5ff7f27SJin Yao "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 1128b5ff7f27SJin Yao "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 1129b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1130b5ff7f27SJin Yao "UMask": "0x40" 1131b5ff7f27SJin Yao }, 1132b5ff7f27SJin Yao { 1133b5ff7f27SJin Yao "BriefDescription": "Number of times an RTM execution started.", 1134b5ff7f27SJin Yao "Counter": "0,1,2,3", 1135b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1136b5ff7f27SJin Yao "EventCode": "0xC9", 1137b5ff7f27SJin Yao "EventName": "RTM_RETIRED.START", 1138b5ff7f27SJin Yao "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 1139b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1140b5ff7f27SJin Yao "UMask": "0x1" 1141b5ff7f27SJin Yao }, 1142b5ff7f27SJin Yao { 1143b5ff7f27SJin Yao "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 1144b5ff7f27SJin Yao "Counter": "0,1,2,3", 1145b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1146b5ff7f27SJin Yao "Errata": "SKL089", 1147b5ff7f27SJin Yao "EventCode": "0xC3", 1148b5ff7f27SJin Yao "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 1149b5ff7f27SJin Yao "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 1150b5ff7f27SJin Yao "SampleAfterValue": "100003", 1151b5ff7f27SJin Yao "UMask": "0x2" 1152b5ff7f27SJin Yao }, 1153b5ff7f27SJin Yao { 1154b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 1155b5ff7f27SJin Yao "Counter": "0,1,2,3", 1156b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1157b5ff7f27SJin Yao "EventCode": "0x54", 1158b5ff7f27SJin Yao "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 1159b5ff7f27SJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 1160b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1161b5ff7f27SJin Yao "UMask": "0x10" 1162b5ff7f27SJin Yao }, 1163b5ff7f27SJin Yao { 1164b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 1165b5ff7f27SJin Yao "Counter": "0,1,2,3", 1166b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1167b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1168b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1169b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1170b5ff7f27SJin Yao "MSRValue": "0x063FC00491", 1171b5ff7f27SJin Yao "Offcore": "1", 1172b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1173b5ff7f27SJin Yao "SampleAfterValue": "100003", 1174b5ff7f27SJin Yao "UMask": "0x1" 1175b5ff7f27SJin Yao }, 1176b5ff7f27SJin Yao { 1177b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 1178b5ff7f27SJin Yao "Counter": "0,1,2,3", 1179b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1180b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1181b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 1182b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1183b5ff7f27SJin Yao "MSRValue": "0x3FBC000491", 1184b5ff7f27SJin Yao "Offcore": "1", 1185b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1186b5ff7f27SJin Yao "SampleAfterValue": "100003", 1187b5ff7f27SJin Yao "UMask": "0x1" 1188b5ff7f27SJin Yao }, 1189b5ff7f27SJin Yao { 1190b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", 1191b5ff7f27SJin Yao "Counter": "0,1,2,3", 1192b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1193b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1194b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 1195b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1196b5ff7f27SJin Yao "MSRValue": "0x083FC00001", 1197b5ff7f27SJin Yao "Offcore": "1", 1198b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1199b5ff7f27SJin Yao "SampleAfterValue": "100003", 1200b5ff7f27SJin Yao "UMask": "0x1" 1201b5ff7f27SJin Yao }, 1202b5ff7f27SJin Yao { 1203b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", 1204b5ff7f27SJin Yao "Counter": "0,1,2,3", 1205b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1206b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1207b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 1208b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1209b5ff7f27SJin Yao "MSRValue": "0x3FBC000080", 1210b5ff7f27SJin Yao "Offcore": "1", 1211b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1212b5ff7f27SJin Yao "SampleAfterValue": "100003", 1213b5ff7f27SJin Yao "UMask": "0x1" 1214b5ff7f27SJin Yao }, 1215b5ff7f27SJin Yao { 1216b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", 1217b5ff7f27SJin Yao "Counter": "0,1,2,3", 1218b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1219b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1220b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1221b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1222b5ff7f27SJin Yao "MSRValue": "0x0604000100", 1223b5ff7f27SJin Yao "Offcore": "1", 1224b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1225b5ff7f27SJin Yao "SampleAfterValue": "100003", 1226b5ff7f27SJin Yao "UMask": "0x1" 1227b5ff7f27SJin Yao }, 1228b5ff7f27SJin Yao { 1229b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", 1230b5ff7f27SJin Yao "Counter": "0,1,2,3", 1231b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1232b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1233b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1234b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1235b5ff7f27SJin Yao "MSRValue": "0x0604000080", 1236b5ff7f27SJin Yao "Offcore": "1", 1237b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1238b5ff7f27SJin Yao "SampleAfterValue": "100003", 1239b5ff7f27SJin Yao "UMask": "0x1" 1240b5ff7f27SJin Yao }, 1241b5ff7f27SJin Yao { 1242630171d4SAndi Kleen "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 1243630171d4SAndi Kleen "Counter": "0,1,2,3", 1244b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1245b5ff7f27SJin Yao "EventCode": "0xC9", 1246630171d4SAndi Kleen "EventName": "RTM_RETIRED.ABORTED_EVENTS", 1247630171d4SAndi Kleen "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 1248630171d4SAndi Kleen "SampleAfterValue": "2000003", 1249b5ff7f27SJin Yao "UMask": "0x80" 1250630171d4SAndi Kleen }, 1251630171d4SAndi Kleen { 1252b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE execution started.", 1253630171d4SAndi Kleen "Counter": "0,1,2,3", 1254b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1255b5ff7f27SJin Yao "EventCode": "0xC8", 1256b5ff7f27SJin Yao "EventName": "HLE_RETIRED.START", 1257b5ff7f27SJin Yao "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 1258b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1259b5ff7f27SJin Yao "UMask": "0x1" 1260630171d4SAndi Kleen }, 1261630171d4SAndi Kleen { 1262b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss in the L3.", 1263630171d4SAndi Kleen "Counter": "0,1,2,3", 1264b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1265630171d4SAndi Kleen "EventCode": "0xB7, 0xBB", 1266630171d4SAndi Kleen "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 1267630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1268b5ff7f27SJin Yao "MSRValue": "0x3FBC000004", 1269b5ff7f27SJin Yao "Offcore": "1", 1270b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1271630171d4SAndi Kleen "SampleAfterValue": "100003", 1272b5ff7f27SJin Yao "UMask": "0x1" 1273630171d4SAndi Kleen }, 1274630171d4SAndi Kleen { 1275b5ff7f27SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 1276630171d4SAndi Kleen "Counter": "0,1,2,3", 1277b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1278b5ff7f27SJin Yao "Data_LA": "1", 1279b5ff7f27SJin Yao "EventCode": "0xcd", 1280b5ff7f27SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 1281b5ff7f27SJin Yao "MSRIndex": "0x3F6", 1282b5ff7f27SJin Yao "MSRValue": "0x80", 1283b5ff7f27SJin Yao "PEBS": "2", 1284b5ff7f27SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 1285b5ff7f27SJin Yao "SampleAfterValue": "1009", 1286b5ff7f27SJin Yao "TakenAlone": "1", 1287b5ff7f27SJin Yao "UMask": "0x1" 1288630171d4SAndi Kleen }, 1289630171d4SAndi Kleen { 1290b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 1291630171d4SAndi Kleen "Counter": "0,1,2,3", 1292b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1293630171d4SAndi Kleen "EventCode": "0xB7, 0xBB", 1294630171d4SAndi Kleen "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 1295630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1296b5ff7f27SJin Yao "MSRValue": "0x083FC00491", 1297b5ff7f27SJin Yao "Offcore": "1", 1298b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1299630171d4SAndi Kleen "SampleAfterValue": "100003", 1300b5ff7f27SJin Yao "UMask": "0x1" 1301630171d4SAndi Kleen }, 1302630171d4SAndi Kleen { 1303b5ff7f27SJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 1304630171d4SAndi Kleen "Counter": "0,1,2,3", 1305b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1306b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1307b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 1308630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1309b5ff7f27SJin Yao "MSRValue": "0x103FC00120", 1310b5ff7f27SJin Yao "Offcore": "1", 1311b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1312630171d4SAndi Kleen "SampleAfterValue": "100003", 1313b5ff7f27SJin Yao "UMask": "0x1" 1314630171d4SAndi Kleen }, 1315630171d4SAndi Kleen { 1316b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", 1317630171d4SAndi Kleen "Counter": "0,1,2,3", 1318b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1319b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1320b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1321630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1322b5ff7f27SJin Yao "MSRValue": "0x063FC00100", 1323b5ff7f27SJin Yao "Offcore": "1", 1324b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1325630171d4SAndi Kleen "SampleAfterValue": "100003", 1326b5ff7f27SJin Yao "UMask": "0x1" 1327630171d4SAndi Kleen }, 1328630171d4SAndi Kleen { 1329b5ff7f27SJin Yao "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 1330630171d4SAndi Kleen "Counter": "0,1,2,3", 1331b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1332b5ff7f27SJin Yao "CounterMask": "6", 1333b5ff7f27SJin Yao "EventCode": "0xA3", 1334b5ff7f27SJin Yao "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 1335b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1336b5ff7f27SJin Yao "UMask": "0x6" 1337630171d4SAndi Kleen }, 1338630171d4SAndi Kleen { 1339b5ff7f27SJin Yao "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 1340630171d4SAndi Kleen "Counter": "0,1,2,3", 1341b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1342b5ff7f27SJin Yao "EventCode": "0xC8", 1343b5ff7f27SJin Yao "EventName": "HLE_RETIRED.ABORTED_EVENTS", 1344b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1345b5ff7f27SJin Yao "UMask": "0x80" 1346630171d4SAndi Kleen }, 1347630171d4SAndi Kleen { 1348b5ff7f27SJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", 1349630171d4SAndi Kleen "Counter": "0,1,2,3", 1350b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1351630171d4SAndi Kleen "EventCode": "0xB7, 0xBB", 1352630171d4SAndi Kleen "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1353630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1354b5ff7f27SJin Yao "MSRValue": "0x0604000122", 1355b5ff7f27SJin Yao "Offcore": "1", 1356b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1357630171d4SAndi Kleen "SampleAfterValue": "100003", 1358b5ff7f27SJin Yao "UMask": "0x1" 1359b5ff7f27SJin Yao }, 1360b5ff7f27SJin Yao { 1361b5ff7f27SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 1362b5ff7f27SJin Yao "Counter": "0,1,2,3", 1363b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1364b5ff7f27SJin Yao "Data_LA": "1", 1365b5ff7f27SJin Yao "EventCode": "0xcd", 1366b5ff7f27SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 1367b5ff7f27SJin Yao "MSRIndex": "0x3F6", 1368b5ff7f27SJin Yao "MSRValue": "0x4", 1369b5ff7f27SJin Yao "PEBS": "2", 1370b5ff7f27SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 1371b5ff7f27SJin Yao "SampleAfterValue": "100003", 1372b5ff7f27SJin Yao "TakenAlone": "1", 1373b5ff7f27SJin Yao "UMask": "0x1" 1374b5ff7f27SJin Yao }, 1375b5ff7f27SJin Yao { 1376b5ff7f27SJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 1377b5ff7f27SJin Yao "Counter": "0,1,2,3", 1378b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1379b5ff7f27SJin Yao "Data_LA": "1", 1380b5ff7f27SJin Yao "EventCode": "0xcd", 1381b5ff7f27SJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 1382b5ff7f27SJin Yao "MSRIndex": "0x3F6", 1383b5ff7f27SJin Yao "MSRValue": "0x8", 1384b5ff7f27SJin Yao "PEBS": "2", 1385b5ff7f27SJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 1386b5ff7f27SJin Yao "SampleAfterValue": "50021", 1387b5ff7f27SJin Yao "TakenAlone": "1", 1388b5ff7f27SJin Yao "UMask": "0x1" 1389b5ff7f27SJin Yao }, 1390b5ff7f27SJin Yao { 1391b5ff7f27SJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", 1392b5ff7f27SJin Yao "Counter": "0,1,2,3", 1393b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1394b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1395b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1396b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1397b5ff7f27SJin Yao "MSRValue": "0x0604000400", 1398b5ff7f27SJin Yao "Offcore": "1", 1399b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1400b5ff7f27SJin Yao "SampleAfterValue": "100003", 1401b5ff7f27SJin Yao "UMask": "0x1" 1402630171d4SAndi Kleen } 1403630171d4SAndi Kleen]