1630171d4SAndi Kleen[ 2630171d4SAndi Kleen { 32c72404eSJin Yao "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4630171d4SAndi Kleen "Counter": "0,1,2,3", 52c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 62c72404eSJin Yao "CounterMask": "2", 72c72404eSJin Yao "EventCode": "0xA3", 82c72404eSJin Yao "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 92c72404eSJin Yao "SampleAfterValue": "2000003", 102c72404eSJin Yao "UMask": "0x2" 112c72404eSJin Yao }, 122c72404eSJin Yao { 132c72404eSJin Yao "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 142c72404eSJin Yao "Counter": "0,1,2,3", 152c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 162c72404eSJin Yao "CounterMask": "6", 172c72404eSJin Yao "EventCode": "0xA3", 182c72404eSJin Yao "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 192c72404eSJin Yao "SampleAfterValue": "2000003", 202c72404eSJin Yao "UMask": "0x6" 212c72404eSJin Yao }, 222c72404eSJin Yao { 232c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 242c72404eSJin Yao "Counter": "0,1,2,3", 252c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 262c72404eSJin Yao "EventCode": "0xC8", 272c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED", 282c72404eSJin Yao "PEBS": "1", 292c72404eSJin Yao "PublicDescription": "Number of times HLE abort was triggered.", 302c72404eSJin Yao "SampleAfterValue": "2000003", 312c72404eSJin Yao "UMask": "0x4" 322c72404eSJin Yao }, 332c72404eSJin Yao { 342c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 352c72404eSJin Yao "Counter": "0,1,2,3", 362c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 372c72404eSJin Yao "EventCode": "0xC8", 382c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_EVENTS", 392c72404eSJin Yao "SampleAfterValue": "2000003", 402c72404eSJin Yao "UMask": "0x80" 412c72404eSJin Yao }, 422c72404eSJin Yao { 432c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 442c72404eSJin Yao "Counter": "0,1,2,3", 452c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 462c72404eSJin Yao "EventCode": "0xC8", 472c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_MEM", 482c72404eSJin Yao "SampleAfterValue": "2000003", 492c72404eSJin Yao "UMask": "0x8" 502c72404eSJin Yao }, 512c72404eSJin Yao { 522c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 532c72404eSJin Yao "Counter": "0,1,2,3", 542c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 552c72404eSJin Yao "EventCode": "0xC8", 562c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 572c72404eSJin Yao "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 582c72404eSJin Yao "SampleAfterValue": "2000003", 592c72404eSJin Yao "UMask": "0x40" 602c72404eSJin Yao }, 612c72404eSJin Yao { 622c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 632c72404eSJin Yao "Counter": "0,1,2,3", 642c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 652c72404eSJin Yao "EventCode": "0xC8", 662c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_TIMER", 672c72404eSJin Yao "SampleAfterValue": "2000003", 682c72404eSJin Yao "UMask": "0x10" 692c72404eSJin Yao }, 702c72404eSJin Yao { 712c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 722c72404eSJin Yao "Counter": "0,1,2,3", 732c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 742c72404eSJin Yao "EventCode": "0xC8", 752c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 762c72404eSJin Yao "SampleAfterValue": "2000003", 772c72404eSJin Yao "UMask": "0x20" 782c72404eSJin Yao }, 792c72404eSJin Yao { 802c72404eSJin Yao "BriefDescription": "Number of times an HLE execution successfully committed", 812c72404eSJin Yao "Counter": "0,1,2,3", 822c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 832c72404eSJin Yao "EventCode": "0xC8", 842c72404eSJin Yao "EventName": "HLE_RETIRED.COMMIT", 852c72404eSJin Yao "PublicDescription": "Number of times HLE commit succeeded.", 862c72404eSJin Yao "SampleAfterValue": "2000003", 872c72404eSJin Yao "UMask": "0x2" 882c72404eSJin Yao }, 892c72404eSJin Yao { 902c72404eSJin Yao "BriefDescription": "Number of times an HLE execution started.", 912c72404eSJin Yao "Counter": "0,1,2,3", 922c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 932c72404eSJin Yao "EventCode": "0xC8", 942c72404eSJin Yao "EventName": "HLE_RETIRED.START", 952c72404eSJin Yao "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 962c72404eSJin Yao "SampleAfterValue": "2000003", 97b5ff7f27SJin Yao "UMask": "0x1" 98630171d4SAndi Kleen }, 99630171d4SAndi Kleen { 1002c72404eSJin Yao "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 1012c72404eSJin Yao "Counter": "0,1,2,3", 1022c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1032c72404eSJin Yao "Errata": "SKL089", 1042c72404eSJin Yao "EventCode": "0xC3", 1052c72404eSJin Yao "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 1062c72404eSJin Yao "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 1072c72404eSJin Yao "SampleAfterValue": "100003", 1082c72404eSJin Yao "UMask": "0x2" 1092c72404eSJin Yao }, 1102c72404eSJin Yao { 1112c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 112630171d4SAndi Kleen "Counter": "0,1,2,3", 113b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1142c72404eSJin Yao "Data_LA": "1", 1152c72404eSJin Yao "EventCode": "0xcd", 1162c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 1172c72404eSJin Yao "MSRIndex": "0x3F6", 1182c72404eSJin Yao "MSRValue": "0x80", 1192c72404eSJin Yao "PEBS": "2", 1202c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 1212c72404eSJin Yao "SampleAfterValue": "1009", 1222c72404eSJin Yao "TakenAlone": "1", 123b5ff7f27SJin Yao "UMask": "0x1" 124630171d4SAndi Kleen }, 125630171d4SAndi Kleen { 1262c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 1272c72404eSJin Yao "Counter": "0,1,2,3", 1282c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1292c72404eSJin Yao "Data_LA": "1", 1302c72404eSJin Yao "EventCode": "0xcd", 1312c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 1322c72404eSJin Yao "MSRIndex": "0x3F6", 1332c72404eSJin Yao "MSRValue": "0x10", 1342c72404eSJin Yao "PEBS": "2", 1352c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 1362c72404eSJin Yao "SampleAfterValue": "20011", 1372c72404eSJin Yao "TakenAlone": "1", 1382c72404eSJin Yao "UMask": "0x1" 1392c72404eSJin Yao }, 1402c72404eSJin Yao { 1412c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 1422c72404eSJin Yao "Counter": "0,1,2,3", 1432c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1442c72404eSJin Yao "Data_LA": "1", 1452c72404eSJin Yao "EventCode": "0xcd", 1462c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 1472c72404eSJin Yao "MSRIndex": "0x3F6", 1482c72404eSJin Yao "MSRValue": "0x100", 1492c72404eSJin Yao "PEBS": "2", 1502c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 1512c72404eSJin Yao "SampleAfterValue": "503", 1522c72404eSJin Yao "TakenAlone": "1", 1532c72404eSJin Yao "UMask": "0x1" 1542c72404eSJin Yao }, 1552c72404eSJin Yao { 1562c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 1572c72404eSJin Yao "Counter": "0,1,2,3", 1582c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1592c72404eSJin Yao "Data_LA": "1", 1602c72404eSJin Yao "EventCode": "0xcd", 1612c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 1622c72404eSJin Yao "MSRIndex": "0x3F6", 1632c72404eSJin Yao "MSRValue": "0x20", 1642c72404eSJin Yao "PEBS": "2", 1652c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 1662c72404eSJin Yao "SampleAfterValue": "100007", 1672c72404eSJin Yao "TakenAlone": "1", 1682c72404eSJin Yao "UMask": "0x1" 1692c72404eSJin Yao }, 1702c72404eSJin Yao { 1712c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 1722c72404eSJin Yao "Counter": "0,1,2,3", 1732c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1742c72404eSJin Yao "Data_LA": "1", 1752c72404eSJin Yao "EventCode": "0xcd", 1762c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 1772c72404eSJin Yao "MSRIndex": "0x3F6", 1782c72404eSJin Yao "MSRValue": "0x4", 1792c72404eSJin Yao "PEBS": "2", 1802c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 1812c72404eSJin Yao "SampleAfterValue": "100003", 1822c72404eSJin Yao "TakenAlone": "1", 1832c72404eSJin Yao "UMask": "0x1" 1842c72404eSJin Yao }, 1852c72404eSJin Yao { 1862c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 1872c72404eSJin Yao "Counter": "0,1,2,3", 1882c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1892c72404eSJin Yao "Data_LA": "1", 1902c72404eSJin Yao "EventCode": "0xcd", 1912c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 1922c72404eSJin Yao "MSRIndex": "0x3F6", 1932c72404eSJin Yao "MSRValue": "0x200", 1942c72404eSJin Yao "PEBS": "2", 1952c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 1962c72404eSJin Yao "SampleAfterValue": "101", 1972c72404eSJin Yao "TakenAlone": "1", 1982c72404eSJin Yao "UMask": "0x1" 1992c72404eSJin Yao }, 2002c72404eSJin Yao { 2012c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 2022c72404eSJin Yao "Counter": "0,1,2,3", 2032c72404eSJin Yao "CounterHTOff": "0,1,2,3", 2042c72404eSJin Yao "Data_LA": "1", 2052c72404eSJin Yao "EventCode": "0xcd", 2062c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 2072c72404eSJin Yao "MSRIndex": "0x3F6", 2082c72404eSJin Yao "MSRValue": "0x40", 2092c72404eSJin Yao "PEBS": "2", 2102c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 2112c72404eSJin Yao "SampleAfterValue": "2003", 2122c72404eSJin Yao "TakenAlone": "1", 2132c72404eSJin Yao "UMask": "0x1" 2142c72404eSJin Yao }, 2152c72404eSJin Yao { 2162c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 2172c72404eSJin Yao "Counter": "0,1,2,3", 2182c72404eSJin Yao "CounterHTOff": "0,1,2,3", 2192c72404eSJin Yao "Data_LA": "1", 2202c72404eSJin Yao "EventCode": "0xcd", 2212c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 2222c72404eSJin Yao "MSRIndex": "0x3F6", 2232c72404eSJin Yao "MSRValue": "0x8", 2242c72404eSJin Yao "PEBS": "2", 2252c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 2262c72404eSJin Yao "SampleAfterValue": "50021", 2272c72404eSJin Yao "TakenAlone": "1", 2282c72404eSJin Yao "UMask": "0x1" 2292c72404eSJin Yao }, 2302c72404eSJin Yao { 2312c72404eSJin Yao "BriefDescription": "Demand Data Read requests who miss L3 cache", 2322c72404eSJin Yao "Counter": "0,1,2,3", 2332c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 2342c72404eSJin Yao "EventCode": "0xB0", 2352c72404eSJin Yao "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 2362c72404eSJin Yao "PublicDescription": "Demand Data Read requests who miss L3 cache.", 2372c72404eSJin Yao "SampleAfterValue": "100003", 2382c72404eSJin Yao "UMask": "0x10" 2392c72404eSJin Yao }, 2402c72404eSJin Yao { 2412c72404eSJin Yao "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 2422c72404eSJin Yao "Counter": "0,1,2,3", 2432c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 2442c72404eSJin Yao "CounterMask": "1", 2452c72404eSJin Yao "EventCode": "0x60", 2462c72404eSJin Yao "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 2472c72404eSJin Yao "SampleAfterValue": "2000003", 2482c72404eSJin Yao "UMask": "0x10" 2492c72404eSJin Yao }, 2502c72404eSJin Yao { 2512c72404eSJin Yao "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 2522c72404eSJin Yao "Counter": "0,1,2,3", 2532c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 2542c72404eSJin Yao "EventCode": "0x60", 2552c72404eSJin Yao "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 2562c72404eSJin Yao "SampleAfterValue": "2000003", 2572c72404eSJin Yao "UMask": "0x10" 2582c72404eSJin Yao }, 2592c72404eSJin Yao { 26019f2d40cSAndi Kleen "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 261630171d4SAndi Kleen "Counter": "0,1,2,3", 262b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 26319f2d40cSAndi Kleen "CounterMask": "6", 264630171d4SAndi Kleen "EventCode": "0x60", 265b5ff7f27SJin Yao "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 266630171d4SAndi Kleen "SampleAfterValue": "2000003", 267b5ff7f27SJin Yao "UMask": "0x10" 268630171d4SAndi Kleen }, 269630171d4SAndi Kleen { 2702c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 271630171d4SAndi Kleen "Counter": "0,1,2,3", 272b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 273b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 2742c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 275b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 2762c72404eSJin Yao "MSRValue": "0x3FBC000491", 277b5ff7f27SJin Yao "Offcore": "1", 278b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 279630171d4SAndi Kleen "SampleAfterValue": "100003", 280b5ff7f27SJin Yao "UMask": "0x1" 281630171d4SAndi Kleen }, 282630171d4SAndi Kleen { 2832c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 284630171d4SAndi Kleen "Counter": "0,1,2,3", 285b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 286b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 2872c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 288b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 2892c72404eSJin Yao "MSRValue": "0x103FC00491", 290b5ff7f27SJin Yao "Offcore": "1", 291b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 292630171d4SAndi Kleen "SampleAfterValue": "100003", 293b5ff7f27SJin Yao "UMask": "0x1" 294630171d4SAndi Kleen }, 295630171d4SAndi Kleen { 2962c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 297630171d4SAndi Kleen "Counter": "0,1,2,3", 298b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 299b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 3002c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 301b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 302*3bad20d7SIan Rogers "MSRValue": "0x83FC00491", 303b5ff7f27SJin Yao "Offcore": "1", 304b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 305b5ff7f27SJin Yao "SampleAfterValue": "100003", 306b5ff7f27SJin Yao "UMask": "0x1" 307630171d4SAndi Kleen }, 308630171d4SAndi Kleen { 3092c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 310630171d4SAndi Kleen "Counter": "0,1,2,3", 311b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 312b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 3132c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 314b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 315*3bad20d7SIan Rogers "MSRValue": "0x63FC00491", 316b5ff7f27SJin Yao "Offcore": "1", 317b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 318b5ff7f27SJin Yao "SampleAfterValue": "100003", 319b5ff7f27SJin Yao "UMask": "0x1" 320630171d4SAndi Kleen }, 321630171d4SAndi Kleen { 3222c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", 323630171d4SAndi Kleen "Counter": "0,1,2,3", 324b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 325b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 3262c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 327b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 328*3bad20d7SIan Rogers "MSRValue": "0x604000491", 329b5ff7f27SJin Yao "Offcore": "1", 330b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 331b5ff7f27SJin Yao "SampleAfterValue": "100003", 332b5ff7f27SJin Yao "UMask": "0x1" 333630171d4SAndi Kleen }, 334630171d4SAndi Kleen { 3352c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", 336b5ff7f27SJin Yao "Counter": "0,1,2,3", 337b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 338b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 3392c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 340b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 341*3bad20d7SIan Rogers "MSRValue": "0x63B800491", 342b5ff7f27SJin Yao "Offcore": "1", 343b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 344b5ff7f27SJin Yao "SampleAfterValue": "100003", 345b5ff7f27SJin Yao "UMask": "0x1" 346b5ff7f27SJin Yao }, 347b5ff7f27SJin Yao { 348b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss in the L3.", 349b5ff7f27SJin Yao "Counter": "0,1,2,3", 350b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 351b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 352b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 353b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 354b5ff7f27SJin Yao "MSRValue": "0x3FBC000490", 355b5ff7f27SJin Yao "Offcore": "1", 356b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 357b5ff7f27SJin Yao "SampleAfterValue": "100003", 358b5ff7f27SJin Yao "UMask": "0x1" 359b5ff7f27SJin Yao }, 360b5ff7f27SJin Yao { 3612c72404eSJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 362b5ff7f27SJin Yao "Counter": "0,1,2,3", 363b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 364b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 3652c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 366b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 3672c72404eSJin Yao "MSRValue": "0x103FC00490", 3682c72404eSJin Yao "Offcore": "1", 3692c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3702c72404eSJin Yao "SampleAfterValue": "100003", 3712c72404eSJin Yao "UMask": "0x1" 3722c72404eSJin Yao }, 3732c72404eSJin Yao { 3742c72404eSJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 3752c72404eSJin Yao "Counter": "0,1,2,3", 3762c72404eSJin Yao "CounterHTOff": "0,1,2,3", 3772c72404eSJin Yao "EventCode": "0xB7, 0xBB", 3782c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 3792c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 380*3bad20d7SIan Rogers "MSRValue": "0x83FC00490", 3812c72404eSJin Yao "Offcore": "1", 3822c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3832c72404eSJin Yao "SampleAfterValue": "100003", 3842c72404eSJin Yao "UMask": "0x1" 3852c72404eSJin Yao }, 3862c72404eSJin Yao { 3872c72404eSJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 3882c72404eSJin Yao "Counter": "0,1,2,3", 3892c72404eSJin Yao "CounterHTOff": "0,1,2,3", 3902c72404eSJin Yao "EventCode": "0xB7, 0xBB", 3912c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 3922c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 393*3bad20d7SIan Rogers "MSRValue": "0x63FC00490", 394b5ff7f27SJin Yao "Offcore": "1", 395b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 396b5ff7f27SJin Yao "SampleAfterValue": "100003", 397b5ff7f27SJin Yao "UMask": "0x1" 398b5ff7f27SJin Yao }, 399b5ff7f27SJin Yao { 400b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", 401b5ff7f27SJin Yao "Counter": "0,1,2,3", 402b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 403b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 404b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 405b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 406*3bad20d7SIan Rogers "MSRValue": "0x604000490", 407b5ff7f27SJin Yao "Offcore": "1", 408b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 409b5ff7f27SJin Yao "SampleAfterValue": "100003", 410b5ff7f27SJin Yao "UMask": "0x1" 411b5ff7f27SJin Yao }, 412b5ff7f27SJin Yao { 4132c72404eSJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", 414b5ff7f27SJin Yao "Counter": "0,1,2,3", 415b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 416b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 4172c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 418b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 419*3bad20d7SIan Rogers "MSRValue": "0x63B800490", 4202c72404eSJin Yao "Offcore": "1", 4212c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4222c72404eSJin Yao "SampleAfterValue": "100003", 4232c72404eSJin Yao "UMask": "0x1" 4242c72404eSJin Yao }, 4252c72404eSJin Yao { 4262c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss in the L3.", 4272c72404eSJin Yao "Counter": "0,1,2,3", 4282c72404eSJin Yao "CounterHTOff": "0,1,2,3", 4292c72404eSJin Yao "EventCode": "0xB7, 0xBB", 4302c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 4312c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 4322c72404eSJin Yao "MSRValue": "0x3FBC000120", 4332c72404eSJin Yao "Offcore": "1", 4342c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4352c72404eSJin Yao "SampleAfterValue": "100003", 4362c72404eSJin Yao "UMask": "0x1" 4372c72404eSJin Yao }, 4382c72404eSJin Yao { 4392c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 4402c72404eSJin Yao "Counter": "0,1,2,3", 4412c72404eSJin Yao "CounterHTOff": "0,1,2,3", 4422c72404eSJin Yao "EventCode": "0xB7, 0xBB", 4432c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 4442c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 4452c72404eSJin Yao "MSRValue": "0x103FC00120", 4462c72404eSJin Yao "Offcore": "1", 4472c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4482c72404eSJin Yao "SampleAfterValue": "100003", 4492c72404eSJin Yao "UMask": "0x1" 4502c72404eSJin Yao }, 4512c72404eSJin Yao { 4522c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 4532c72404eSJin Yao "Counter": "0,1,2,3", 4542c72404eSJin Yao "CounterHTOff": "0,1,2,3", 4552c72404eSJin Yao "EventCode": "0xB7, 0xBB", 4562c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 4572c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 458*3bad20d7SIan Rogers "MSRValue": "0x83FC00120", 4592c72404eSJin Yao "Offcore": "1", 4602c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4612c72404eSJin Yao "SampleAfterValue": "100003", 4622c72404eSJin Yao "UMask": "0x1" 4632c72404eSJin Yao }, 4642c72404eSJin Yao { 4652c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 4662c72404eSJin Yao "Counter": "0,1,2,3", 4672c72404eSJin Yao "CounterHTOff": "0,1,2,3", 4682c72404eSJin Yao "EventCode": "0xB7, 0xBB", 4692c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 4702c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 471*3bad20d7SIan Rogers "MSRValue": "0x63FC00120", 4722c72404eSJin Yao "Offcore": "1", 4732c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4742c72404eSJin Yao "SampleAfterValue": "100003", 4752c72404eSJin Yao "UMask": "0x1" 4762c72404eSJin Yao }, 4772c72404eSJin Yao { 4782c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", 4792c72404eSJin Yao "Counter": "0,1,2,3", 4802c72404eSJin Yao "CounterHTOff": "0,1,2,3", 4812c72404eSJin Yao "EventCode": "0xB7, 0xBB", 4822c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4832c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 484*3bad20d7SIan Rogers "MSRValue": "0x604000120", 4852c72404eSJin Yao "Offcore": "1", 4862c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4872c72404eSJin Yao "SampleAfterValue": "100003", 4882c72404eSJin Yao "UMask": "0x1" 4892c72404eSJin Yao }, 4902c72404eSJin Yao { 4912c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", 4922c72404eSJin Yao "Counter": "0,1,2,3", 4932c72404eSJin Yao "CounterHTOff": "0,1,2,3", 4942c72404eSJin Yao "EventCode": "0xB7, 0xBB", 4952c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4962c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 497*3bad20d7SIan Rogers "MSRValue": "0x63B800120", 4982c72404eSJin Yao "Offcore": "1", 4992c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5002c72404eSJin Yao "SampleAfterValue": "100003", 5012c72404eSJin Yao "UMask": "0x1" 5022c72404eSJin Yao }, 5032c72404eSJin Yao { 5042c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", 5052c72404eSJin Yao "Counter": "0,1,2,3", 5062c72404eSJin Yao "CounterHTOff": "0,1,2,3", 5072c72404eSJin Yao "EventCode": "0xB7, 0xBB", 5082c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", 5092c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 5102c72404eSJin Yao "MSRValue": "0x3FBC000122", 5112c72404eSJin Yao "Offcore": "1", 5122c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5132c72404eSJin Yao "SampleAfterValue": "100003", 5142c72404eSJin Yao "UMask": "0x1" 5152c72404eSJin Yao }, 5162c72404eSJin Yao { 5172c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 5182c72404eSJin Yao "Counter": "0,1,2,3", 5192c72404eSJin Yao "CounterHTOff": "0,1,2,3", 5202c72404eSJin Yao "EventCode": "0xB7, 0xBB", 5212c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", 5222c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 5232c72404eSJin Yao "MSRValue": "0x103FC00122", 5242c72404eSJin Yao "Offcore": "1", 5252c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5262c72404eSJin Yao "SampleAfterValue": "100003", 5272c72404eSJin Yao "UMask": "0x1" 5282c72404eSJin Yao }, 5292c72404eSJin Yao { 5302c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 5312c72404eSJin Yao "Counter": "0,1,2,3", 5322c72404eSJin Yao "CounterHTOff": "0,1,2,3", 5332c72404eSJin Yao "EventCode": "0xB7, 0xBB", 5342c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5352c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 536*3bad20d7SIan Rogers "MSRValue": "0x83FC00122", 5372c72404eSJin Yao "Offcore": "1", 5382c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5392c72404eSJin Yao "SampleAfterValue": "100003", 5402c72404eSJin Yao "UMask": "0x1" 5412c72404eSJin Yao }, 5422c72404eSJin Yao { 5432c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 5442c72404eSJin Yao "Counter": "0,1,2,3", 5452c72404eSJin Yao "CounterHTOff": "0,1,2,3", 5462c72404eSJin Yao "EventCode": "0xB7, 0xBB", 5472c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 5482c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 549*3bad20d7SIan Rogers "MSRValue": "0x63FC00122", 5502c72404eSJin Yao "Offcore": "1", 5512c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5522c72404eSJin Yao "SampleAfterValue": "100003", 5532c72404eSJin Yao "UMask": "0x1" 5542c72404eSJin Yao }, 5552c72404eSJin Yao { 5562c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", 5572c72404eSJin Yao "Counter": "0,1,2,3", 5582c72404eSJin Yao "CounterHTOff": "0,1,2,3", 5592c72404eSJin Yao "EventCode": "0xB7, 0xBB", 5602c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 5612c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 562*3bad20d7SIan Rogers "MSRValue": "0x604000122", 5632c72404eSJin Yao "Offcore": "1", 5642c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5652c72404eSJin Yao "SampleAfterValue": "100003", 5662c72404eSJin Yao "UMask": "0x1" 5672c72404eSJin Yao }, 5682c72404eSJin Yao { 5692c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", 5702c72404eSJin Yao "Counter": "0,1,2,3", 5712c72404eSJin Yao "CounterHTOff": "0,1,2,3", 5722c72404eSJin Yao "EventCode": "0xB7, 0xBB", 5732c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 5742c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 575*3bad20d7SIan Rogers "MSRValue": "0x63B800122", 5762c72404eSJin Yao "Offcore": "1", 5772c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5782c72404eSJin Yao "SampleAfterValue": "100003", 5792c72404eSJin Yao "UMask": "0x1" 5802c72404eSJin Yao }, 5812c72404eSJin Yao { 5822c72404eSJin Yao "BriefDescription": "Counts all demand code reads that miss in the L3.", 5832c72404eSJin Yao "Counter": "0,1,2,3", 5842c72404eSJin Yao "CounterHTOff": "0,1,2,3", 5852c72404eSJin Yao "EventCode": "0xB7, 0xBB", 5862c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 5872c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 5882c72404eSJin Yao "MSRValue": "0x3FBC000004", 5892c72404eSJin Yao "Offcore": "1", 5902c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5912c72404eSJin Yao "SampleAfterValue": "100003", 5922c72404eSJin Yao "UMask": "0x1" 5932c72404eSJin Yao }, 5942c72404eSJin Yao { 5952c72404eSJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", 5962c72404eSJin Yao "Counter": "0,1,2,3", 5972c72404eSJin Yao "CounterHTOff": "0,1,2,3", 5982c72404eSJin Yao "EventCode": "0xB7, 0xBB", 5992c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 6002c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 6012c72404eSJin Yao "MSRValue": "0x103FC00004", 602b5ff7f27SJin Yao "Offcore": "1", 603b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 604b5ff7f27SJin Yao "SampleAfterValue": "100003", 605b5ff7f27SJin Yao "UMask": "0x1" 606b5ff7f27SJin Yao }, 607b5ff7f27SJin Yao { 608b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", 609b5ff7f27SJin Yao "Counter": "0,1,2,3", 610b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 611b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 612b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 613b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 614*3bad20d7SIan Rogers "MSRValue": "0x83FC00004", 615b5ff7f27SJin Yao "Offcore": "1", 616b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 617b5ff7f27SJin Yao "SampleAfterValue": "100003", 618b5ff7f27SJin Yao "UMask": "0x1" 619b5ff7f27SJin Yao }, 620b5ff7f27SJin Yao { 621b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.", 622b5ff7f27SJin Yao "Counter": "0,1,2,3", 623b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 624b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 625b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 626b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 627*3bad20d7SIan Rogers "MSRValue": "0x63FC00004", 628b5ff7f27SJin Yao "Offcore": "1", 629b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 630b5ff7f27SJin Yao "SampleAfterValue": "100003", 631b5ff7f27SJin Yao "UMask": "0x1" 632b5ff7f27SJin Yao }, 633b5ff7f27SJin Yao { 6342c72404eSJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.", 635b5ff7f27SJin Yao "Counter": "0,1,2,3", 636b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 637b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 6382c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 639b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 640*3bad20d7SIan Rogers "MSRValue": "0x604000004", 641b5ff7f27SJin Yao "Offcore": "1", 642b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 643b5ff7f27SJin Yao "SampleAfterValue": "100003", 644b5ff7f27SJin Yao "UMask": "0x1" 645b5ff7f27SJin Yao }, 646b5ff7f27SJin Yao { 6472c72404eSJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", 648b5ff7f27SJin Yao "Counter": "0,1,2,3", 649b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 650b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 6512c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 652b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 653*3bad20d7SIan Rogers "MSRValue": "0x63B800004", 654b5ff7f27SJin Yao "Offcore": "1", 655b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 656b5ff7f27SJin Yao "SampleAfterValue": "100003", 657b5ff7f27SJin Yao "UMask": "0x1" 658b5ff7f27SJin Yao }, 659b5ff7f27SJin Yao { 660b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss in the L3.", 661b5ff7f27SJin Yao "Counter": "0,1,2,3", 662b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 663b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 664b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 665b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 666b5ff7f27SJin Yao "MSRValue": "0x3FBC000001", 667b5ff7f27SJin Yao "Offcore": "1", 668b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 669b5ff7f27SJin Yao "SampleAfterValue": "100003", 670b5ff7f27SJin Yao "UMask": "0x1" 671b5ff7f27SJin Yao }, 672b5ff7f27SJin Yao { 6732c72404eSJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", 674b5ff7f27SJin Yao "Counter": "0,1,2,3", 675b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 676b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 6772c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 678b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 6792c72404eSJin Yao "MSRValue": "0x103FC00001", 680b5ff7f27SJin Yao "Offcore": "1", 681b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 682b5ff7f27SJin Yao "SampleAfterValue": "100003", 683b5ff7f27SJin Yao "UMask": "0x1" 684b5ff7f27SJin Yao }, 685b5ff7f27SJin Yao { 686b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", 687b5ff7f27SJin Yao "Counter": "0,1,2,3", 688b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 689b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 690b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 691b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 692*3bad20d7SIan Rogers "MSRValue": "0x83FC00001", 693b5ff7f27SJin Yao "Offcore": "1", 694b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 695b5ff7f27SJin Yao "SampleAfterValue": "100003", 696b5ff7f27SJin Yao "UMask": "0x1" 697b5ff7f27SJin Yao }, 698b5ff7f27SJin Yao { 6992c72404eSJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", 7002c72404eSJin Yao "Counter": "0,1,2,3", 7012c72404eSJin Yao "CounterHTOff": "0,1,2,3", 7022c72404eSJin Yao "EventCode": "0xB7, 0xBB", 7032c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 7042c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 705*3bad20d7SIan Rogers "MSRValue": "0x63FC00001", 7062c72404eSJin Yao "Offcore": "1", 7072c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7082c72404eSJin Yao "SampleAfterValue": "100003", 7092c72404eSJin Yao "UMask": "0x1" 7102c72404eSJin Yao }, 7112c72404eSJin Yao { 7122c72404eSJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", 7132c72404eSJin Yao "Counter": "0,1,2,3", 7142c72404eSJin Yao "CounterHTOff": "0,1,2,3", 7152c72404eSJin Yao "EventCode": "0xB7, 0xBB", 7162c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 7172c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 718*3bad20d7SIan Rogers "MSRValue": "0x604000001", 7192c72404eSJin Yao "Offcore": "1", 7202c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7212c72404eSJin Yao "SampleAfterValue": "100003", 7222c72404eSJin Yao "UMask": "0x1" 7232c72404eSJin Yao }, 7242c72404eSJin Yao { 7252c72404eSJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", 7262c72404eSJin Yao "Counter": "0,1,2,3", 7272c72404eSJin Yao "CounterHTOff": "0,1,2,3", 7282c72404eSJin Yao "EventCode": "0xB7, 0xBB", 7292c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 7302c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 731*3bad20d7SIan Rogers "MSRValue": "0x63B800001", 7322c72404eSJin Yao "Offcore": "1", 7332c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7342c72404eSJin Yao "SampleAfterValue": "100003", 7352c72404eSJin Yao "UMask": "0x1" 7362c72404eSJin Yao }, 7372c72404eSJin Yao { 7382c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", 7392c72404eSJin Yao "Counter": "0,1,2,3", 7402c72404eSJin Yao "CounterHTOff": "0,1,2,3", 7412c72404eSJin Yao "EventCode": "0xB7, 0xBB", 7422c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 7432c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 7442c72404eSJin Yao "MSRValue": "0x3FBC000002", 7452c72404eSJin Yao "Offcore": "1", 7462c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7472c72404eSJin Yao "SampleAfterValue": "100003", 7482c72404eSJin Yao "UMask": "0x1" 7492c72404eSJin Yao }, 7502c72404eSJin Yao { 7512c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", 7522c72404eSJin Yao "Counter": "0,1,2,3", 7532c72404eSJin Yao "CounterHTOff": "0,1,2,3", 7542c72404eSJin Yao "EventCode": "0xB7, 0xBB", 7552c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", 7562c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 7572c72404eSJin Yao "MSRValue": "0x103FC00002", 7582c72404eSJin Yao "Offcore": "1", 7592c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7602c72404eSJin Yao "SampleAfterValue": "100003", 7612c72404eSJin Yao "UMask": "0x1" 7622c72404eSJin Yao }, 7632c72404eSJin Yao { 7642c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", 7652c72404eSJin Yao "Counter": "0,1,2,3", 7662c72404eSJin Yao "CounterHTOff": "0,1,2,3", 7672c72404eSJin Yao "EventCode": "0xB7, 0xBB", 7682c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 7692c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 770*3bad20d7SIan Rogers "MSRValue": "0x83FC00002", 7712c72404eSJin Yao "Offcore": "1", 7722c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7732c72404eSJin Yao "SampleAfterValue": "100003", 7742c72404eSJin Yao "UMask": "0x1" 7752c72404eSJin Yao }, 7762c72404eSJin Yao { 7772c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", 7782c72404eSJin Yao "Counter": "0,1,2,3", 7792c72404eSJin Yao "CounterHTOff": "0,1,2,3", 7802c72404eSJin Yao "EventCode": "0xB7, 0xBB", 7812c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 7822c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 783*3bad20d7SIan Rogers "MSRValue": "0x63FC00002", 7842c72404eSJin Yao "Offcore": "1", 7852c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7862c72404eSJin Yao "SampleAfterValue": "100003", 7872c72404eSJin Yao "UMask": "0x1" 7882c72404eSJin Yao }, 7892c72404eSJin Yao { 7902c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", 7912c72404eSJin Yao "Counter": "0,1,2,3", 7922c72404eSJin Yao "CounterHTOff": "0,1,2,3", 7932c72404eSJin Yao "EventCode": "0xB7, 0xBB", 7942c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 7952c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 796*3bad20d7SIan Rogers "MSRValue": "0x604000002", 7972c72404eSJin Yao "Offcore": "1", 7982c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7992c72404eSJin Yao "SampleAfterValue": "100003", 8002c72404eSJin Yao "UMask": "0x1" 8012c72404eSJin Yao }, 8022c72404eSJin Yao { 8032c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", 8042c72404eSJin Yao "Counter": "0,1,2,3", 8052c72404eSJin Yao "CounterHTOff": "0,1,2,3", 8062c72404eSJin Yao "EventCode": "0xB7, 0xBB", 8072c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8082c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 809*3bad20d7SIan Rogers "MSRValue": "0x63B800002", 8102c72404eSJin Yao "Offcore": "1", 8112c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8122c72404eSJin Yao "SampleAfterValue": "100003", 8132c72404eSJin Yao "UMask": "0x1" 8142c72404eSJin Yao }, 8152c72404eSJin Yao { 8162c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", 8172c72404eSJin Yao "Counter": "0,1,2,3", 8182c72404eSJin Yao "CounterHTOff": "0,1,2,3", 8192c72404eSJin Yao "EventCode": "0xB7, 0xBB", 8202c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 8212c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 8222c72404eSJin Yao "MSRValue": "0x3FBC000400", 8232c72404eSJin Yao "Offcore": "1", 8242c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8252c72404eSJin Yao "SampleAfterValue": "100003", 8262c72404eSJin Yao "UMask": "0x1" 8272c72404eSJin Yao }, 8282c72404eSJin Yao { 8292c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", 8302c72404eSJin Yao "Counter": "0,1,2,3", 8312c72404eSJin Yao "CounterHTOff": "0,1,2,3", 8322c72404eSJin Yao "EventCode": "0xB7, 0xBB", 8332c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 8342c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 8352c72404eSJin Yao "MSRValue": "0x103FC00400", 8362c72404eSJin Yao "Offcore": "1", 8372c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8382c72404eSJin Yao "SampleAfterValue": "100003", 8392c72404eSJin Yao "UMask": "0x1" 8402c72404eSJin Yao }, 8412c72404eSJin Yao { 8422c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", 8432c72404eSJin Yao "Counter": "0,1,2,3", 8442c72404eSJin Yao "CounterHTOff": "0,1,2,3", 8452c72404eSJin Yao "EventCode": "0xB7, 0xBB", 8462c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 8472c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 848*3bad20d7SIan Rogers "MSRValue": "0x83FC00400", 8492c72404eSJin Yao "Offcore": "1", 8502c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8512c72404eSJin Yao "SampleAfterValue": "100003", 8522c72404eSJin Yao "UMask": "0x1" 8532c72404eSJin Yao }, 8542c72404eSJin Yao { 8552c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", 8562c72404eSJin Yao "Counter": "0,1,2,3", 8572c72404eSJin Yao "CounterHTOff": "0,1,2,3", 8582c72404eSJin Yao "EventCode": "0xB7, 0xBB", 8592c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", 8602c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 861*3bad20d7SIan Rogers "MSRValue": "0x63FC00400", 8622c72404eSJin Yao "Offcore": "1", 8632c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8642c72404eSJin Yao "SampleAfterValue": "100003", 8652c72404eSJin Yao "UMask": "0x1" 8662c72404eSJin Yao }, 8672c72404eSJin Yao { 8682c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", 8692c72404eSJin Yao "Counter": "0,1,2,3", 8702c72404eSJin Yao "CounterHTOff": "0,1,2,3", 8712c72404eSJin Yao "EventCode": "0xB7, 0xBB", 8722c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 8732c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 874*3bad20d7SIan Rogers "MSRValue": "0x604000400", 8752c72404eSJin Yao "Offcore": "1", 8762c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8772c72404eSJin Yao "SampleAfterValue": "100003", 8782c72404eSJin Yao "UMask": "0x1" 8792c72404eSJin Yao }, 8802c72404eSJin Yao { 8812c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", 8822c72404eSJin Yao "Counter": "0,1,2,3", 8832c72404eSJin Yao "CounterHTOff": "0,1,2,3", 8842c72404eSJin Yao "EventCode": "0xB7, 0xBB", 8852c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8862c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 887*3bad20d7SIan Rogers "MSRValue": "0x63B800400", 8882c72404eSJin Yao "Offcore": "1", 8892c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8902c72404eSJin Yao "SampleAfterValue": "100003", 8912c72404eSJin Yao "UMask": "0x1" 8922c72404eSJin Yao }, 8932c72404eSJin Yao { 8942c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", 8952c72404eSJin Yao "Counter": "0,1,2,3", 8962c72404eSJin Yao "CounterHTOff": "0,1,2,3", 8972c72404eSJin Yao "EventCode": "0xB7, 0xBB", 8982c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 8992c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 9002c72404eSJin Yao "MSRValue": "0x3FBC000010", 9012c72404eSJin Yao "Offcore": "1", 9022c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9032c72404eSJin Yao "SampleAfterValue": "100003", 9042c72404eSJin Yao "UMask": "0x1" 9052c72404eSJin Yao }, 9062c72404eSJin Yao { 9072c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", 9082c72404eSJin Yao "Counter": "0,1,2,3", 9092c72404eSJin Yao "CounterHTOff": "0,1,2,3", 9102c72404eSJin Yao "EventCode": "0xB7, 0xBB", 9112c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 9122c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 9132c72404eSJin Yao "MSRValue": "0x103FC00010", 9142c72404eSJin Yao "Offcore": "1", 9152c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9162c72404eSJin Yao "SampleAfterValue": "100003", 9172c72404eSJin Yao "UMask": "0x1" 9182c72404eSJin Yao }, 9192c72404eSJin Yao { 9202c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 9212c72404eSJin Yao "Counter": "0,1,2,3", 9222c72404eSJin Yao "CounterHTOff": "0,1,2,3", 9232c72404eSJin Yao "EventCode": "0xB7, 0xBB", 9242c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9252c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 926*3bad20d7SIan Rogers "MSRValue": "0x83FC00010", 9272c72404eSJin Yao "Offcore": "1", 9282c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9292c72404eSJin Yao "SampleAfterValue": "100003", 9302c72404eSJin Yao "UMask": "0x1" 9312c72404eSJin Yao }, 9322c72404eSJin Yao { 9332c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", 9342c72404eSJin Yao "Counter": "0,1,2,3", 9352c72404eSJin Yao "CounterHTOff": "0,1,2,3", 9362c72404eSJin Yao "EventCode": "0xB7, 0xBB", 9372c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 9382c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 939*3bad20d7SIan Rogers "MSRValue": "0x63FC00010", 9402c72404eSJin Yao "Offcore": "1", 9412c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9422c72404eSJin Yao "SampleAfterValue": "100003", 9432c72404eSJin Yao "UMask": "0x1" 9442c72404eSJin Yao }, 9452c72404eSJin Yao { 9462c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", 9472c72404eSJin Yao "Counter": "0,1,2,3", 9482c72404eSJin Yao "CounterHTOff": "0,1,2,3", 9492c72404eSJin Yao "EventCode": "0xB7, 0xBB", 9502c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9512c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 952*3bad20d7SIan Rogers "MSRValue": "0x604000010", 9532c72404eSJin Yao "Offcore": "1", 9542c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9552c72404eSJin Yao "SampleAfterValue": "100003", 9562c72404eSJin Yao "UMask": "0x1" 9572c72404eSJin Yao }, 9582c72404eSJin Yao { 9592c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", 9602c72404eSJin Yao "Counter": "0,1,2,3", 9612c72404eSJin Yao "CounterHTOff": "0,1,2,3", 9622c72404eSJin Yao "EventCode": "0xB7, 0xBB", 9632c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9642c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 965*3bad20d7SIan Rogers "MSRValue": "0x63B800010", 9662c72404eSJin Yao "Offcore": "1", 9672c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9682c72404eSJin Yao "SampleAfterValue": "100003", 9692c72404eSJin Yao "UMask": "0x1" 9702c72404eSJin Yao }, 9712c72404eSJin Yao { 9722c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", 9732c72404eSJin Yao "Counter": "0,1,2,3", 9742c72404eSJin Yao "CounterHTOff": "0,1,2,3", 9752c72404eSJin Yao "EventCode": "0xB7, 0xBB", 9762c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", 9772c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 9782c72404eSJin Yao "MSRValue": "0x3FBC000020", 9792c72404eSJin Yao "Offcore": "1", 9802c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9812c72404eSJin Yao "SampleAfterValue": "100003", 9822c72404eSJin Yao "UMask": "0x1" 9832c72404eSJin Yao }, 9842c72404eSJin Yao { 9852c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", 9862c72404eSJin Yao "Counter": "0,1,2,3", 9872c72404eSJin Yao "CounterHTOff": "0,1,2,3", 9882c72404eSJin Yao "EventCode": "0xB7, 0xBB", 9892c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", 9902c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 9912c72404eSJin Yao "MSRValue": "0x103FC00020", 9922c72404eSJin Yao "Offcore": "1", 9932c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9942c72404eSJin Yao "SampleAfterValue": "100003", 9952c72404eSJin Yao "UMask": "0x1" 9962c72404eSJin Yao }, 9972c72404eSJin Yao { 9982c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 9992c72404eSJin Yao "Counter": "0,1,2,3", 10002c72404eSJin Yao "CounterHTOff": "0,1,2,3", 10012c72404eSJin Yao "EventCode": "0xB7, 0xBB", 10022c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 10032c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1004*3bad20d7SIan Rogers "MSRValue": "0x83FC00020", 10052c72404eSJin Yao "Offcore": "1", 10062c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 10072c72404eSJin Yao "SampleAfterValue": "100003", 10082c72404eSJin Yao "UMask": "0x1" 10092c72404eSJin Yao }, 10102c72404eSJin Yao { 10112c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", 10122c72404eSJin Yao "Counter": "0,1,2,3", 10132c72404eSJin Yao "CounterHTOff": "0,1,2,3", 10142c72404eSJin Yao "EventCode": "0xB7, 0xBB", 10152c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 10162c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1017*3bad20d7SIan Rogers "MSRValue": "0x63FC00020", 10182c72404eSJin Yao "Offcore": "1", 10192c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 10202c72404eSJin Yao "SampleAfterValue": "100003", 10212c72404eSJin Yao "UMask": "0x1" 10222c72404eSJin Yao }, 10232c72404eSJin Yao { 10242c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", 10252c72404eSJin Yao "Counter": "0,1,2,3", 10262c72404eSJin Yao "CounterHTOff": "0,1,2,3", 10272c72404eSJin Yao "EventCode": "0xB7, 0xBB", 10282c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 10292c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1030*3bad20d7SIan Rogers "MSRValue": "0x604000020", 10312c72404eSJin Yao "Offcore": "1", 10322c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 10332c72404eSJin Yao "SampleAfterValue": "100003", 10342c72404eSJin Yao "UMask": "0x1" 10352c72404eSJin Yao }, 10362c72404eSJin Yao { 10372c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", 10382c72404eSJin Yao "Counter": "0,1,2,3", 10392c72404eSJin Yao "CounterHTOff": "0,1,2,3", 10402c72404eSJin Yao "EventCode": "0xB7, 0xBB", 10412c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 10422c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1043*3bad20d7SIan Rogers "MSRValue": "0x63B800020", 10442c72404eSJin Yao "Offcore": "1", 10452c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 10462c72404eSJin Yao "SampleAfterValue": "100003", 10472c72404eSJin Yao "UMask": "0x1" 10482c72404eSJin Yao }, 10492c72404eSJin Yao { 1050b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", 1051b5ff7f27SJin Yao "Counter": "0,1,2,3", 1052b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1053b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1054b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 1055b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1056b5ff7f27SJin Yao "MSRValue": "0x3FBC000080", 1057b5ff7f27SJin Yao "Offcore": "1", 1058b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1059b5ff7f27SJin Yao "SampleAfterValue": "100003", 1060b5ff7f27SJin Yao "UMask": "0x1" 1061b5ff7f27SJin Yao }, 1062b5ff7f27SJin Yao { 10632c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", 1064b5ff7f27SJin Yao "Counter": "0,1,2,3", 1065b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1066b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 10672c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 1068b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 10692c72404eSJin Yao "MSRValue": "0x103FC00080", 10702c72404eSJin Yao "Offcore": "1", 10712c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 10722c72404eSJin Yao "SampleAfterValue": "100003", 10732c72404eSJin Yao "UMask": "0x1" 10742c72404eSJin Yao }, 10752c72404eSJin Yao { 10762c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 10772c72404eSJin Yao "Counter": "0,1,2,3", 10782c72404eSJin Yao "CounterHTOff": "0,1,2,3", 10792c72404eSJin Yao "EventCode": "0xB7, 0xBB", 10802c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 10812c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1082*3bad20d7SIan Rogers "MSRValue": "0x83FC00080", 10832c72404eSJin Yao "Offcore": "1", 10842c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 10852c72404eSJin Yao "SampleAfterValue": "100003", 10862c72404eSJin Yao "UMask": "0x1" 10872c72404eSJin Yao }, 10882c72404eSJin Yao { 10892c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", 10902c72404eSJin Yao "Counter": "0,1,2,3", 10912c72404eSJin Yao "CounterHTOff": "0,1,2,3", 10922c72404eSJin Yao "EventCode": "0xB7, 0xBB", 10932c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 10942c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1095*3bad20d7SIan Rogers "MSRValue": "0x63FC00080", 1096b5ff7f27SJin Yao "Offcore": "1", 1097b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1098b5ff7f27SJin Yao "SampleAfterValue": "100003", 1099b5ff7f27SJin Yao "UMask": "0x1" 1100b5ff7f27SJin Yao }, 1101b5ff7f27SJin Yao { 1102b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", 1103b5ff7f27SJin Yao "Counter": "0,1,2,3", 1104b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1105b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1106b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1107b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1108*3bad20d7SIan Rogers "MSRValue": "0x604000080", 1109b5ff7f27SJin Yao "Offcore": "1", 1110b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1111b5ff7f27SJin Yao "SampleAfterValue": "100003", 1112b5ff7f27SJin Yao "UMask": "0x1" 1113b5ff7f27SJin Yao }, 1114b5ff7f27SJin Yao { 11152c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", 1116630171d4SAndi Kleen "Counter": "0,1,2,3", 1117b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1118630171d4SAndi Kleen "EventCode": "0xB7, 0xBB", 11192c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1120630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1121*3bad20d7SIan Rogers "MSRValue": "0x63B800080", 1122b5ff7f27SJin Yao "Offcore": "1", 1123b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1124630171d4SAndi Kleen "SampleAfterValue": "100003", 1125b5ff7f27SJin Yao "UMask": "0x1" 1126630171d4SAndi Kleen }, 1127630171d4SAndi Kleen { 11282c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", 1129630171d4SAndi Kleen "Counter": "0,1,2,3", 1130b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1131630171d4SAndi Kleen "EventCode": "0xB7, 0xBB", 11322c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", 1133630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 11342c72404eSJin Yao "MSRValue": "0x3FBC000100", 1135b5ff7f27SJin Yao "Offcore": "1", 1136b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1137630171d4SAndi Kleen "SampleAfterValue": "100003", 1138b5ff7f27SJin Yao "UMask": "0x1" 1139630171d4SAndi Kleen }, 1140630171d4SAndi Kleen { 11412c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", 1142630171d4SAndi Kleen "Counter": "0,1,2,3", 1143b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1144b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 11452c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", 1146630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 11472c72404eSJin Yao "MSRValue": "0x103FC00100", 11482c72404eSJin Yao "Offcore": "1", 11492c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 11502c72404eSJin Yao "SampleAfterValue": "100003", 11512c72404eSJin Yao "UMask": "0x1" 11522c72404eSJin Yao }, 11532c72404eSJin Yao { 11542c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 11552c72404eSJin Yao "Counter": "0,1,2,3", 11562c72404eSJin Yao "CounterHTOff": "0,1,2,3", 11572c72404eSJin Yao "EventCode": "0xB7, 0xBB", 11582c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 11592c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1160*3bad20d7SIan Rogers "MSRValue": "0x83FC00100", 1161b5ff7f27SJin Yao "Offcore": "1", 1162b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1163630171d4SAndi Kleen "SampleAfterValue": "100003", 1164b5ff7f27SJin Yao "UMask": "0x1" 1165630171d4SAndi Kleen }, 1166630171d4SAndi Kleen { 1167b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", 1168630171d4SAndi Kleen "Counter": "0,1,2,3", 1169b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1170b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1171b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1172630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1173*3bad20d7SIan Rogers "MSRValue": "0x63FC00100", 1174b5ff7f27SJin Yao "Offcore": "1", 1175b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1176630171d4SAndi Kleen "SampleAfterValue": "100003", 1177b5ff7f27SJin Yao "UMask": "0x1" 1178630171d4SAndi Kleen }, 1179630171d4SAndi Kleen { 11802c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", 1181630171d4SAndi Kleen "Counter": "0,1,2,3", 11822c72404eSJin Yao "CounterHTOff": "0,1,2,3", 11832c72404eSJin Yao "EventCode": "0xB7, 0xBB", 11842c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 11852c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1186*3bad20d7SIan Rogers "MSRValue": "0x604000100", 11872c72404eSJin Yao "Offcore": "1", 11882c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 11892c72404eSJin Yao "SampleAfterValue": "100003", 11902c72404eSJin Yao "UMask": "0x1" 1191630171d4SAndi Kleen }, 1192630171d4SAndi Kleen { 11932c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", 11942c72404eSJin Yao "Counter": "0,1,2,3", 11952c72404eSJin Yao "CounterHTOff": "0,1,2,3", 11962c72404eSJin Yao "EventCode": "0xB7, 0xBB", 11972c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 11982c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1199*3bad20d7SIan Rogers "MSRValue": "0x63B800100", 12002c72404eSJin Yao "Offcore": "1", 12012c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 12022c72404eSJin Yao "SampleAfterValue": "100003", 12032c72404eSJin Yao "UMask": "0x1" 12042c72404eSJin Yao }, 12052c72404eSJin Yao { 12062c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 1207630171d4SAndi Kleen "Counter": "0,1,2,3", 1208b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12092c72404eSJin Yao "EventCode": "0xC9", 12102c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED", 12112c72404eSJin Yao "PEBS": "1", 12122c72404eSJin Yao "PublicDescription": "Number of times RTM abort was triggered.", 12132c72404eSJin Yao "SampleAfterValue": "2000003", 12142c72404eSJin Yao "UMask": "0x4" 12152c72404eSJin Yao }, 12162c72404eSJin Yao { 12172c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 12182c72404eSJin Yao "Counter": "0,1,2,3", 12192c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12202c72404eSJin Yao "EventCode": "0xC9", 12212c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_EVENTS", 12222c72404eSJin Yao "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 1223b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1224b5ff7f27SJin Yao "UMask": "0x80" 1225630171d4SAndi Kleen }, 1226630171d4SAndi Kleen { 12272c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 1228630171d4SAndi Kleen "Counter": "0,1,2,3", 12292c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12302c72404eSJin Yao "EventCode": "0xC9", 12312c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_MEM", 12322c72404eSJin Yao "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 12332c72404eSJin Yao "SampleAfterValue": "2000003", 12342c72404eSJin Yao "UMask": "0x8" 12352c72404eSJin Yao }, 12362c72404eSJin Yao { 12372c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 12382c72404eSJin Yao "Counter": "0,1,2,3", 12392c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12402c72404eSJin Yao "EventCode": "0xC9", 12412c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 12422c72404eSJin Yao "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 12432c72404eSJin Yao "SampleAfterValue": "2000003", 12442c72404eSJin Yao "UMask": "0x40" 12452c72404eSJin Yao }, 12462c72404eSJin Yao { 12472c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 12482c72404eSJin Yao "Counter": "0,1,2,3", 12492c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12502c72404eSJin Yao "EventCode": "0xC9", 12512c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_TIMER", 12522c72404eSJin Yao "SampleAfterValue": "2000003", 12532c72404eSJin Yao "UMask": "0x10" 12542c72404eSJin Yao }, 12552c72404eSJin Yao { 12562c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 12572c72404eSJin Yao "Counter": "0,1,2,3", 12582c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12592c72404eSJin Yao "EventCode": "0xC9", 12602c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 12612c72404eSJin Yao "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 12622c72404eSJin Yao "SampleAfterValue": "2000003", 12632c72404eSJin Yao "UMask": "0x20" 12642c72404eSJin Yao }, 12652c72404eSJin Yao { 12662c72404eSJin Yao "BriefDescription": "Number of times an RTM execution successfully committed", 12672c72404eSJin Yao "Counter": "0,1,2,3", 12682c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12692c72404eSJin Yao "EventCode": "0xC9", 12702c72404eSJin Yao "EventName": "RTM_RETIRED.COMMIT", 12712c72404eSJin Yao "PublicDescription": "Number of times RTM commit succeeded.", 12722c72404eSJin Yao "SampleAfterValue": "2000003", 12732c72404eSJin Yao "UMask": "0x2" 12742c72404eSJin Yao }, 12752c72404eSJin Yao { 12762c72404eSJin Yao "BriefDescription": "Number of times an RTM execution started.", 12772c72404eSJin Yao "Counter": "0,1,2,3", 12782c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12792c72404eSJin Yao "EventCode": "0xC9", 12802c72404eSJin Yao "EventName": "RTM_RETIRED.START", 12812c72404eSJin Yao "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 12822c72404eSJin Yao "SampleAfterValue": "2000003", 1283b5ff7f27SJin Yao "UMask": "0x1" 1284b5ff7f27SJin Yao }, 1285b5ff7f27SJin Yao { 12862c72404eSJin Yao "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 1287b5ff7f27SJin Yao "Counter": "0,1,2,3", 12882c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12892c72404eSJin Yao "EventCode": "0x5d", 12902c72404eSJin Yao "EventName": "TX_EXEC.MISC1", 12912c72404eSJin Yao "SampleAfterValue": "2000003", 1292b5ff7f27SJin Yao "UMask": "0x1" 1293b5ff7f27SJin Yao }, 1294b5ff7f27SJin Yao { 12952c72404eSJin Yao "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 1296b5ff7f27SJin Yao "Counter": "0,1,2,3", 12972c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 12982c72404eSJin Yao "EventCode": "0x5d", 12992c72404eSJin Yao "EventName": "TX_EXEC.MISC2", 13002c72404eSJin Yao "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 13012c72404eSJin Yao "SampleAfterValue": "2000003", 13022c72404eSJin Yao "UMask": "0x2" 13032c72404eSJin Yao }, 13042c72404eSJin Yao { 13052c72404eSJin Yao "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 13062c72404eSJin Yao "Counter": "0,1,2,3", 13072c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13082c72404eSJin Yao "EventCode": "0x5d", 13092c72404eSJin Yao "EventName": "TX_EXEC.MISC3", 13102c72404eSJin Yao "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 13112c72404eSJin Yao "SampleAfterValue": "2000003", 13122c72404eSJin Yao "UMask": "0x4" 13132c72404eSJin Yao }, 13142c72404eSJin Yao { 13152c72404eSJin Yao "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 13162c72404eSJin Yao "Counter": "0,1,2,3", 13172c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13182c72404eSJin Yao "EventCode": "0x5d", 13192c72404eSJin Yao "EventName": "TX_EXEC.MISC4", 13202c72404eSJin Yao "PublicDescription": "RTM region detected inside HLE.", 13212c72404eSJin Yao "SampleAfterValue": "2000003", 13222c72404eSJin Yao "UMask": "0x8" 13232c72404eSJin Yao }, 13242c72404eSJin Yao { 13252c72404eSJin Yao "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 13262c72404eSJin Yao "Counter": "0,1,2,3", 13272c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13282c72404eSJin Yao "EventCode": "0x5d", 13292c72404eSJin Yao "EventName": "TX_EXEC.MISC5", 13302c72404eSJin Yao "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 13312c72404eSJin Yao "SampleAfterValue": "2000003", 13322c72404eSJin Yao "UMask": "0x10" 13332c72404eSJin Yao }, 13342c72404eSJin Yao { 13352c72404eSJin Yao "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 13362c72404eSJin Yao "Counter": "0,1,2,3", 13372c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13382c72404eSJin Yao "EventCode": "0x54", 13392c72404eSJin Yao "EventName": "TX_MEM.ABORT_CAPACITY", 13402c72404eSJin Yao "SampleAfterValue": "2000003", 13412c72404eSJin Yao "UMask": "0x2" 13422c72404eSJin Yao }, 13432c72404eSJin Yao { 13442c72404eSJin Yao "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 13452c72404eSJin Yao "Counter": "0,1,2,3", 13462c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13472c72404eSJin Yao "EventCode": "0x54", 13482c72404eSJin Yao "EventName": "TX_MEM.ABORT_CONFLICT", 13492c72404eSJin Yao "PublicDescription": "Number of times a TSX line had a cache conflict.", 13502c72404eSJin Yao "SampleAfterValue": "2000003", 1351b5ff7f27SJin Yao "UMask": "0x1" 1352b5ff7f27SJin Yao }, 1353b5ff7f27SJin Yao { 13542c72404eSJin Yao "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 1355b5ff7f27SJin Yao "Counter": "0,1,2,3", 13562c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13572c72404eSJin Yao "EventCode": "0x54", 13582c72404eSJin Yao "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 13592c72404eSJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 13602c72404eSJin Yao "SampleAfterValue": "2000003", 13612c72404eSJin Yao "UMask": "0x10" 13622c72404eSJin Yao }, 13632c72404eSJin Yao { 13642c72404eSJin Yao "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 13652c72404eSJin Yao "Counter": "0,1,2,3", 13662c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13672c72404eSJin Yao "EventCode": "0x54", 13682c72404eSJin Yao "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 13692c72404eSJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 13702c72404eSJin Yao "SampleAfterValue": "2000003", 13712c72404eSJin Yao "UMask": "0x8" 13722c72404eSJin Yao }, 13732c72404eSJin Yao { 13742c72404eSJin Yao "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 13752c72404eSJin Yao "Counter": "0,1,2,3", 13762c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13772c72404eSJin Yao "EventCode": "0x54", 13782c72404eSJin Yao "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 13792c72404eSJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 13802c72404eSJin Yao "SampleAfterValue": "2000003", 13812c72404eSJin Yao "UMask": "0x20" 13822c72404eSJin Yao }, 13832c72404eSJin Yao { 13842c72404eSJin Yao "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 13852c72404eSJin Yao "Counter": "0,1,2,3", 13862c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13872c72404eSJin Yao "EventCode": "0x54", 13882c72404eSJin Yao "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 13892c72404eSJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 13902c72404eSJin Yao "SampleAfterValue": "2000003", 13912c72404eSJin Yao "UMask": "0x4" 13922c72404eSJin Yao }, 13932c72404eSJin Yao { 13942c72404eSJin Yao "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 13952c72404eSJin Yao "Counter": "0,1,2,3", 13962c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 13972c72404eSJin Yao "EventCode": "0x54", 13982c72404eSJin Yao "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 13992c72404eSJin Yao "PublicDescription": "Number of times we could not allocate Lock Buffer.", 14002c72404eSJin Yao "SampleAfterValue": "2000003", 14012c72404eSJin Yao "UMask": "0x40" 1402630171d4SAndi Kleen } 1403630171d4SAndi Kleen]