1630171d4SAndi Kleen[ 2630171d4SAndi Kleen { 3*2c72404eSJin Yao "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4630171d4SAndi Kleen "Counter": "0,1,2,3", 5*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 6*2c72404eSJin Yao "CounterMask": "2", 7*2c72404eSJin Yao "EventCode": "0xA3", 8*2c72404eSJin Yao "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 9*2c72404eSJin Yao "SampleAfterValue": "2000003", 10*2c72404eSJin Yao "UMask": "0x2" 11*2c72404eSJin Yao }, 12*2c72404eSJin Yao { 13*2c72404eSJin Yao "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 14*2c72404eSJin Yao "Counter": "0,1,2,3", 15*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 16*2c72404eSJin Yao "CounterMask": "6", 17*2c72404eSJin Yao "EventCode": "0xA3", 18*2c72404eSJin Yao "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 19*2c72404eSJin Yao "SampleAfterValue": "2000003", 20*2c72404eSJin Yao "UMask": "0x6" 21*2c72404eSJin Yao }, 22*2c72404eSJin Yao { 23*2c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 24*2c72404eSJin Yao "Counter": "0,1,2,3", 25*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 26*2c72404eSJin Yao "EventCode": "0xC8", 27*2c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED", 28*2c72404eSJin Yao "PEBS": "1", 29*2c72404eSJin Yao "PublicDescription": "Number of times HLE abort was triggered.", 30*2c72404eSJin Yao "SampleAfterValue": "2000003", 31*2c72404eSJin Yao "UMask": "0x4" 32*2c72404eSJin Yao }, 33*2c72404eSJin Yao { 34*2c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 35*2c72404eSJin Yao "Counter": "0,1,2,3", 36*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 37*2c72404eSJin Yao "EventCode": "0xC8", 38*2c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_EVENTS", 39*2c72404eSJin Yao "SampleAfterValue": "2000003", 40*2c72404eSJin Yao "UMask": "0x80" 41*2c72404eSJin Yao }, 42*2c72404eSJin Yao { 43*2c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 44*2c72404eSJin Yao "Counter": "0,1,2,3", 45*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 46*2c72404eSJin Yao "EventCode": "0xC8", 47*2c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_MEM", 48*2c72404eSJin Yao "SampleAfterValue": "2000003", 49*2c72404eSJin Yao "UMask": "0x8" 50*2c72404eSJin Yao }, 51*2c72404eSJin Yao { 52*2c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 53*2c72404eSJin Yao "Counter": "0,1,2,3", 54*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 55*2c72404eSJin Yao "EventCode": "0xC8", 56*2c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 57*2c72404eSJin Yao "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 58*2c72404eSJin Yao "SampleAfterValue": "2000003", 59*2c72404eSJin Yao "UMask": "0x40" 60*2c72404eSJin Yao }, 61*2c72404eSJin Yao { 62*2c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 63*2c72404eSJin Yao "Counter": "0,1,2,3", 64*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 65*2c72404eSJin Yao "EventCode": "0xC8", 66*2c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_TIMER", 67*2c72404eSJin Yao "SampleAfterValue": "2000003", 68*2c72404eSJin Yao "UMask": "0x10" 69*2c72404eSJin Yao }, 70*2c72404eSJin Yao { 71*2c72404eSJin Yao "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 72*2c72404eSJin Yao "Counter": "0,1,2,3", 73*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 74*2c72404eSJin Yao "EventCode": "0xC8", 75*2c72404eSJin Yao "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 76*2c72404eSJin Yao "SampleAfterValue": "2000003", 77*2c72404eSJin Yao "UMask": "0x20" 78*2c72404eSJin Yao }, 79*2c72404eSJin Yao { 80*2c72404eSJin Yao "BriefDescription": "Number of times an HLE execution successfully committed", 81*2c72404eSJin Yao "Counter": "0,1,2,3", 82*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 83*2c72404eSJin Yao "EventCode": "0xC8", 84*2c72404eSJin Yao "EventName": "HLE_RETIRED.COMMIT", 85*2c72404eSJin Yao "PublicDescription": "Number of times HLE commit succeeded.", 86*2c72404eSJin Yao "SampleAfterValue": "2000003", 87*2c72404eSJin Yao "UMask": "0x2" 88*2c72404eSJin Yao }, 89*2c72404eSJin Yao { 90*2c72404eSJin Yao "BriefDescription": "Number of times an HLE execution started.", 91*2c72404eSJin Yao "Counter": "0,1,2,3", 92*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 93*2c72404eSJin Yao "EventCode": "0xC8", 94*2c72404eSJin Yao "EventName": "HLE_RETIRED.START", 95*2c72404eSJin Yao "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 96*2c72404eSJin Yao "SampleAfterValue": "2000003", 97b5ff7f27SJin Yao "UMask": "0x1" 98630171d4SAndi Kleen }, 99630171d4SAndi Kleen { 100*2c72404eSJin Yao "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 101*2c72404eSJin Yao "Counter": "0,1,2,3", 102*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 103*2c72404eSJin Yao "Errata": "SKL089", 104*2c72404eSJin Yao "EventCode": "0xC3", 105*2c72404eSJin Yao "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 106*2c72404eSJin Yao "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 107*2c72404eSJin Yao "SampleAfterValue": "100003", 108*2c72404eSJin Yao "UMask": "0x2" 109*2c72404eSJin Yao }, 110*2c72404eSJin Yao { 111*2c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 112630171d4SAndi Kleen "Counter": "0,1,2,3", 113b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 114*2c72404eSJin Yao "Data_LA": "1", 115*2c72404eSJin Yao "EventCode": "0xcd", 116*2c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 117*2c72404eSJin Yao "MSRIndex": "0x3F6", 118*2c72404eSJin Yao "MSRValue": "0x80", 119*2c72404eSJin Yao "PEBS": "2", 120*2c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 121*2c72404eSJin Yao "SampleAfterValue": "1009", 122*2c72404eSJin Yao "TakenAlone": "1", 123b5ff7f27SJin Yao "UMask": "0x1" 124630171d4SAndi Kleen }, 125630171d4SAndi Kleen { 126*2c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 127*2c72404eSJin Yao "Counter": "0,1,2,3", 128*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 129*2c72404eSJin Yao "Data_LA": "1", 130*2c72404eSJin Yao "EventCode": "0xcd", 131*2c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 132*2c72404eSJin Yao "MSRIndex": "0x3F6", 133*2c72404eSJin Yao "MSRValue": "0x10", 134*2c72404eSJin Yao "PEBS": "2", 135*2c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 136*2c72404eSJin Yao "SampleAfterValue": "20011", 137*2c72404eSJin Yao "TakenAlone": "1", 138*2c72404eSJin Yao "UMask": "0x1" 139*2c72404eSJin Yao }, 140*2c72404eSJin Yao { 141*2c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 142*2c72404eSJin Yao "Counter": "0,1,2,3", 143*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 144*2c72404eSJin Yao "Data_LA": "1", 145*2c72404eSJin Yao "EventCode": "0xcd", 146*2c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 147*2c72404eSJin Yao "MSRIndex": "0x3F6", 148*2c72404eSJin Yao "MSRValue": "0x100", 149*2c72404eSJin Yao "PEBS": "2", 150*2c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 151*2c72404eSJin Yao "SampleAfterValue": "503", 152*2c72404eSJin Yao "TakenAlone": "1", 153*2c72404eSJin Yao "UMask": "0x1" 154*2c72404eSJin Yao }, 155*2c72404eSJin Yao { 156*2c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 157*2c72404eSJin Yao "Counter": "0,1,2,3", 158*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 159*2c72404eSJin Yao "Data_LA": "1", 160*2c72404eSJin Yao "EventCode": "0xcd", 161*2c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 162*2c72404eSJin Yao "MSRIndex": "0x3F6", 163*2c72404eSJin Yao "MSRValue": "0x20", 164*2c72404eSJin Yao "PEBS": "2", 165*2c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 166*2c72404eSJin Yao "SampleAfterValue": "100007", 167*2c72404eSJin Yao "TakenAlone": "1", 168*2c72404eSJin Yao "UMask": "0x1" 169*2c72404eSJin Yao }, 170*2c72404eSJin Yao { 171*2c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 172*2c72404eSJin Yao "Counter": "0,1,2,3", 173*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 174*2c72404eSJin Yao "Data_LA": "1", 175*2c72404eSJin Yao "EventCode": "0xcd", 176*2c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 177*2c72404eSJin Yao "MSRIndex": "0x3F6", 178*2c72404eSJin Yao "MSRValue": "0x4", 179*2c72404eSJin Yao "PEBS": "2", 180*2c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 181*2c72404eSJin Yao "SampleAfterValue": "100003", 182*2c72404eSJin Yao "TakenAlone": "1", 183*2c72404eSJin Yao "UMask": "0x1" 184*2c72404eSJin Yao }, 185*2c72404eSJin Yao { 186*2c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 187*2c72404eSJin Yao "Counter": "0,1,2,3", 188*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 189*2c72404eSJin Yao "Data_LA": "1", 190*2c72404eSJin Yao "EventCode": "0xcd", 191*2c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 192*2c72404eSJin Yao "MSRIndex": "0x3F6", 193*2c72404eSJin Yao "MSRValue": "0x200", 194*2c72404eSJin Yao "PEBS": "2", 195*2c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 196*2c72404eSJin Yao "SampleAfterValue": "101", 197*2c72404eSJin Yao "TakenAlone": "1", 198*2c72404eSJin Yao "UMask": "0x1" 199*2c72404eSJin Yao }, 200*2c72404eSJin Yao { 201*2c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 202*2c72404eSJin Yao "Counter": "0,1,2,3", 203*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 204*2c72404eSJin Yao "Data_LA": "1", 205*2c72404eSJin Yao "EventCode": "0xcd", 206*2c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 207*2c72404eSJin Yao "MSRIndex": "0x3F6", 208*2c72404eSJin Yao "MSRValue": "0x40", 209*2c72404eSJin Yao "PEBS": "2", 210*2c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 211*2c72404eSJin Yao "SampleAfterValue": "2003", 212*2c72404eSJin Yao "TakenAlone": "1", 213*2c72404eSJin Yao "UMask": "0x1" 214*2c72404eSJin Yao }, 215*2c72404eSJin Yao { 216*2c72404eSJin Yao "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 217*2c72404eSJin Yao "Counter": "0,1,2,3", 218*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 219*2c72404eSJin Yao "Data_LA": "1", 220*2c72404eSJin Yao "EventCode": "0xcd", 221*2c72404eSJin Yao "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 222*2c72404eSJin Yao "MSRIndex": "0x3F6", 223*2c72404eSJin Yao "MSRValue": "0x8", 224*2c72404eSJin Yao "PEBS": "2", 225*2c72404eSJin Yao "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 226*2c72404eSJin Yao "SampleAfterValue": "50021", 227*2c72404eSJin Yao "TakenAlone": "1", 228*2c72404eSJin Yao "UMask": "0x1" 229*2c72404eSJin Yao }, 230*2c72404eSJin Yao { 231*2c72404eSJin Yao "BriefDescription": "Demand Data Read requests who miss L3 cache", 232*2c72404eSJin Yao "Counter": "0,1,2,3", 233*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 234*2c72404eSJin Yao "EventCode": "0xB0", 235*2c72404eSJin Yao "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 236*2c72404eSJin Yao "PublicDescription": "Demand Data Read requests who miss L3 cache.", 237*2c72404eSJin Yao "SampleAfterValue": "100003", 238*2c72404eSJin Yao "UMask": "0x10" 239*2c72404eSJin Yao }, 240*2c72404eSJin Yao { 241*2c72404eSJin Yao "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 242*2c72404eSJin Yao "Counter": "0,1,2,3", 243*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 244*2c72404eSJin Yao "CounterMask": "1", 245*2c72404eSJin Yao "EventCode": "0x60", 246*2c72404eSJin Yao "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 247*2c72404eSJin Yao "SampleAfterValue": "2000003", 248*2c72404eSJin Yao "UMask": "0x10" 249*2c72404eSJin Yao }, 250*2c72404eSJin Yao { 251*2c72404eSJin Yao "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 252*2c72404eSJin Yao "Counter": "0,1,2,3", 253*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 254*2c72404eSJin Yao "EventCode": "0x60", 255*2c72404eSJin Yao "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 256*2c72404eSJin Yao "SampleAfterValue": "2000003", 257*2c72404eSJin Yao "UMask": "0x10" 258*2c72404eSJin Yao }, 259*2c72404eSJin Yao { 26019f2d40cSAndi Kleen "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 261630171d4SAndi Kleen "Counter": "0,1,2,3", 262b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 26319f2d40cSAndi Kleen "CounterMask": "6", 264630171d4SAndi Kleen "EventCode": "0x60", 265b5ff7f27SJin Yao "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 266630171d4SAndi Kleen "SampleAfterValue": "2000003", 267b5ff7f27SJin Yao "UMask": "0x10" 268630171d4SAndi Kleen }, 269630171d4SAndi Kleen { 270*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 271630171d4SAndi Kleen "Counter": "0,1,2,3", 272b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 273b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 274*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 275b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 276*2c72404eSJin Yao "MSRValue": "0x3FBC000491", 277b5ff7f27SJin Yao "Offcore": "1", 278b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 279630171d4SAndi Kleen "SampleAfterValue": "100003", 280b5ff7f27SJin Yao "UMask": "0x1" 281630171d4SAndi Kleen }, 282630171d4SAndi Kleen { 283*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 284630171d4SAndi Kleen "Counter": "0,1,2,3", 285b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 286b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 287*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 288b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 289*2c72404eSJin Yao "MSRValue": "0x103FC00491", 290b5ff7f27SJin Yao "Offcore": "1", 291b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 292630171d4SAndi Kleen "SampleAfterValue": "100003", 293b5ff7f27SJin Yao "UMask": "0x1" 294630171d4SAndi Kleen }, 295630171d4SAndi Kleen { 296*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 297630171d4SAndi Kleen "Counter": "0,1,2,3", 298b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 299b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 300*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 301b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 302*2c72404eSJin Yao "MSRValue": "0x083FC00491", 303b5ff7f27SJin Yao "Offcore": "1", 304b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 305b5ff7f27SJin Yao "SampleAfterValue": "100003", 306b5ff7f27SJin Yao "UMask": "0x1" 307630171d4SAndi Kleen }, 308630171d4SAndi Kleen { 309*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 310630171d4SAndi Kleen "Counter": "0,1,2,3", 311b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 312b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 313*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 314b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 315*2c72404eSJin Yao "MSRValue": "0x063FC00491", 316b5ff7f27SJin Yao "Offcore": "1", 317b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 318b5ff7f27SJin Yao "SampleAfterValue": "100003", 319b5ff7f27SJin Yao "UMask": "0x1" 320630171d4SAndi Kleen }, 321630171d4SAndi Kleen { 322*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", 323630171d4SAndi Kleen "Counter": "0,1,2,3", 324b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 325b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 326*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 327b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 328*2c72404eSJin Yao "MSRValue": "0x0604000491", 329b5ff7f27SJin Yao "Offcore": "1", 330b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 331b5ff7f27SJin Yao "SampleAfterValue": "100003", 332b5ff7f27SJin Yao "UMask": "0x1" 333630171d4SAndi Kleen }, 334630171d4SAndi Kleen { 335*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", 336b5ff7f27SJin Yao "Counter": "0,1,2,3", 337b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 338b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 339*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 340b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 341*2c72404eSJin Yao "MSRValue": "0x063B800491", 342b5ff7f27SJin Yao "Offcore": "1", 343b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 344b5ff7f27SJin Yao "SampleAfterValue": "100003", 345b5ff7f27SJin Yao "UMask": "0x1" 346b5ff7f27SJin Yao }, 347b5ff7f27SJin Yao { 348b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss in the L3.", 349b5ff7f27SJin Yao "Counter": "0,1,2,3", 350b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 351b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 352b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 353b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 354b5ff7f27SJin Yao "MSRValue": "0x3FBC000490", 355b5ff7f27SJin Yao "Offcore": "1", 356b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 357b5ff7f27SJin Yao "SampleAfterValue": "100003", 358b5ff7f27SJin Yao "UMask": "0x1" 359b5ff7f27SJin Yao }, 360b5ff7f27SJin Yao { 361*2c72404eSJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 362b5ff7f27SJin Yao "Counter": "0,1,2,3", 363b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 364b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 365*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 366b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 367*2c72404eSJin Yao "MSRValue": "0x103FC00490", 368*2c72404eSJin Yao "Offcore": "1", 369*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 370*2c72404eSJin Yao "SampleAfterValue": "100003", 371*2c72404eSJin Yao "UMask": "0x1" 372*2c72404eSJin Yao }, 373*2c72404eSJin Yao { 374*2c72404eSJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 375*2c72404eSJin Yao "Counter": "0,1,2,3", 376*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 377*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 378*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 379*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 380*2c72404eSJin Yao "MSRValue": "0x083FC00490", 381*2c72404eSJin Yao "Offcore": "1", 382*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 383*2c72404eSJin Yao "SampleAfterValue": "100003", 384*2c72404eSJin Yao "UMask": "0x1" 385*2c72404eSJin Yao }, 386*2c72404eSJin Yao { 387*2c72404eSJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 388*2c72404eSJin Yao "Counter": "0,1,2,3", 389*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 390*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 391*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 392*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 393*2c72404eSJin Yao "MSRValue": "0x063FC00490", 394b5ff7f27SJin Yao "Offcore": "1", 395b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 396b5ff7f27SJin Yao "SampleAfterValue": "100003", 397b5ff7f27SJin Yao "UMask": "0x1" 398b5ff7f27SJin Yao }, 399b5ff7f27SJin Yao { 400b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", 401b5ff7f27SJin Yao "Counter": "0,1,2,3", 402b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 403b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 404b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 405b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 406b5ff7f27SJin Yao "MSRValue": "0x0604000490", 407b5ff7f27SJin Yao "Offcore": "1", 408b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 409b5ff7f27SJin Yao "SampleAfterValue": "100003", 410b5ff7f27SJin Yao "UMask": "0x1" 411b5ff7f27SJin Yao }, 412b5ff7f27SJin Yao { 413*2c72404eSJin Yao "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", 414b5ff7f27SJin Yao "Counter": "0,1,2,3", 415b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 416b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 417*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 418b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 419*2c72404eSJin Yao "MSRValue": "0x063B800490", 420*2c72404eSJin Yao "Offcore": "1", 421*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 422*2c72404eSJin Yao "SampleAfterValue": "100003", 423*2c72404eSJin Yao "UMask": "0x1" 424*2c72404eSJin Yao }, 425*2c72404eSJin Yao { 426*2c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss in the L3.", 427*2c72404eSJin Yao "Counter": "0,1,2,3", 428*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 429*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 430*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 431*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 432*2c72404eSJin Yao "MSRValue": "0x3FBC000120", 433*2c72404eSJin Yao "Offcore": "1", 434*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 435*2c72404eSJin Yao "SampleAfterValue": "100003", 436*2c72404eSJin Yao "UMask": "0x1" 437*2c72404eSJin Yao }, 438*2c72404eSJin Yao { 439*2c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 440*2c72404eSJin Yao "Counter": "0,1,2,3", 441*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 442*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 443*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 444*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 445*2c72404eSJin Yao "MSRValue": "0x103FC00120", 446*2c72404eSJin Yao "Offcore": "1", 447*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 448*2c72404eSJin Yao "SampleAfterValue": "100003", 449*2c72404eSJin Yao "UMask": "0x1" 450*2c72404eSJin Yao }, 451*2c72404eSJin Yao { 452*2c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 453*2c72404eSJin Yao "Counter": "0,1,2,3", 454*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 455*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 456*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 457*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 458*2c72404eSJin Yao "MSRValue": "0x083FC00120", 459*2c72404eSJin Yao "Offcore": "1", 460*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 461*2c72404eSJin Yao "SampleAfterValue": "100003", 462*2c72404eSJin Yao "UMask": "0x1" 463*2c72404eSJin Yao }, 464*2c72404eSJin Yao { 465*2c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 466*2c72404eSJin Yao "Counter": "0,1,2,3", 467*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 468*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 469*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 470*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 471*2c72404eSJin Yao "MSRValue": "0x063FC00120", 472*2c72404eSJin Yao "Offcore": "1", 473*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 474*2c72404eSJin Yao "SampleAfterValue": "100003", 475*2c72404eSJin Yao "UMask": "0x1" 476*2c72404eSJin Yao }, 477*2c72404eSJin Yao { 478*2c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", 479*2c72404eSJin Yao "Counter": "0,1,2,3", 480*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 481*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 482*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 483*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 484*2c72404eSJin Yao "MSRValue": "0x0604000120", 485*2c72404eSJin Yao "Offcore": "1", 486*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 487*2c72404eSJin Yao "SampleAfterValue": "100003", 488*2c72404eSJin Yao "UMask": "0x1" 489*2c72404eSJin Yao }, 490*2c72404eSJin Yao { 491*2c72404eSJin Yao "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", 492*2c72404eSJin Yao "Counter": "0,1,2,3", 493*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 494*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 495*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 496*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 497*2c72404eSJin Yao "MSRValue": "0x063B800120", 498*2c72404eSJin Yao "Offcore": "1", 499*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 500*2c72404eSJin Yao "SampleAfterValue": "100003", 501*2c72404eSJin Yao "UMask": "0x1" 502*2c72404eSJin Yao }, 503*2c72404eSJin Yao { 504*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", 505*2c72404eSJin Yao "Counter": "0,1,2,3", 506*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 507*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 508*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", 509*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 510*2c72404eSJin Yao "MSRValue": "0x3FBC000122", 511*2c72404eSJin Yao "Offcore": "1", 512*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 513*2c72404eSJin Yao "SampleAfterValue": "100003", 514*2c72404eSJin Yao "UMask": "0x1" 515*2c72404eSJin Yao }, 516*2c72404eSJin Yao { 517*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 518*2c72404eSJin Yao "Counter": "0,1,2,3", 519*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 520*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 521*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", 522*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 523*2c72404eSJin Yao "MSRValue": "0x103FC00122", 524*2c72404eSJin Yao "Offcore": "1", 525*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 526*2c72404eSJin Yao "SampleAfterValue": "100003", 527*2c72404eSJin Yao "UMask": "0x1" 528*2c72404eSJin Yao }, 529*2c72404eSJin Yao { 530*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 531*2c72404eSJin Yao "Counter": "0,1,2,3", 532*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 533*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 534*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 535*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 536*2c72404eSJin Yao "MSRValue": "0x083FC00122", 537*2c72404eSJin Yao "Offcore": "1", 538*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 539*2c72404eSJin Yao "SampleAfterValue": "100003", 540*2c72404eSJin Yao "UMask": "0x1" 541*2c72404eSJin Yao }, 542*2c72404eSJin Yao { 543*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 544*2c72404eSJin Yao "Counter": "0,1,2,3", 545*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 546*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 547*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 548*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 549*2c72404eSJin Yao "MSRValue": "0x063FC00122", 550*2c72404eSJin Yao "Offcore": "1", 551*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 552*2c72404eSJin Yao "SampleAfterValue": "100003", 553*2c72404eSJin Yao "UMask": "0x1" 554*2c72404eSJin Yao }, 555*2c72404eSJin Yao { 556*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", 557*2c72404eSJin Yao "Counter": "0,1,2,3", 558*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 559*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 560*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 561*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 562*2c72404eSJin Yao "MSRValue": "0x0604000122", 563*2c72404eSJin Yao "Offcore": "1", 564*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 565*2c72404eSJin Yao "SampleAfterValue": "100003", 566*2c72404eSJin Yao "UMask": "0x1" 567*2c72404eSJin Yao }, 568*2c72404eSJin Yao { 569*2c72404eSJin Yao "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", 570*2c72404eSJin Yao "Counter": "0,1,2,3", 571*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 572*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 573*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 574*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 575*2c72404eSJin Yao "MSRValue": "0x063B800122", 576*2c72404eSJin Yao "Offcore": "1", 577*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 578*2c72404eSJin Yao "SampleAfterValue": "100003", 579*2c72404eSJin Yao "UMask": "0x1" 580*2c72404eSJin Yao }, 581*2c72404eSJin Yao { 582*2c72404eSJin Yao "BriefDescription": "Counts all demand code reads that miss in the L3.", 583*2c72404eSJin Yao "Counter": "0,1,2,3", 584*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 585*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 586*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 587*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 588*2c72404eSJin Yao "MSRValue": "0x3FBC000004", 589*2c72404eSJin Yao "Offcore": "1", 590*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 591*2c72404eSJin Yao "SampleAfterValue": "100003", 592*2c72404eSJin Yao "UMask": "0x1" 593*2c72404eSJin Yao }, 594*2c72404eSJin Yao { 595*2c72404eSJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", 596*2c72404eSJin Yao "Counter": "0,1,2,3", 597*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 598*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 599*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 600*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 601*2c72404eSJin Yao "MSRValue": "0x103FC00004", 602b5ff7f27SJin Yao "Offcore": "1", 603b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 604b5ff7f27SJin Yao "SampleAfterValue": "100003", 605b5ff7f27SJin Yao "UMask": "0x1" 606b5ff7f27SJin Yao }, 607b5ff7f27SJin Yao { 608b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", 609b5ff7f27SJin Yao "Counter": "0,1,2,3", 610b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 611b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 612b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 613b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 614b5ff7f27SJin Yao "MSRValue": "0x083FC00004", 615b5ff7f27SJin Yao "Offcore": "1", 616b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 617b5ff7f27SJin Yao "SampleAfterValue": "100003", 618b5ff7f27SJin Yao "UMask": "0x1" 619b5ff7f27SJin Yao }, 620b5ff7f27SJin Yao { 621b5ff7f27SJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.", 622b5ff7f27SJin Yao "Counter": "0,1,2,3", 623b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 624b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 625b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 626b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 627b5ff7f27SJin Yao "MSRValue": "0x063FC00004", 628b5ff7f27SJin Yao "Offcore": "1", 629b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 630b5ff7f27SJin Yao "SampleAfterValue": "100003", 631b5ff7f27SJin Yao "UMask": "0x1" 632b5ff7f27SJin Yao }, 633b5ff7f27SJin Yao { 634*2c72404eSJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.", 635b5ff7f27SJin Yao "Counter": "0,1,2,3", 636b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 637b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 638*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 639b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 640*2c72404eSJin Yao "MSRValue": "0x0604000004", 641b5ff7f27SJin Yao "Offcore": "1", 642b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 643b5ff7f27SJin Yao "SampleAfterValue": "100003", 644b5ff7f27SJin Yao "UMask": "0x1" 645b5ff7f27SJin Yao }, 646b5ff7f27SJin Yao { 647*2c72404eSJin Yao "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", 648b5ff7f27SJin Yao "Counter": "0,1,2,3", 649b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 650b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 651*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 652b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 653*2c72404eSJin Yao "MSRValue": "0x063B800004", 654b5ff7f27SJin Yao "Offcore": "1", 655b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 656b5ff7f27SJin Yao "SampleAfterValue": "100003", 657b5ff7f27SJin Yao "UMask": "0x1" 658b5ff7f27SJin Yao }, 659b5ff7f27SJin Yao { 660b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss in the L3.", 661b5ff7f27SJin Yao "Counter": "0,1,2,3", 662b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 663b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 664b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 665b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 666b5ff7f27SJin Yao "MSRValue": "0x3FBC000001", 667b5ff7f27SJin Yao "Offcore": "1", 668b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 669b5ff7f27SJin Yao "SampleAfterValue": "100003", 670b5ff7f27SJin Yao "UMask": "0x1" 671b5ff7f27SJin Yao }, 672b5ff7f27SJin Yao { 673*2c72404eSJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", 674b5ff7f27SJin Yao "Counter": "0,1,2,3", 675b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 676b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 677*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 678b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 679*2c72404eSJin Yao "MSRValue": "0x103FC00001", 680b5ff7f27SJin Yao "Offcore": "1", 681b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 682b5ff7f27SJin Yao "SampleAfterValue": "100003", 683b5ff7f27SJin Yao "UMask": "0x1" 684b5ff7f27SJin Yao }, 685b5ff7f27SJin Yao { 686b5ff7f27SJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", 687b5ff7f27SJin Yao "Counter": "0,1,2,3", 688b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 689b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 690b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 691b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 692b5ff7f27SJin Yao "MSRValue": "0x083FC00001", 693b5ff7f27SJin Yao "Offcore": "1", 694b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 695b5ff7f27SJin Yao "SampleAfterValue": "100003", 696b5ff7f27SJin Yao "UMask": "0x1" 697b5ff7f27SJin Yao }, 698b5ff7f27SJin Yao { 699*2c72404eSJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", 700*2c72404eSJin Yao "Counter": "0,1,2,3", 701*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 702*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 703*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 704*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 705*2c72404eSJin Yao "MSRValue": "0x063FC00001", 706*2c72404eSJin Yao "Offcore": "1", 707*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 708*2c72404eSJin Yao "SampleAfterValue": "100003", 709*2c72404eSJin Yao "UMask": "0x1" 710*2c72404eSJin Yao }, 711*2c72404eSJin Yao { 712*2c72404eSJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", 713*2c72404eSJin Yao "Counter": "0,1,2,3", 714*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 715*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 716*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 717*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 718*2c72404eSJin Yao "MSRValue": "0x0604000001", 719*2c72404eSJin Yao "Offcore": "1", 720*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 721*2c72404eSJin Yao "SampleAfterValue": "100003", 722*2c72404eSJin Yao "UMask": "0x1" 723*2c72404eSJin Yao }, 724*2c72404eSJin Yao { 725*2c72404eSJin Yao "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", 726*2c72404eSJin Yao "Counter": "0,1,2,3", 727*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 728*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 729*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 730*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 731*2c72404eSJin Yao "MSRValue": "0x063B800001", 732*2c72404eSJin Yao "Offcore": "1", 733*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 734*2c72404eSJin Yao "SampleAfterValue": "100003", 735*2c72404eSJin Yao "UMask": "0x1" 736*2c72404eSJin Yao }, 737*2c72404eSJin Yao { 738*2c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", 739*2c72404eSJin Yao "Counter": "0,1,2,3", 740*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 741*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 742*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 743*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 744*2c72404eSJin Yao "MSRValue": "0x3FBC000002", 745*2c72404eSJin Yao "Offcore": "1", 746*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 747*2c72404eSJin Yao "SampleAfterValue": "100003", 748*2c72404eSJin Yao "UMask": "0x1" 749*2c72404eSJin Yao }, 750*2c72404eSJin Yao { 751*2c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", 752*2c72404eSJin Yao "Counter": "0,1,2,3", 753*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 754*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 755*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", 756*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 757*2c72404eSJin Yao "MSRValue": "0x103FC00002", 758*2c72404eSJin Yao "Offcore": "1", 759*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 760*2c72404eSJin Yao "SampleAfterValue": "100003", 761*2c72404eSJin Yao "UMask": "0x1" 762*2c72404eSJin Yao }, 763*2c72404eSJin Yao { 764*2c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", 765*2c72404eSJin Yao "Counter": "0,1,2,3", 766*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 767*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 768*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 769*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 770*2c72404eSJin Yao "MSRValue": "0x083FC00002", 771*2c72404eSJin Yao "Offcore": "1", 772*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 773*2c72404eSJin Yao "SampleAfterValue": "100003", 774*2c72404eSJin Yao "UMask": "0x1" 775*2c72404eSJin Yao }, 776*2c72404eSJin Yao { 777*2c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", 778*2c72404eSJin Yao "Counter": "0,1,2,3", 779*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 780*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 781*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 782*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 783*2c72404eSJin Yao "MSRValue": "0x063FC00002", 784*2c72404eSJin Yao "Offcore": "1", 785*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 786*2c72404eSJin Yao "SampleAfterValue": "100003", 787*2c72404eSJin Yao "UMask": "0x1" 788*2c72404eSJin Yao }, 789*2c72404eSJin Yao { 790*2c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", 791*2c72404eSJin Yao "Counter": "0,1,2,3", 792*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 793*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 794*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 795*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 796*2c72404eSJin Yao "MSRValue": "0x0604000002", 797*2c72404eSJin Yao "Offcore": "1", 798*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 799*2c72404eSJin Yao "SampleAfterValue": "100003", 800*2c72404eSJin Yao "UMask": "0x1" 801*2c72404eSJin Yao }, 802*2c72404eSJin Yao { 803*2c72404eSJin Yao "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", 804*2c72404eSJin Yao "Counter": "0,1,2,3", 805*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 806*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 807*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 808*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 809*2c72404eSJin Yao "MSRValue": "0x063B800002", 810*2c72404eSJin Yao "Offcore": "1", 811*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 812*2c72404eSJin Yao "SampleAfterValue": "100003", 813*2c72404eSJin Yao "UMask": "0x1" 814*2c72404eSJin Yao }, 815*2c72404eSJin Yao { 816*2c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", 817*2c72404eSJin Yao "Counter": "0,1,2,3", 818*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 819*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 820*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 821*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 822*2c72404eSJin Yao "MSRValue": "0x3FBC000400", 823*2c72404eSJin Yao "Offcore": "1", 824*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 825*2c72404eSJin Yao "SampleAfterValue": "100003", 826*2c72404eSJin Yao "UMask": "0x1" 827*2c72404eSJin Yao }, 828*2c72404eSJin Yao { 829*2c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", 830*2c72404eSJin Yao "Counter": "0,1,2,3", 831*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 832*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 833*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 834*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 835*2c72404eSJin Yao "MSRValue": "0x103FC00400", 836*2c72404eSJin Yao "Offcore": "1", 837*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 838*2c72404eSJin Yao "SampleAfterValue": "100003", 839*2c72404eSJin Yao "UMask": "0x1" 840*2c72404eSJin Yao }, 841*2c72404eSJin Yao { 842*2c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", 843*2c72404eSJin Yao "Counter": "0,1,2,3", 844*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 845*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 846*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 847*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 848*2c72404eSJin Yao "MSRValue": "0x083FC00400", 849*2c72404eSJin Yao "Offcore": "1", 850*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 851*2c72404eSJin Yao "SampleAfterValue": "100003", 852*2c72404eSJin Yao "UMask": "0x1" 853*2c72404eSJin Yao }, 854*2c72404eSJin Yao { 855*2c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", 856*2c72404eSJin Yao "Counter": "0,1,2,3", 857*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 858*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 859*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", 860*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 861*2c72404eSJin Yao "MSRValue": "0x063FC00400", 862*2c72404eSJin Yao "Offcore": "1", 863*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 864*2c72404eSJin Yao "SampleAfterValue": "100003", 865*2c72404eSJin Yao "UMask": "0x1" 866*2c72404eSJin Yao }, 867*2c72404eSJin Yao { 868*2c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", 869*2c72404eSJin Yao "Counter": "0,1,2,3", 870*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 871*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 872*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 873*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 874*2c72404eSJin Yao "MSRValue": "0x0604000400", 875*2c72404eSJin Yao "Offcore": "1", 876*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 877*2c72404eSJin Yao "SampleAfterValue": "100003", 878*2c72404eSJin Yao "UMask": "0x1" 879*2c72404eSJin Yao }, 880*2c72404eSJin Yao { 881*2c72404eSJin Yao "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", 882*2c72404eSJin Yao "Counter": "0,1,2,3", 883*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 884*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 885*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 886*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 887*2c72404eSJin Yao "MSRValue": "0x063B800400", 888*2c72404eSJin Yao "Offcore": "1", 889*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 890*2c72404eSJin Yao "SampleAfterValue": "100003", 891*2c72404eSJin Yao "UMask": "0x1" 892*2c72404eSJin Yao }, 893*2c72404eSJin Yao { 894*2c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", 895*2c72404eSJin Yao "Counter": "0,1,2,3", 896*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 897*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 898*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 899*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 900*2c72404eSJin Yao "MSRValue": "0x3FBC000010", 901*2c72404eSJin Yao "Offcore": "1", 902*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 903*2c72404eSJin Yao "SampleAfterValue": "100003", 904*2c72404eSJin Yao "UMask": "0x1" 905*2c72404eSJin Yao }, 906*2c72404eSJin Yao { 907*2c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", 908*2c72404eSJin Yao "Counter": "0,1,2,3", 909*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 910*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 911*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 912*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 913*2c72404eSJin Yao "MSRValue": "0x103FC00010", 914*2c72404eSJin Yao "Offcore": "1", 915*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 916*2c72404eSJin Yao "SampleAfterValue": "100003", 917*2c72404eSJin Yao "UMask": "0x1" 918*2c72404eSJin Yao }, 919*2c72404eSJin Yao { 920*2c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 921*2c72404eSJin Yao "Counter": "0,1,2,3", 922*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 923*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 924*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 925*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 926*2c72404eSJin Yao "MSRValue": "0x083FC00010", 927*2c72404eSJin Yao "Offcore": "1", 928*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 929*2c72404eSJin Yao "SampleAfterValue": "100003", 930*2c72404eSJin Yao "UMask": "0x1" 931*2c72404eSJin Yao }, 932*2c72404eSJin Yao { 933*2c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", 934*2c72404eSJin Yao "Counter": "0,1,2,3", 935*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 936*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 937*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 938*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 939*2c72404eSJin Yao "MSRValue": "0x063FC00010", 940*2c72404eSJin Yao "Offcore": "1", 941*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 942*2c72404eSJin Yao "SampleAfterValue": "100003", 943*2c72404eSJin Yao "UMask": "0x1" 944*2c72404eSJin Yao }, 945*2c72404eSJin Yao { 946*2c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", 947*2c72404eSJin Yao "Counter": "0,1,2,3", 948*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 949*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 950*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 951*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 952*2c72404eSJin Yao "MSRValue": "0x0604000010", 953*2c72404eSJin Yao "Offcore": "1", 954*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 955*2c72404eSJin Yao "SampleAfterValue": "100003", 956*2c72404eSJin Yao "UMask": "0x1" 957*2c72404eSJin Yao }, 958*2c72404eSJin Yao { 959*2c72404eSJin Yao "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", 960*2c72404eSJin Yao "Counter": "0,1,2,3", 961*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 962*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 963*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 964*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 965*2c72404eSJin Yao "MSRValue": "0x063B800010", 966*2c72404eSJin Yao "Offcore": "1", 967*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 968*2c72404eSJin Yao "SampleAfterValue": "100003", 969*2c72404eSJin Yao "UMask": "0x1" 970*2c72404eSJin Yao }, 971*2c72404eSJin Yao { 972*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", 973*2c72404eSJin Yao "Counter": "0,1,2,3", 974*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 975*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 976*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", 977*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 978*2c72404eSJin Yao "MSRValue": "0x3FBC000020", 979*2c72404eSJin Yao "Offcore": "1", 980*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 981*2c72404eSJin Yao "SampleAfterValue": "100003", 982*2c72404eSJin Yao "UMask": "0x1" 983*2c72404eSJin Yao }, 984*2c72404eSJin Yao { 985*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", 986*2c72404eSJin Yao "Counter": "0,1,2,3", 987*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 988*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 989*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", 990*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 991*2c72404eSJin Yao "MSRValue": "0x103FC00020", 992*2c72404eSJin Yao "Offcore": "1", 993*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 994*2c72404eSJin Yao "SampleAfterValue": "100003", 995*2c72404eSJin Yao "UMask": "0x1" 996*2c72404eSJin Yao }, 997*2c72404eSJin Yao { 998*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 999*2c72404eSJin Yao "Counter": "0,1,2,3", 1000*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1001*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 1002*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 1003*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1004*2c72404eSJin Yao "MSRValue": "0x083FC00020", 1005*2c72404eSJin Yao "Offcore": "1", 1006*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1007*2c72404eSJin Yao "SampleAfterValue": "100003", 1008*2c72404eSJin Yao "UMask": "0x1" 1009*2c72404eSJin Yao }, 1010*2c72404eSJin Yao { 1011*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", 1012*2c72404eSJin Yao "Counter": "0,1,2,3", 1013*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1014*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 1015*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1016*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1017*2c72404eSJin Yao "MSRValue": "0x063FC00020", 1018*2c72404eSJin Yao "Offcore": "1", 1019*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1020*2c72404eSJin Yao "SampleAfterValue": "100003", 1021*2c72404eSJin Yao "UMask": "0x1" 1022*2c72404eSJin Yao }, 1023*2c72404eSJin Yao { 1024*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", 1025*2c72404eSJin Yao "Counter": "0,1,2,3", 1026*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1027*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 1028*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1029*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1030*2c72404eSJin Yao "MSRValue": "0x0604000020", 1031*2c72404eSJin Yao "Offcore": "1", 1032*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1033*2c72404eSJin Yao "SampleAfterValue": "100003", 1034*2c72404eSJin Yao "UMask": "0x1" 1035*2c72404eSJin Yao }, 1036*2c72404eSJin Yao { 1037*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", 1038*2c72404eSJin Yao "Counter": "0,1,2,3", 1039*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1040*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 1041*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1042*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1043*2c72404eSJin Yao "MSRValue": "0x063B800020", 1044*2c72404eSJin Yao "Offcore": "1", 1045*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1046*2c72404eSJin Yao "SampleAfterValue": "100003", 1047*2c72404eSJin Yao "UMask": "0x1" 1048*2c72404eSJin Yao }, 1049*2c72404eSJin Yao { 1050b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", 1051b5ff7f27SJin Yao "Counter": "0,1,2,3", 1052b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1053b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1054b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 1055b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1056b5ff7f27SJin Yao "MSRValue": "0x3FBC000080", 1057b5ff7f27SJin Yao "Offcore": "1", 1058b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1059b5ff7f27SJin Yao "SampleAfterValue": "100003", 1060b5ff7f27SJin Yao "UMask": "0x1" 1061b5ff7f27SJin Yao }, 1062b5ff7f27SJin Yao { 1063*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", 1064b5ff7f27SJin Yao "Counter": "0,1,2,3", 1065b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1066b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1067*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 1068b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1069*2c72404eSJin Yao "MSRValue": "0x103FC00080", 1070*2c72404eSJin Yao "Offcore": "1", 1071*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1072*2c72404eSJin Yao "SampleAfterValue": "100003", 1073*2c72404eSJin Yao "UMask": "0x1" 1074*2c72404eSJin Yao }, 1075*2c72404eSJin Yao { 1076*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 1077*2c72404eSJin Yao "Counter": "0,1,2,3", 1078*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1079*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 1080*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 1081*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1082*2c72404eSJin Yao "MSRValue": "0x083FC00080", 1083*2c72404eSJin Yao "Offcore": "1", 1084*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1085*2c72404eSJin Yao "SampleAfterValue": "100003", 1086*2c72404eSJin Yao "UMask": "0x1" 1087*2c72404eSJin Yao }, 1088*2c72404eSJin Yao { 1089*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", 1090*2c72404eSJin Yao "Counter": "0,1,2,3", 1091*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1092*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 1093*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1094*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1095*2c72404eSJin Yao "MSRValue": "0x063FC00080", 1096b5ff7f27SJin Yao "Offcore": "1", 1097b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1098b5ff7f27SJin Yao "SampleAfterValue": "100003", 1099b5ff7f27SJin Yao "UMask": "0x1" 1100b5ff7f27SJin Yao }, 1101b5ff7f27SJin Yao { 1102b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", 1103b5ff7f27SJin Yao "Counter": "0,1,2,3", 1104b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1105b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1106b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1107b5ff7f27SJin Yao "MSRIndex": "0x1a6,0x1a7", 1108b5ff7f27SJin Yao "MSRValue": "0x0604000080", 1109b5ff7f27SJin Yao "Offcore": "1", 1110b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1111b5ff7f27SJin Yao "SampleAfterValue": "100003", 1112b5ff7f27SJin Yao "UMask": "0x1" 1113b5ff7f27SJin Yao }, 1114b5ff7f27SJin Yao { 1115*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", 1116630171d4SAndi Kleen "Counter": "0,1,2,3", 1117b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1118630171d4SAndi Kleen "EventCode": "0xB7, 0xBB", 1119*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1120630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1121*2c72404eSJin Yao "MSRValue": "0x063B800080", 1122b5ff7f27SJin Yao "Offcore": "1", 1123b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1124630171d4SAndi Kleen "SampleAfterValue": "100003", 1125b5ff7f27SJin Yao "UMask": "0x1" 1126630171d4SAndi Kleen }, 1127630171d4SAndi Kleen { 1128*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", 1129630171d4SAndi Kleen "Counter": "0,1,2,3", 1130b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1131630171d4SAndi Kleen "EventCode": "0xB7, 0xBB", 1132*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", 1133630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1134*2c72404eSJin Yao "MSRValue": "0x3FBC000100", 1135b5ff7f27SJin Yao "Offcore": "1", 1136b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1137630171d4SAndi Kleen "SampleAfterValue": "100003", 1138b5ff7f27SJin Yao "UMask": "0x1" 1139630171d4SAndi Kleen }, 1140630171d4SAndi Kleen { 1141*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", 1142630171d4SAndi Kleen "Counter": "0,1,2,3", 1143b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1144b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1145*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", 1146630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1147*2c72404eSJin Yao "MSRValue": "0x103FC00100", 1148*2c72404eSJin Yao "Offcore": "1", 1149*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1150*2c72404eSJin Yao "SampleAfterValue": "100003", 1151*2c72404eSJin Yao "UMask": "0x1" 1152*2c72404eSJin Yao }, 1153*2c72404eSJin Yao { 1154*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 1155*2c72404eSJin Yao "Counter": "0,1,2,3", 1156*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1157*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 1158*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 1159*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1160*2c72404eSJin Yao "MSRValue": "0x083FC00100", 1161b5ff7f27SJin Yao "Offcore": "1", 1162b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1163630171d4SAndi Kleen "SampleAfterValue": "100003", 1164b5ff7f27SJin Yao "UMask": "0x1" 1165630171d4SAndi Kleen }, 1166630171d4SAndi Kleen { 1167b5ff7f27SJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", 1168630171d4SAndi Kleen "Counter": "0,1,2,3", 1169b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3", 1170b5ff7f27SJin Yao "EventCode": "0xB7, 0xBB", 1171b5ff7f27SJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 1172630171d4SAndi Kleen "MSRIndex": "0x1a6,0x1a7", 1173b5ff7f27SJin Yao "MSRValue": "0x063FC00100", 1174b5ff7f27SJin Yao "Offcore": "1", 1175b5ff7f27SJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1176630171d4SAndi Kleen "SampleAfterValue": "100003", 1177b5ff7f27SJin Yao "UMask": "0x1" 1178630171d4SAndi Kleen }, 1179630171d4SAndi Kleen { 1180*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", 1181630171d4SAndi Kleen "Counter": "0,1,2,3", 1182*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1183*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 1184*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1185*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1186*2c72404eSJin Yao "MSRValue": "0x0604000100", 1187*2c72404eSJin Yao "Offcore": "1", 1188*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1189*2c72404eSJin Yao "SampleAfterValue": "100003", 1190*2c72404eSJin Yao "UMask": "0x1" 1191630171d4SAndi Kleen }, 1192630171d4SAndi Kleen { 1193*2c72404eSJin Yao "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", 1194*2c72404eSJin Yao "Counter": "0,1,2,3", 1195*2c72404eSJin Yao "CounterHTOff": "0,1,2,3", 1196*2c72404eSJin Yao "EventCode": "0xB7, 0xBB", 1197*2c72404eSJin Yao "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1198*2c72404eSJin Yao "MSRIndex": "0x1a6,0x1a7", 1199*2c72404eSJin Yao "MSRValue": "0x063B800100", 1200*2c72404eSJin Yao "Offcore": "1", 1201*2c72404eSJin Yao "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1202*2c72404eSJin Yao "SampleAfterValue": "100003", 1203*2c72404eSJin Yao "UMask": "0x1" 1204*2c72404eSJin Yao }, 1205*2c72404eSJin Yao { 1206*2c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 1207630171d4SAndi Kleen "Counter": "0,1,2,3", 1208b5ff7f27SJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1209*2c72404eSJin Yao "EventCode": "0xC9", 1210*2c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED", 1211*2c72404eSJin Yao "PEBS": "1", 1212*2c72404eSJin Yao "PublicDescription": "Number of times RTM abort was triggered.", 1213*2c72404eSJin Yao "SampleAfterValue": "2000003", 1214*2c72404eSJin Yao "UMask": "0x4" 1215*2c72404eSJin Yao }, 1216*2c72404eSJin Yao { 1217*2c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 1218*2c72404eSJin Yao "Counter": "0,1,2,3", 1219*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1220*2c72404eSJin Yao "EventCode": "0xC9", 1221*2c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_EVENTS", 1222*2c72404eSJin Yao "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 1223b5ff7f27SJin Yao "SampleAfterValue": "2000003", 1224b5ff7f27SJin Yao "UMask": "0x80" 1225630171d4SAndi Kleen }, 1226630171d4SAndi Kleen { 1227*2c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 1228630171d4SAndi Kleen "Counter": "0,1,2,3", 1229*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1230*2c72404eSJin Yao "EventCode": "0xC9", 1231*2c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_MEM", 1232*2c72404eSJin Yao "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 1233*2c72404eSJin Yao "SampleAfterValue": "2000003", 1234*2c72404eSJin Yao "UMask": "0x8" 1235*2c72404eSJin Yao }, 1236*2c72404eSJin Yao { 1237*2c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 1238*2c72404eSJin Yao "Counter": "0,1,2,3", 1239*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1240*2c72404eSJin Yao "EventCode": "0xC9", 1241*2c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 1242*2c72404eSJin Yao "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 1243*2c72404eSJin Yao "SampleAfterValue": "2000003", 1244*2c72404eSJin Yao "UMask": "0x40" 1245*2c72404eSJin Yao }, 1246*2c72404eSJin Yao { 1247*2c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 1248*2c72404eSJin Yao "Counter": "0,1,2,3", 1249*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1250*2c72404eSJin Yao "EventCode": "0xC9", 1251*2c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_TIMER", 1252*2c72404eSJin Yao "SampleAfterValue": "2000003", 1253*2c72404eSJin Yao "UMask": "0x10" 1254*2c72404eSJin Yao }, 1255*2c72404eSJin Yao { 1256*2c72404eSJin Yao "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 1257*2c72404eSJin Yao "Counter": "0,1,2,3", 1258*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1259*2c72404eSJin Yao "EventCode": "0xC9", 1260*2c72404eSJin Yao "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 1261*2c72404eSJin Yao "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 1262*2c72404eSJin Yao "SampleAfterValue": "2000003", 1263*2c72404eSJin Yao "UMask": "0x20" 1264*2c72404eSJin Yao }, 1265*2c72404eSJin Yao { 1266*2c72404eSJin Yao "BriefDescription": "Number of times an RTM execution successfully committed", 1267*2c72404eSJin Yao "Counter": "0,1,2,3", 1268*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1269*2c72404eSJin Yao "EventCode": "0xC9", 1270*2c72404eSJin Yao "EventName": "RTM_RETIRED.COMMIT", 1271*2c72404eSJin Yao "PublicDescription": "Number of times RTM commit succeeded.", 1272*2c72404eSJin Yao "SampleAfterValue": "2000003", 1273*2c72404eSJin Yao "UMask": "0x2" 1274*2c72404eSJin Yao }, 1275*2c72404eSJin Yao { 1276*2c72404eSJin Yao "BriefDescription": "Number of times an RTM execution started.", 1277*2c72404eSJin Yao "Counter": "0,1,2,3", 1278*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1279*2c72404eSJin Yao "EventCode": "0xC9", 1280*2c72404eSJin Yao "EventName": "RTM_RETIRED.START", 1281*2c72404eSJin Yao "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 1282*2c72404eSJin Yao "SampleAfterValue": "2000003", 1283b5ff7f27SJin Yao "UMask": "0x1" 1284b5ff7f27SJin Yao }, 1285b5ff7f27SJin Yao { 1286*2c72404eSJin Yao "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 1287b5ff7f27SJin Yao "Counter": "0,1,2,3", 1288*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1289*2c72404eSJin Yao "EventCode": "0x5d", 1290*2c72404eSJin Yao "EventName": "TX_EXEC.MISC1", 1291*2c72404eSJin Yao "SampleAfterValue": "2000003", 1292b5ff7f27SJin Yao "UMask": "0x1" 1293b5ff7f27SJin Yao }, 1294b5ff7f27SJin Yao { 1295*2c72404eSJin Yao "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 1296b5ff7f27SJin Yao "Counter": "0,1,2,3", 1297*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1298*2c72404eSJin Yao "EventCode": "0x5d", 1299*2c72404eSJin Yao "EventName": "TX_EXEC.MISC2", 1300*2c72404eSJin Yao "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 1301*2c72404eSJin Yao "SampleAfterValue": "2000003", 1302*2c72404eSJin Yao "UMask": "0x2" 1303*2c72404eSJin Yao }, 1304*2c72404eSJin Yao { 1305*2c72404eSJin Yao "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 1306*2c72404eSJin Yao "Counter": "0,1,2,3", 1307*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1308*2c72404eSJin Yao "EventCode": "0x5d", 1309*2c72404eSJin Yao "EventName": "TX_EXEC.MISC3", 1310*2c72404eSJin Yao "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 1311*2c72404eSJin Yao "SampleAfterValue": "2000003", 1312*2c72404eSJin Yao "UMask": "0x4" 1313*2c72404eSJin Yao }, 1314*2c72404eSJin Yao { 1315*2c72404eSJin Yao "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 1316*2c72404eSJin Yao "Counter": "0,1,2,3", 1317*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1318*2c72404eSJin Yao "EventCode": "0x5d", 1319*2c72404eSJin Yao "EventName": "TX_EXEC.MISC4", 1320*2c72404eSJin Yao "PublicDescription": "RTM region detected inside HLE.", 1321*2c72404eSJin Yao "SampleAfterValue": "2000003", 1322*2c72404eSJin Yao "UMask": "0x8" 1323*2c72404eSJin Yao }, 1324*2c72404eSJin Yao { 1325*2c72404eSJin Yao "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 1326*2c72404eSJin Yao "Counter": "0,1,2,3", 1327*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1328*2c72404eSJin Yao "EventCode": "0x5d", 1329*2c72404eSJin Yao "EventName": "TX_EXEC.MISC5", 1330*2c72404eSJin Yao "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 1331*2c72404eSJin Yao "SampleAfterValue": "2000003", 1332*2c72404eSJin Yao "UMask": "0x10" 1333*2c72404eSJin Yao }, 1334*2c72404eSJin Yao { 1335*2c72404eSJin Yao "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 1336*2c72404eSJin Yao "Counter": "0,1,2,3", 1337*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1338*2c72404eSJin Yao "EventCode": "0x54", 1339*2c72404eSJin Yao "EventName": "TX_MEM.ABORT_CAPACITY", 1340*2c72404eSJin Yao "SampleAfterValue": "2000003", 1341*2c72404eSJin Yao "UMask": "0x2" 1342*2c72404eSJin Yao }, 1343*2c72404eSJin Yao { 1344*2c72404eSJin Yao "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 1345*2c72404eSJin Yao "Counter": "0,1,2,3", 1346*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1347*2c72404eSJin Yao "EventCode": "0x54", 1348*2c72404eSJin Yao "EventName": "TX_MEM.ABORT_CONFLICT", 1349*2c72404eSJin Yao "PublicDescription": "Number of times a TSX line had a cache conflict.", 1350*2c72404eSJin Yao "SampleAfterValue": "2000003", 1351b5ff7f27SJin Yao "UMask": "0x1" 1352b5ff7f27SJin Yao }, 1353b5ff7f27SJin Yao { 1354*2c72404eSJin Yao "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 1355b5ff7f27SJin Yao "Counter": "0,1,2,3", 1356*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1357*2c72404eSJin Yao "EventCode": "0x54", 1358*2c72404eSJin Yao "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 1359*2c72404eSJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 1360*2c72404eSJin Yao "SampleAfterValue": "2000003", 1361*2c72404eSJin Yao "UMask": "0x10" 1362*2c72404eSJin Yao }, 1363*2c72404eSJin Yao { 1364*2c72404eSJin Yao "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 1365*2c72404eSJin Yao "Counter": "0,1,2,3", 1366*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1367*2c72404eSJin Yao "EventCode": "0x54", 1368*2c72404eSJin Yao "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 1369*2c72404eSJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 1370*2c72404eSJin Yao "SampleAfterValue": "2000003", 1371*2c72404eSJin Yao "UMask": "0x8" 1372*2c72404eSJin Yao }, 1373*2c72404eSJin Yao { 1374*2c72404eSJin Yao "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 1375*2c72404eSJin Yao "Counter": "0,1,2,3", 1376*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1377*2c72404eSJin Yao "EventCode": "0x54", 1378*2c72404eSJin Yao "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 1379*2c72404eSJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 1380*2c72404eSJin Yao "SampleAfterValue": "2000003", 1381*2c72404eSJin Yao "UMask": "0x20" 1382*2c72404eSJin Yao }, 1383*2c72404eSJin Yao { 1384*2c72404eSJin Yao "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 1385*2c72404eSJin Yao "Counter": "0,1,2,3", 1386*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1387*2c72404eSJin Yao "EventCode": "0x54", 1388*2c72404eSJin Yao "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 1389*2c72404eSJin Yao "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 1390*2c72404eSJin Yao "SampleAfterValue": "2000003", 1391*2c72404eSJin Yao "UMask": "0x4" 1392*2c72404eSJin Yao }, 1393*2c72404eSJin Yao { 1394*2c72404eSJin Yao "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 1395*2c72404eSJin Yao "Counter": "0,1,2,3", 1396*2c72404eSJin Yao "CounterHTOff": "0,1,2,3,4,5,6,7", 1397*2c72404eSJin Yao "EventCode": "0x54", 1398*2c72404eSJin Yao "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 1399*2c72404eSJin Yao "PublicDescription": "Number of times we could not allocate Lock Buffer.", 1400*2c72404eSJin Yao "SampleAfterValue": "2000003", 1401*2c72404eSJin Yao "UMask": "0x40" 1402630171d4SAndi Kleen } 1403630171d4SAndi Kleen]