147cbd67eSAndi Kleen[ 247cbd67eSAndi Kleen { 3c93240a7SAndi Kleen "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", 4c93240a7SAndi Kleen "EventCode": "0x08", 547cbd67eSAndi Kleen "Counter": "0,1,2,3", 647cbd67eSAndi Kleen "UMask": "0x1", 7c93240a7SAndi Kleen "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 8c93240a7SAndi Kleen "SampleAfterValue": "100003", 9c93240a7SAndi Kleen "BriefDescription": "Load misses in all DTLB levels that cause page walks", 1047cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 1147cbd67eSAndi Kleen }, 1247cbd67eSAndi Kleen { 13c93240a7SAndi Kleen "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", 14c93240a7SAndi Kleen "EventCode": "0x08", 15c93240a7SAndi Kleen "Counter": "0,1,2,3", 16c93240a7SAndi Kleen "UMask": "0x2", 17c93240a7SAndi Kleen "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 18c93240a7SAndi Kleen "SampleAfterValue": "2000003", 19c93240a7SAndi Kleen "BriefDescription": "Page walk completed due to a demand data load to a 4K page", 20c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 21c93240a7SAndi Kleen }, 22c93240a7SAndi Kleen { 23c93240a7SAndi Kleen "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", 24c93240a7SAndi Kleen "EventCode": "0x08", 25c93240a7SAndi Kleen "Counter": "0,1,2,3", 26c93240a7SAndi Kleen "UMask": "0x4", 27c93240a7SAndi Kleen "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 28c93240a7SAndi Kleen "SampleAfterValue": "2000003", 29c93240a7SAndi Kleen "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", 30c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 31c93240a7SAndi Kleen }, 32c93240a7SAndi Kleen { 33c93240a7SAndi Kleen "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", 34c93240a7SAndi Kleen "EventCode": "0x08", 35c93240a7SAndi Kleen "Counter": "0,1,2,3", 36c93240a7SAndi Kleen "UMask": "0x8", 37c93240a7SAndi Kleen "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 38c93240a7SAndi Kleen "SampleAfterValue": "2000003", 39c93240a7SAndi Kleen "BriefDescription": "Page walk completed due to a demand data load to a 1G page", 40c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 41c93240a7SAndi Kleen }, 42c93240a7SAndi Kleen { 43c93240a7SAndi Kleen "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", 44c93240a7SAndi Kleen "EventCode": "0x08", 45c93240a7SAndi Kleen "Counter": "0,1,2,3", 46c93240a7SAndi Kleen "UMask": "0xe", 47c93240a7SAndi Kleen "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 48c93240a7SAndi Kleen "SampleAfterValue": "100003", 49c93240a7SAndi Kleen "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", 50c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 51c93240a7SAndi Kleen }, 52c93240a7SAndi Kleen { 53c93240a7SAndi Kleen "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.", 54c93240a7SAndi Kleen "EventCode": "0x08", 55c93240a7SAndi Kleen "Counter": "0,1,2,3", 56c93240a7SAndi Kleen "UMask": "0x10", 57c93240a7SAndi Kleen "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", 58c93240a7SAndi Kleen "SampleAfterValue": "2000003", 59c93240a7SAndi Kleen "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", 60c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 61c93240a7SAndi Kleen }, 62c93240a7SAndi Kleen { 63c93240a7SAndi Kleen "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.", 64c93240a7SAndi Kleen "EventCode": "0x08", 65c93240a7SAndi Kleen "Counter": "0,1,2,3", 66c93240a7SAndi Kleen "UMask": "0x10", 67c93240a7SAndi Kleen "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", 68c93240a7SAndi Kleen "SampleAfterValue": "100003", 69c93240a7SAndi Kleen "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", 70c93240a7SAndi Kleen "CounterMask": "1", 71c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 72c93240a7SAndi Kleen }, 73c93240a7SAndi Kleen { 74c93240a7SAndi Kleen "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", 75c93240a7SAndi Kleen "EventCode": "0x08", 76c93240a7SAndi Kleen "Counter": "0,1,2,3", 77c93240a7SAndi Kleen "UMask": "0x20", 78c93240a7SAndi Kleen "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 79c93240a7SAndi Kleen "SampleAfterValue": "2000003", 80c93240a7SAndi Kleen "BriefDescription": "Loads that miss the DTLB and hit the STLB.", 81c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 82c93240a7SAndi Kleen }, 83c93240a7SAndi Kleen { 84c93240a7SAndi Kleen "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", 85c93240a7SAndi Kleen "EventCode": "0x49", 86c93240a7SAndi Kleen "Counter": "0,1,2,3", 87c93240a7SAndi Kleen "UMask": "0x1", 88c93240a7SAndi Kleen "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 89c93240a7SAndi Kleen "SampleAfterValue": "100003", 90c93240a7SAndi Kleen "BriefDescription": "Store misses in all DTLB levels that cause page walks", 91c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 92c93240a7SAndi Kleen }, 93c93240a7SAndi Kleen { 94c93240a7SAndi Kleen "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", 95c93240a7SAndi Kleen "EventCode": "0x49", 96c93240a7SAndi Kleen "Counter": "0,1,2,3", 97c93240a7SAndi Kleen "UMask": "0x2", 98c93240a7SAndi Kleen "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 99c93240a7SAndi Kleen "SampleAfterValue": "100003", 100c93240a7SAndi Kleen "BriefDescription": "Page walk completed due to a demand data store to a 4K page", 101c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 102c93240a7SAndi Kleen }, 103c93240a7SAndi Kleen { 104c93240a7SAndi Kleen "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", 105c93240a7SAndi Kleen "EventCode": "0x49", 106c93240a7SAndi Kleen "Counter": "0,1,2,3", 107c93240a7SAndi Kleen "UMask": "0x4", 108c93240a7SAndi Kleen "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 109c93240a7SAndi Kleen "SampleAfterValue": "100003", 110c93240a7SAndi Kleen "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", 111c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 112c93240a7SAndi Kleen }, 113c93240a7SAndi Kleen { 114c93240a7SAndi Kleen "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages. The page walks can end with or without a page fault.", 115c93240a7SAndi Kleen "EventCode": "0x49", 116c93240a7SAndi Kleen "Counter": "0,1,2,3", 117c93240a7SAndi Kleen "UMask": "0x8", 118c93240a7SAndi Kleen "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 119c93240a7SAndi Kleen "SampleAfterValue": "100003", 120c93240a7SAndi Kleen "BriefDescription": "Page walk completed due to a demand data store to a 1G page", 121c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 122c93240a7SAndi Kleen }, 123c93240a7SAndi Kleen { 124c93240a7SAndi Kleen "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", 125c93240a7SAndi Kleen "EventCode": "0x49", 126c93240a7SAndi Kleen "Counter": "0,1,2,3", 127c93240a7SAndi Kleen "UMask": "0xe", 128c93240a7SAndi Kleen "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 129c93240a7SAndi Kleen "SampleAfterValue": "100003", 130c93240a7SAndi Kleen "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", 131c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 132c93240a7SAndi Kleen }, 133c93240a7SAndi Kleen { 134c93240a7SAndi Kleen "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.", 135c93240a7SAndi Kleen "EventCode": "0x49", 136c93240a7SAndi Kleen "Counter": "0,1,2,3", 137c93240a7SAndi Kleen "UMask": "0x10", 138c93240a7SAndi Kleen "EventName": "DTLB_STORE_MISSES.WALK_PENDING", 139c93240a7SAndi Kleen "SampleAfterValue": "2000003", 140c93240a7SAndi Kleen "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", 141c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 142c93240a7SAndi Kleen }, 143c93240a7SAndi Kleen { 144c93240a7SAndi Kleen "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", 145c93240a7SAndi Kleen "EventCode": "0x49", 146c93240a7SAndi Kleen "Counter": "0,1,2,3", 147c93240a7SAndi Kleen "UMask": "0x10", 148c93240a7SAndi Kleen "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", 149c93240a7SAndi Kleen "SampleAfterValue": "100003", 150c93240a7SAndi Kleen "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", 151c93240a7SAndi Kleen "CounterMask": "1", 152c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 153c93240a7SAndi Kleen }, 154c93240a7SAndi Kleen { 155c93240a7SAndi Kleen "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 156c93240a7SAndi Kleen "EventCode": "0x49", 157c93240a7SAndi Kleen "Counter": "0,1,2,3", 158c93240a7SAndi Kleen "UMask": "0x20", 159c93240a7SAndi Kleen "EventName": "DTLB_STORE_MISSES.STLB_HIT", 160c93240a7SAndi Kleen "SampleAfterValue": "100003", 161c93240a7SAndi Kleen "BriefDescription": "Stores that miss the DTLB and hit the STLB.", 162c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 163c93240a7SAndi Kleen }, 164c93240a7SAndi Kleen { 165c93240a7SAndi Kleen "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.", 16647cbd67eSAndi Kleen "EventCode": "0x4F", 16747cbd67eSAndi Kleen "Counter": "0,1,2,3", 16847cbd67eSAndi Kleen "UMask": "0x10", 16947cbd67eSAndi Kleen "EventName": "EPT.WALK_PENDING", 17047cbd67eSAndi Kleen "SampleAfterValue": "2000003", 17147cbd67eSAndi Kleen "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", 17247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 17347cbd67eSAndi Kleen }, 17447cbd67eSAndi Kleen { 175c93240a7SAndi Kleen "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.", 17647cbd67eSAndi Kleen "EventCode": "0x85", 17747cbd67eSAndi Kleen "Counter": "0,1,2,3", 17847cbd67eSAndi Kleen "UMask": "0x1", 17947cbd67eSAndi Kleen "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 18047cbd67eSAndi Kleen "SampleAfterValue": "100003", 18147cbd67eSAndi Kleen "BriefDescription": "Misses at all ITLB levels that cause page walks", 18247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 18347cbd67eSAndi Kleen }, 18447cbd67eSAndi Kleen { 185c93240a7SAndi Kleen "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", 18647cbd67eSAndi Kleen "EventCode": "0x85", 18747cbd67eSAndi Kleen "Counter": "0,1,2,3", 18847cbd67eSAndi Kleen "UMask": "0x2", 18947cbd67eSAndi Kleen "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 19047cbd67eSAndi Kleen "SampleAfterValue": "100003", 19147cbd67eSAndi Kleen "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 19247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 19347cbd67eSAndi Kleen }, 19447cbd67eSAndi Kleen { 195c93240a7SAndi Kleen "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", 19647cbd67eSAndi Kleen "EventCode": "0x85", 19747cbd67eSAndi Kleen "Counter": "0,1,2,3", 19847cbd67eSAndi Kleen "UMask": "0x4", 19947cbd67eSAndi Kleen "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 20047cbd67eSAndi Kleen "SampleAfterValue": "100003", 20147cbd67eSAndi Kleen "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 20247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 20347cbd67eSAndi Kleen }, 20447cbd67eSAndi Kleen { 205c93240a7SAndi Kleen "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", 20647cbd67eSAndi Kleen "EventCode": "0x85", 20747cbd67eSAndi Kleen "Counter": "0,1,2,3", 20847cbd67eSAndi Kleen "UMask": "0x8", 20947cbd67eSAndi Kleen "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", 21047cbd67eSAndi Kleen "SampleAfterValue": "100003", 21147cbd67eSAndi Kleen "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", 21247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 21347cbd67eSAndi Kleen }, 21447cbd67eSAndi Kleen { 215c93240a7SAndi Kleen "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", 216c93240a7SAndi Kleen "EventCode": "0x85", 217c93240a7SAndi Kleen "Counter": "0,1,2,3", 218c93240a7SAndi Kleen "UMask": "0xe", 219c93240a7SAndi Kleen "EventName": "ITLB_MISSES.WALK_COMPLETED", 220c93240a7SAndi Kleen "SampleAfterValue": "100003", 221c93240a7SAndi Kleen "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", 222c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 223c93240a7SAndi Kleen }, 224c93240a7SAndi Kleen { 225c93240a7SAndi Kleen "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.", 22647cbd67eSAndi Kleen "EventCode": "0x85", 22747cbd67eSAndi Kleen "Counter": "0,1,2,3", 22847cbd67eSAndi Kleen "UMask": "0x10", 22947cbd67eSAndi Kleen "EventName": "ITLB_MISSES.WALK_PENDING", 23047cbd67eSAndi Kleen "SampleAfterValue": "100003", 23147cbd67eSAndi Kleen "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", 23247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 23347cbd67eSAndi Kleen }, 23447cbd67eSAndi Kleen { 235c93240a7SAndi Kleen "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.", 236c93240a7SAndi Kleen "EventCode": "0x85", 237c93240a7SAndi Kleen "Counter": "0,1,2,3", 238c93240a7SAndi Kleen "UMask": "0x10", 239c93240a7SAndi Kleen "EventName": "ITLB_MISSES.WALK_ACTIVE", 240c93240a7SAndi Kleen "SampleAfterValue": "100003", 241c93240a7SAndi Kleen "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.", 242c93240a7SAndi Kleen "CounterMask": "1", 243c93240a7SAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 244c93240a7SAndi Kleen }, 245c93240a7SAndi Kleen { 24647cbd67eSAndi Kleen "EventCode": "0x85", 24747cbd67eSAndi Kleen "Counter": "0,1,2,3", 24847cbd67eSAndi Kleen "UMask": "0x20", 24947cbd67eSAndi Kleen "EventName": "ITLB_MISSES.STLB_HIT", 25047cbd67eSAndi Kleen "SampleAfterValue": "100003", 25147cbd67eSAndi Kleen "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", 25247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 25347cbd67eSAndi Kleen }, 25447cbd67eSAndi Kleen { 255c93240a7SAndi Kleen "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", 256c93240a7SAndi Kleen "EventCode": "0xAE", 25747cbd67eSAndi Kleen "Counter": "0,1,2,3", 25847cbd67eSAndi Kleen "UMask": "0x1", 259c93240a7SAndi Kleen "EventName": "ITLB.ITLB_FLUSH", 260c93240a7SAndi Kleen "SampleAfterValue": "100007", 261c93240a7SAndi Kleen "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 26247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 26347cbd67eSAndi Kleen }, 26447cbd67eSAndi Kleen { 265c93240a7SAndi Kleen "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", 26647cbd67eSAndi Kleen "EventCode": "0xBD", 26747cbd67eSAndi Kleen "Counter": "0,1,2,3", 26847cbd67eSAndi Kleen "UMask": "0x1", 26947cbd67eSAndi Kleen "EventName": "TLB_FLUSH.DTLB_THREAD", 27047cbd67eSAndi Kleen "SampleAfterValue": "100007", 27147cbd67eSAndi Kleen "BriefDescription": "DTLB flush attempts of the thread-specific entries", 27247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 27347cbd67eSAndi Kleen }, 27447cbd67eSAndi Kleen { 275c93240a7SAndi Kleen "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", 27647cbd67eSAndi Kleen "EventCode": "0xBD", 27747cbd67eSAndi Kleen "Counter": "0,1,2,3", 27847cbd67eSAndi Kleen "UMask": "0x20", 27947cbd67eSAndi Kleen "EventName": "TLB_FLUSH.STLB_ANY", 28047cbd67eSAndi Kleen "SampleAfterValue": "100007", 28147cbd67eSAndi Kleen "BriefDescription": "STLB flush attempts", 28247cbd67eSAndi Kleen "CounterHTOff": "0,1,2,3,4,5,6,7" 28347cbd67eSAndi Kleen } 28447cbd67eSAndi Kleen]