1[
2    {
3        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
4        "EventCode": "0x84",
5        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
6        "PerPkg": "1",
7        "UMask": "0x1",
8        "Unit": "ARB"
9    },
10    {
11        "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
12        "EventCode": "0x80",
13        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
14        "PerPkg": "1",
15        "UMask": "0x1",
16        "Unit": "ARB"
17    },
18    {
19        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
20        "CounterMask": "1",
21        "EventCode": "0x80",
22        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
23        "PerPkg": "1",
24        "UMask": "0x1",
25        "Unit": "ARB"
26    },
27    {
28        "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
29        "EventCode": "0x80",
30        "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
31        "PerPkg": "1",
32        "UMask": "0x2",
33        "Unit": "ARB"
34    },
35    {
36        "EventCode": "0x81",
37        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
38        "PerPkg": "1",
39        "UMask": "0x1",
40        "Unit": "ARB"
41    },
42    {
43        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
44        "EventCode": "0x81",
45        "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
46        "PerPkg": "1",
47        "UMask": "0x2",
48        "Unit": "ARB"
49    },
50    {
51        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
52        "EventCode": "0x81",
53        "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
54        "PerPkg": "1",
55        "UMask": "0x2",
56        "Unit": "ARB"
57    },
58    {
59        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
60        "EventCode": "0x81",
61        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
62        "PerPkg": "1",
63        "UMask": "0x20",
64        "Unit": "ARB"
65    },
66    {
67        "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
68        "EventCode": "0xff",
69        "EventName": "UNC_CLOCK.SOCKET",
70        "PerPkg": "1",
71        "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
72        "Unit": "CLOCK"
73    }
74]
75