1*9a8b3036SIan Rogers[ 2*9a8b3036SIan Rogers { 3*9a8b3036SIan Rogers "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", 4*9a8b3036SIan Rogers "EventCode": "0x84", 5*9a8b3036SIan Rogers "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", 6*9a8b3036SIan Rogers "PerPkg": "1", 7*9a8b3036SIan Rogers "UMask": "0x1", 8*9a8b3036SIan Rogers "Unit": "ARB" 9*9a8b3036SIan Rogers }, 10*9a8b3036SIan Rogers { 11*9a8b3036SIan Rogers "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.", 12*9a8b3036SIan Rogers "EventCode": "0x80", 13*9a8b3036SIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", 14*9a8b3036SIan Rogers "PerPkg": "1", 15*9a8b3036SIan Rogers "UMask": "0x1", 16*9a8b3036SIan Rogers "Unit": "ARB" 17*9a8b3036SIan Rogers }, 18*9a8b3036SIan Rogers { 19*9a8b3036SIan Rogers "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 20*9a8b3036SIan Rogers "CounterMask": "1", 21*9a8b3036SIan Rogers "EventCode": "0x80", 22*9a8b3036SIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", 23*9a8b3036SIan Rogers "PerPkg": "1", 24*9a8b3036SIan Rogers "UMask": "0x1", 25*9a8b3036SIan Rogers "Unit": "ARB" 26*9a8b3036SIan Rogers }, 27*9a8b3036SIan Rogers { 28*9a8b3036SIan Rogers "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.", 29*9a8b3036SIan Rogers "EventCode": "0x80", 30*9a8b3036SIan Rogers "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ", 31*9a8b3036SIan Rogers "PerPkg": "1", 32*9a8b3036SIan Rogers "UMask": "0x2", 33*9a8b3036SIan Rogers "Unit": "ARB" 34*9a8b3036SIan Rogers }, 35*9a8b3036SIan Rogers { 36*9a8b3036SIan Rogers "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", 37*9a8b3036SIan Rogers "EventCode": "0x81", 38*9a8b3036SIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.ALL", 39*9a8b3036SIan Rogers "PerPkg": "1", 40*9a8b3036SIan Rogers "UMask": "0x1", 41*9a8b3036SIan Rogers "Unit": "ARB" 42*9a8b3036SIan Rogers }, 43*9a8b3036SIan Rogers { 44*9a8b3036SIan Rogers "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", 45*9a8b3036SIan Rogers "EventCode": "0x81", 46*9a8b3036SIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ", 47*9a8b3036SIan Rogers "PerPkg": "1", 48*9a8b3036SIan Rogers "UMask": "0x2", 49*9a8b3036SIan Rogers "Unit": "ARB" 50*9a8b3036SIan Rogers }, 51*9a8b3036SIan Rogers { 52*9a8b3036SIan Rogers "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", 53*9a8b3036SIan Rogers "EventCode": "0x81", 54*9a8b3036SIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", 55*9a8b3036SIan Rogers "PerPkg": "1", 56*9a8b3036SIan Rogers "UMask": "0x2", 57*9a8b3036SIan Rogers "Unit": "ARB" 58*9a8b3036SIan Rogers }, 59*9a8b3036SIan Rogers { 60*9a8b3036SIan Rogers "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", 61*9a8b3036SIan Rogers "EventCode": "0x81", 62*9a8b3036SIan Rogers "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", 63*9a8b3036SIan Rogers "PerPkg": "1", 64*9a8b3036SIan Rogers "UMask": "0x20", 65*9a8b3036SIan Rogers "Unit": "ARB" 66*9a8b3036SIan Rogers } 67*9a8b3036SIan Rogers] 68