1[ 2 { 3 "BriefDescription": "Number of hardware interrupts received by the processor.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xCB", 7 "EventName": "HW_INTERRUPTS.RECEIVED", 8 "PublicDescription": "Counts the number of hardware interruptions received by the processor.", 9 "SampleAfterValue": "203", 10 "UMask": "0x1" 11 }, 12 { 13 "Counter": "0,1,2,3", 14 "CounterHTOff": "0,1,2,3,4,5,6,7", 15 "EventCode": "0x09", 16 "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", 17 "SampleAfterValue": "2000003", 18 "UMask": "0x1" 19 }, 20 { 21 "BriefDescription": "Number of PREFETCHNTA instructions executed.", 22 "Counter": "0,1,2,3", 23 "CounterHTOff": "0,1,2,3,4,5,6,7", 24 "EventCode": "0x32", 25 "EventName": "SW_PREFETCH_ACCESS.NTA", 26 "SampleAfterValue": "2000003", 27 "UMask": "0x1" 28 }, 29 { 30 "BriefDescription": "Number of PREFETCHW instructions executed.", 31 "Counter": "0,1,2,3", 32 "CounterHTOff": "0,1,2,3,4,5,6,7", 33 "EventCode": "0x32", 34 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 35 "SampleAfterValue": "2000003", 36 "UMask": "0x8" 37 }, 38 { 39 "BriefDescription": "Number of PREFETCHT0 instructions executed.", 40 "Counter": "0,1,2,3", 41 "CounterHTOff": "0,1,2,3,4,5,6,7", 42 "EventCode": "0x32", 43 "EventName": "SW_PREFETCH_ACCESS.T0", 44 "SampleAfterValue": "2000003", 45 "UMask": "0x2" 46 }, 47 { 48 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 49 "Counter": "0,1,2,3", 50 "CounterHTOff": "0,1,2,3,4,5,6,7", 51 "EventCode": "0x32", 52 "EventName": "SW_PREFETCH_ACCESS.T1_T2", 53 "SampleAfterValue": "2000003", 54 "UMask": "0x4" 55 } 56]