1[
2    {
3        "BriefDescription": "Number of PREFETCHW instructions executed.",
4        "Counter": "0,1,2,3",
5        "CounterHTOff": "0,1,2,3,4,5,6,7",
6        "EventCode": "0x32",
7        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
8        "SampleAfterValue": "2000003",
9        "UMask": "0x8"
10    },
11    {
12        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
13        "Counter": "0,1,2,3",
14        "CounterHTOff": "0,1,2,3,4,5,6,7",
15        "EventCode": "0x32",
16        "EventName": "SW_PREFETCH_ACCESS.T0",
17        "SampleAfterValue": "2000003",
18        "UMask": "0x2"
19    },
20    {
21        "BriefDescription": "Number of hardware interrupts received by the processor.",
22        "Counter": "0,1,2,3",
23        "CounterHTOff": "0,1,2,3,4,5,6,7",
24        "EventCode": "0xCB",
25        "EventName": "HW_INTERRUPTS.RECEIVED",
26        "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
27        "SampleAfterValue": "203",
28        "UMask": "0x1"
29    },
30    {
31        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
32        "Counter": "0,1,2,3",
33        "CounterHTOff": "0,1,2,3,4,5,6,7",
34        "EventCode": "0x32",
35        "EventName": "SW_PREFETCH_ACCESS.NTA",
36        "SampleAfterValue": "2000003",
37        "UMask": "0x1"
38    },
39    {
40        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
41        "Counter": "0,1,2,3",
42        "CounterHTOff": "0,1,2,3,4,5,6,7",
43        "EventCode": "0x32",
44        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
45        "SampleAfterValue": "2000003",
46        "UMask": "0x4"
47    },
48    {
49        "Counter": "0,1,2,3",
50        "CounterHTOff": "0,1,2,3,4,5,6,7",
51        "EventCode": "0x09",
52        "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
53        "SampleAfterValue": "2000003",
54        "UMask": "0x1"
55    }
56]