1[ 2 { 3 "PublicDescription": "Unfriendly TSX abort triggered by a flowmarker.", 4 "EventCode": "0x5d", 5 "Counter": "0,1,2,3", 6 "UMask": "0x1", 7 "EventName": "TX_EXEC.MISC1", 8 "SampleAfterValue": "2000003", 9 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 14 "EventCode": "0x5d", 15 "Counter": "0,1,2,3", 16 "UMask": "0x2", 17 "EventName": "TX_EXEC.MISC2", 18 "SampleAfterValue": "2000003", 19 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 20 "CounterHTOff": "0,1,2,3,4,5,6,7" 21 }, 22 { 23 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 24 "EventCode": "0x5d", 25 "Counter": "0,1,2,3", 26 "UMask": "0x4", 27 "EventName": "TX_EXEC.MISC3", 28 "SampleAfterValue": "2000003", 29 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 30 "CounterHTOff": "0,1,2,3,4,5,6,7" 31 }, 32 { 33 "PublicDescription": "RTM region detected inside HLE.", 34 "EventCode": "0x5d", 35 "Counter": "0,1,2,3", 36 "UMask": "0x8", 37 "EventName": "TX_EXEC.MISC4", 38 "SampleAfterValue": "2000003", 39 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 40 "CounterHTOff": "0,1,2,3,4,5,6,7" 41 }, 42 { 43 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 44 "EventCode": "0x5d", 45 "Counter": "0,1,2,3", 46 "UMask": "0x10", 47 "EventName": "TX_EXEC.MISC5", 48 "SampleAfterValue": "2000003", 49 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 50 "CounterHTOff": "0,1,2,3,4,5,6,7" 51 }, 52 { 53 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", 54 "EventCode": "0xC8", 55 "Counter": "0,1,2,3", 56 "UMask": "0x1", 57 "EventName": "HLE_RETIRED.START", 58 "SampleAfterValue": "2000003", 59 "BriefDescription": "Number of times an HLE execution started.", 60 "CounterHTOff": "0,1,2,3,4,5,6,7" 61 }, 62 { 63 "PublicDescription": "Number of times HLE commit succeeded.", 64 "EventCode": "0xC8", 65 "Counter": "0,1,2,3", 66 "UMask": "0x2", 67 "EventName": "HLE_RETIRED.COMMIT", 68 "SampleAfterValue": "2000003", 69 "BriefDescription": "Number of times an HLE execution successfully committed", 70 "CounterHTOff": "0,1,2,3,4,5,6,7" 71 }, 72 { 73 "PEBS": "1", 74 "PublicDescription": "Number of times HLE abort was triggered.", 75 "EventCode": "0xC8", 76 "Counter": "0,1,2,3", 77 "UMask": "0x4", 78 "EventName": "HLE_RETIRED.ABORTED", 79 "SampleAfterValue": "2000003", 80 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ", 81 "CounterHTOff": "0,1,2,3,4,5,6,7" 82 }, 83 { 84 "EventCode": "0xC8", 85 "Counter": "0,1,2,3", 86 "UMask": "0x8", 87 "EventName": "HLE_RETIRED.ABORTED_MEM", 88 "SampleAfterValue": "2000003", 89 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 90 "CounterHTOff": "0,1,2,3,4,5,6,7" 91 }, 92 { 93 "EventCode": "0xC8", 94 "Counter": "0,1,2,3", 95 "UMask": "0x10", 96 "EventName": "HLE_RETIRED.ABORTED_TIMER", 97 "SampleAfterValue": "2000003", 98 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 99 "CounterHTOff": "0,1,2,3,4,5,6,7" 100 }, 101 { 102 "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 103 "EventCode": "0xC8", 104 "Counter": "0,1,2,3", 105 "UMask": "0x20", 106 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 107 "SampleAfterValue": "2000003", 108 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.). ", 109 "CounterHTOff": "0,1,2,3,4,5,6,7" 110 }, 111 { 112 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 113 "EventCode": "0xC8", 114 "Counter": "0,1,2,3", 115 "UMask": "0x40", 116 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 117 "SampleAfterValue": "2000003", 118 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 119 "CounterHTOff": "0,1,2,3,4,5,6,7" 120 }, 121 { 122 "EventCode": "0xC8", 123 "Counter": "0,1,2,3", 124 "UMask": "0x80", 125 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 126 "SampleAfterValue": "2000003", 127 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 128 "CounterHTOff": "0,1,2,3,4,5,6,7" 129 }, 130 { 131 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", 132 "EventCode": "0xC9", 133 "Counter": "0,1,2,3", 134 "UMask": "0x1", 135 "EventName": "RTM_RETIRED.START", 136 "SampleAfterValue": "2000003", 137 "BriefDescription": "Number of times an RTM execution started.", 138 "CounterHTOff": "0,1,2,3,4,5,6,7" 139 }, 140 { 141 "PublicDescription": "Number of times RTM commit succeeded.", 142 "EventCode": "0xC9", 143 "Counter": "0,1,2,3", 144 "UMask": "0x2", 145 "EventName": "RTM_RETIRED.COMMIT", 146 "SampleAfterValue": "2000003", 147 "BriefDescription": "Number of times an RTM execution successfully committed", 148 "CounterHTOff": "0,1,2,3,4,5,6,7" 149 }, 150 { 151 "PEBS": "1", 152 "PublicDescription": "Number of times RTM abort was triggered.", 153 "EventCode": "0xC9", 154 "Counter": "0,1,2,3", 155 "UMask": "0x4", 156 "EventName": "RTM_RETIRED.ABORTED", 157 "SampleAfterValue": "2000003", 158 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ", 159 "CounterHTOff": "0,1,2,3,4,5,6,7" 160 }, 161 { 162 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 163 "EventCode": "0xC9", 164 "Counter": "0,1,2,3", 165 "UMask": "0x8", 166 "EventName": "RTM_RETIRED.ABORTED_MEM", 167 "SampleAfterValue": "2000003", 168 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 169 "CounterHTOff": "0,1,2,3,4,5,6,7" 170 }, 171 { 172 "EventCode": "0xC9", 173 "Counter": "0,1,2,3", 174 "UMask": "0x10", 175 "EventName": "RTM_RETIRED.ABORTED_TIMER", 176 "SampleAfterValue": "2000003", 177 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 178 "CounterHTOff": "0,1,2,3,4,5,6,7" 179 }, 180 { 181 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 182 "EventCode": "0xC9", 183 "Counter": "0,1,2,3", 184 "UMask": "0x20", 185 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 186 "SampleAfterValue": "2000003", 187 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 188 "CounterHTOff": "0,1,2,3,4,5,6,7" 189 }, 190 { 191 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 192 "EventCode": "0xC9", 193 "Counter": "0,1,2,3", 194 "UMask": "0x40", 195 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 196 "SampleAfterValue": "2000003", 197 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 198 "CounterHTOff": "0,1,2,3,4,5,6,7" 199 }, 200 { 201 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 202 "EventCode": "0xC9", 203 "Counter": "0,1,2,3", 204 "UMask": "0x80", 205 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 206 "SampleAfterValue": "2000003", 207 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 208 "CounterHTOff": "0,1,2,3,4,5,6,7" 209 }, 210 { 211 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", 212 "EventCode": "0xC3", 213 "Counter": "0,1,2,3", 214 "UMask": "0x2", 215 "Errata": "SKL089", 216 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 217 "SampleAfterValue": "100003", 218 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 219 "CounterHTOff": "0,1,2,3,4,5,6,7" 220 }, 221 { 222 "PEBS": "2", 223 "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 224 "EventCode": "0xCD", 225 "MSRValue": "0x4", 226 "Counter": "0,1,2,3", 227 "UMask": "0x1", 228 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 229 "MSRIndex": "0x3F6", 230 "SampleAfterValue": "100003", 231 "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.", 232 "TakenAlone": "1", 233 "CounterHTOff": "0,1,2,3" 234 }, 235 { 236 "PEBS": "2", 237 "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 238 "EventCode": "0xCD", 239 "MSRValue": "0x8", 240 "Counter": "0,1,2,3", 241 "UMask": "0x1", 242 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 243 "MSRIndex": "0x3F6", 244 "SampleAfterValue": "50021", 245 "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.", 246 "TakenAlone": "1", 247 "CounterHTOff": "0,1,2,3" 248 }, 249 { 250 "PEBS": "2", 251 "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 252 "EventCode": "0xCD", 253 "MSRValue": "0x10", 254 "Counter": "0,1,2,3", 255 "UMask": "0x1", 256 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 257 "MSRIndex": "0x3F6", 258 "SampleAfterValue": "20011", 259 "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.", 260 "TakenAlone": "1", 261 "CounterHTOff": "0,1,2,3" 262 }, 263 { 264 "PEBS": "2", 265 "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 266 "EventCode": "0xCD", 267 "MSRValue": "0x20", 268 "Counter": "0,1,2,3", 269 "UMask": "0x1", 270 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 271 "MSRIndex": "0x3F6", 272 "SampleAfterValue": "100007", 273 "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.", 274 "TakenAlone": "1", 275 "CounterHTOff": "0,1,2,3" 276 }, 277 { 278 "PEBS": "2", 279 "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 280 "EventCode": "0xCD", 281 "MSRValue": "0x40", 282 "Counter": "0,1,2,3", 283 "UMask": "0x1", 284 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 285 "MSRIndex": "0x3F6", 286 "SampleAfterValue": "2003", 287 "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.", 288 "TakenAlone": "1", 289 "CounterHTOff": "0,1,2,3" 290 }, 291 { 292 "PEBS": "2", 293 "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 294 "EventCode": "0xCD", 295 "MSRValue": "0x80", 296 "Counter": "0,1,2,3", 297 "UMask": "0x1", 298 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 299 "MSRIndex": "0x3F6", 300 "SampleAfterValue": "1009", 301 "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.", 302 "TakenAlone": "1", 303 "CounterHTOff": "0,1,2,3" 304 }, 305 { 306 "PEBS": "2", 307 "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 308 "EventCode": "0xCD", 309 "MSRValue": "0x100", 310 "Counter": "0,1,2,3", 311 "UMask": "0x1", 312 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 313 "MSRIndex": "0x3F6", 314 "SampleAfterValue": "503", 315 "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.", 316 "TakenAlone": "1", 317 "CounterHTOff": "0,1,2,3" 318 }, 319 { 320 "PEBS": "2", 321 "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 322 "EventCode": "0xCD", 323 "MSRValue": "0x200", 324 "Counter": "0,1,2,3", 325 "UMask": "0x1", 326 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 327 "MSRIndex": "0x3F6", 328 "SampleAfterValue": "101", 329 "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.", 330 "TakenAlone": "1", 331 "CounterHTOff": "0,1,2,3" 332 }, 333 { 334 "PublicDescription": "Number of times a TSX line had a cache conflict.", 335 "EventCode": "0x54", 336 "Counter": "0,1,2,3", 337 "UMask": "0x1", 338 "EventName": "TX_MEM.ABORT_CONFLICT", 339 "SampleAfterValue": "2000003", 340 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 341 "CounterHTOff": "0,1,2,3,4,5,6,7" 342 }, 343 { 344 "EventCode": "0x54", 345 "Counter": "0,1,2,3", 346 "UMask": "0x2", 347 "EventName": "TX_MEM.ABORT_CAPACITY", 348 "SampleAfterValue": "2000003", 349 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 350 "CounterHTOff": "0,1,2,3,4,5,6,7" 351 }, 352 { 353 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 354 "EventCode": "0x54", 355 "Counter": "0,1,2,3", 356 "UMask": "0x4", 357 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 358 "SampleAfterValue": "2000003", 359 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 360 "CounterHTOff": "0,1,2,3,4,5,6,7" 361 }, 362 { 363 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 364 "EventCode": "0x54", 365 "Counter": "0,1,2,3", 366 "UMask": "0x8", 367 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 368 "SampleAfterValue": "2000003", 369 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 370 "CounterHTOff": "0,1,2,3,4,5,6,7" 371 }, 372 { 373 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 374 "EventCode": "0x54", 375 "Counter": "0,1,2,3", 376 "UMask": "0x10", 377 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 378 "SampleAfterValue": "2000003", 379 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 380 "CounterHTOff": "0,1,2,3,4,5,6,7" 381 }, 382 { 383 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 384 "EventCode": "0x54", 385 "Counter": "0,1,2,3", 386 "UMask": "0x20", 387 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 388 "SampleAfterValue": "2000003", 389 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 390 "CounterHTOff": "0,1,2,3,4,5,6,7" 391 }, 392 { 393 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 394 "EventCode": "0x54", 395 "Counter": "0,1,2,3", 396 "UMask": "0x40", 397 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 398 "SampleAfterValue": "2000003", 399 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 400 "CounterHTOff": "0,1,2,3,4,5,6,7" 401 }, 402 { 403 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 404 "EventCode": "0xB0", 405 "Counter": "0,1,2,3", 406 "UMask": "0x10", 407 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 408 "SampleAfterValue": "100003", 409 "BriefDescription": "Demand Data Read requests who miss L3 cache", 410 "CounterHTOff": "0,1,2,3,4,5,6,7" 411 }, 412 { 413 "EventCode": "0x60", 414 "Counter": "0,1,2,3", 415 "UMask": "0x10", 416 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 417 "SampleAfterValue": "2000003", 418 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 419 "CounterHTOff": "0,1,2,3,4,5,6,7" 420 }, 421 { 422 "EventCode": "0xA3", 423 "Counter": "0,1,2,3", 424 "UMask": "0x2", 425 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 426 "SampleAfterValue": "2000003", 427 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 428 "CounterMask": "2", 429 "CounterHTOff": "0,1,2,3,4,5,6,7" 430 }, 431 { 432 "EventCode": "0xA3", 433 "Counter": "0,1,2,3", 434 "UMask": "0x6", 435 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 436 "SampleAfterValue": "2000003", 437 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 438 "CounterMask": "6", 439 "CounterHTOff": "0,1,2,3,4,5,6,7" 440 }, 441 { 442 "EventCode": "0x60", 443 "Counter": "0,1,2,3", 444 "UMask": "0x10", 445 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 446 "SampleAfterValue": "2000003", 447 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 448 "CounterMask": "1", 449 "CounterHTOff": "0,1,2,3,4,5,6,7" 450 }, 451 { 452 "EventCode": "0x60", 453 "Counter": "0,1,2,3", 454 "UMask": "0x10", 455 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 456 "SampleAfterValue": "2000003", 457 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 458 "CounterMask": "6", 459 "CounterHTOff": "0,1,2,3,4,5,6,7" 460 }, 461 { 462 "EventCode": "0xB7, 0xBB", 463 "MSRValue": "0x3ffc008000 ", 464 "Counter": "0,1,2,3", 465 "UMask": "0x1", 466 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", 467 "MSRIndex": "0x1a6,0x1a7", 468 "SampleAfterValue": "100003", 469 "BriefDescription": "OTHER & L3_MISS & ANY_SNOOP", 470 "Offcore": "1", 471 "CounterHTOff": "0,1,2,3" 472 }, 473 { 474 "EventCode": "0xB7, 0xBB", 475 "MSRValue": "0x203c008000 ", 476 "Counter": "0,1,2,3", 477 "UMask": "0x1", 478 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", 479 "MSRIndex": "0x1a6,0x1a7", 480 "SampleAfterValue": "100003", 481 "BriefDescription": "OTHER & L3_MISS & SNOOP_NON_DRAM", 482 "Offcore": "1", 483 "CounterHTOff": "0,1,2,3" 484 }, 485 { 486 "EventCode": "0xB7, 0xBB", 487 "MSRValue": "0x103c008000 ", 488 "Counter": "0,1,2,3", 489 "UMask": "0x1", 490 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM", 491 "MSRIndex": "0x1a6,0x1a7", 492 "SampleAfterValue": "100003", 493 "BriefDescription": "OTHER & L3_MISS & SNOOP_HITM", 494 "Offcore": "1", 495 "CounterHTOff": "0,1,2,3" 496 }, 497 { 498 "EventCode": "0xB7, 0xBB", 499 "MSRValue": "0x043c008000 ", 500 "Counter": "0,1,2,3", 501 "UMask": "0x1", 502 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", 503 "MSRIndex": "0x1a6,0x1a7", 504 "SampleAfterValue": "100003", 505 "BriefDescription": "OTHER & L3_MISS & SNOOP_HIT_NO_FWD", 506 "Offcore": "1", 507 "CounterHTOff": "0,1,2,3" 508 }, 509 { 510 "EventCode": "0xB7, 0xBB", 511 "MSRValue": "0x023c008000 ", 512 "Counter": "0,1,2,3", 513 "UMask": "0x1", 514 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", 515 "MSRIndex": "0x1a6,0x1a7", 516 "SampleAfterValue": "100003", 517 "BriefDescription": "OTHER & L3_MISS & SNOOP_MISS", 518 "Offcore": "1", 519 "CounterHTOff": "0,1,2,3" 520 }, 521 { 522 "EventCode": "0xB7, 0xBB", 523 "MSRValue": "0x013c008000 ", 524 "Counter": "0,1,2,3", 525 "UMask": "0x1", 526 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", 527 "MSRIndex": "0x1a6,0x1a7", 528 "SampleAfterValue": "100003", 529 "BriefDescription": "OTHER & L3_MISS & SNOOP_NOT_NEEDED", 530 "Offcore": "1", 531 "CounterHTOff": "0,1,2,3" 532 }, 533 { 534 "EventCode": "0xB7, 0xBB", 535 "MSRValue": "0x00bc008000 ", 536 "Counter": "0,1,2,3", 537 "UMask": "0x1", 538 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", 539 "MSRIndex": "0x1a6,0x1a7", 540 "SampleAfterValue": "100003", 541 "BriefDescription": "OTHER & L3_MISS & SNOOP_NONE", 542 "Offcore": "1", 543 "CounterHTOff": "0,1,2,3" 544 }, 545 { 546 "EventCode": "0xB7, 0xBB", 547 "MSRValue": "0x007c008000 ", 548 "Counter": "0,1,2,3", 549 "UMask": "0x1", 550 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", 551 "MSRIndex": "0x1a6,0x1a7", 552 "SampleAfterValue": "100003", 553 "BriefDescription": "OTHER & L3_MISS & SPL_HIT", 554 "Offcore": "1", 555 "CounterHTOff": "0,1,2,3" 556 }, 557 { 558 "EventCode": "0xB7, 0xBB", 559 "MSRValue": "0x3fc4008000 ", 560 "Counter": "0,1,2,3", 561 "UMask": "0x1", 562 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 563 "MSRIndex": "0x1a6,0x1a7", 564 "SampleAfterValue": "100003", 565 "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & ANY_SNOOP", 566 "Offcore": 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"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NON_DRAM", 971 "MSRIndex": "0x1a6,0x1a7", 972 "SampleAfterValue": "100003", 973 "BriefDescription": "STREAMING_STORES & L3_HIT_M & SNOOP_NON_DRAM", 974 "Offcore": "1", 975 "CounterHTOff": "0,1,2,3" 976 }, 977 { 978 "EventCode": "0xB7, 0xBB", 979 "MSRValue": "0x2000020800 ", 980 "Counter": "0,1,2,3", 981 "UMask": "0x1", 982 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NON_DRAM", 983 "MSRIndex": "0x1a6,0x1a7", 984 "SampleAfterValue": "100003", 985 "BriefDescription": "STREAMING_STORES & SUPPLIER_NONE & SNOOP_NON_DRAM", 986 "Offcore": "1", 987 "CounterHTOff": "0,1,2,3" 988 }, 989 { 990 "EventCode": "0xB7, 0xBB", 991 "MSRValue": "0x3ffc000100 ", 992 "Counter": "0,1,2,3", 993 "UMask": "0x1", 994 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", 995 "MSRIndex": "0x1a6,0x1a7", 996 "SampleAfterValue": "100003", 997 "BriefDescription": "PF_L3_RFO & L3_MISS & ANY_SNOOP", 998 "Offcore": "1", 999 "CounterHTOff": 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"0x1a6,0x1a7", 1032 "SampleAfterValue": "100003", 1033 "BriefDescription": "PF_L3_RFO & L3_MISS & SNOOP_HIT_NO_FWD", 1034 "Offcore": "1", 1035 "CounterHTOff": "0,1,2,3" 1036 }, 1037 { 1038 "EventCode": "0xB7, 0xBB", 1039 "MSRValue": "0x023c000100 ", 1040 "Counter": "0,1,2,3", 1041 "UMask": "0x1", 1042 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", 1043 "MSRIndex": "0x1a6,0x1a7", 1044 "SampleAfterValue": "100003", 1045 "BriefDescription": "PF_L3_RFO & L3_MISS & SNOOP_MISS", 1046 "Offcore": "1", 1047 "CounterHTOff": "0,1,2,3" 1048 }, 1049 { 1050 "EventCode": "0xB7, 0xBB", 1051 "MSRValue": "0x013c000100 ", 1052 "Counter": "0,1,2,3", 1053 "UMask": "0x1", 1054 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", 1055 "MSRIndex": "0x1a6,0x1a7", 1056 "SampleAfterValue": "100003", 1057 "BriefDescription": "PF_L3_RFO & L3_MISS & SNOOP_NOT_NEEDED", 1058 "Offcore": "1", 1059 "CounterHTOff": "0,1,2,3" 1060 }, 1061 { 1062 "EventCode": "0xB7, 0xBB", 1063 "MSRValue": "0x00bc000100 ", 1064 "Counter": "0,1,2,3", 1065 "UMask": "0x1", 1066 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", 1067 "MSRIndex": "0x1a6,0x1a7", 1068 "SampleAfterValue": "100003", 1069 "BriefDescription": "PF_L3_RFO & L3_MISS & SNOOP_NONE", 1070 "Offcore": "1", 1071 "CounterHTOff": "0,1,2,3" 1072 }, 1073 { 1074 "EventCode": "0xB7, 0xBB", 1075 "MSRValue": "0x007c000100 ", 1076 "Counter": "0,1,2,3", 1077 "UMask": "0x1", 1078 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SPL_HIT", 1079 "MSRIndex": "0x1a6,0x1a7", 1080 "SampleAfterValue": "100003", 1081 "BriefDescription": "PF_L3_RFO & L3_MISS & SPL_HIT", 1082 "Offcore": "1", 1083 "CounterHTOff": "0,1,2,3" 1084 }, 1085 { 1086 "EventCode": "0xB7, 0xBB", 1087 "MSRValue": "0x3fc4000100 ", 1088 "Counter": "0,1,2,3", 1089 "UMask": "0x1", 1090 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1091 "MSRIndex": "0x1a6,0x1a7", 1092 "SampleAfterValue": "100003", 1093 "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP", 1094 "Offcore": "1", 1095 "CounterHTOff": "0,1,2,3" 1096 }, 1097 { 1098 "EventCode": "0xB7, 0xBB", 1099 "MSRValue": "0x2004000100 ", 1100 "Counter": "0,1,2,3", 1101 "UMask": "0x1", 1102 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1103 "MSRIndex": "0x1a6,0x1a7", 1104 "SampleAfterValue": "100003", 1105 "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", 1106 "Offcore": "1", 1107 "CounterHTOff": "0,1,2,3" 1108 }, 1109 { 1110 "EventCode": "0xB7, 0xBB", 1111 "MSRValue": "0x1004000100 ", 1112 "Counter": "0,1,2,3", 1113 "UMask": "0x1", 1114 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1115 "MSRIndex": "0x1a6,0x1a7", 1116 "SampleAfterValue": "100003", 1117 "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HITM", 1118 "Offcore": "1", 1119 "CounterHTOff": "0,1,2,3" 1120 }, 1121 { 1122 "EventCode": "0xB7, 0xBB", 1123 "MSRValue": "0x0404000100 ", 1124 "Counter": "0,1,2,3", 1125 "UMask": "0x1", 1126 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1127 "MSRIndex": "0x1a6,0x1a7", 1128 "SampleAfterValue": "100003", 1129 "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", 1130 "Offcore": "1", 1131 "CounterHTOff": "0,1,2,3" 1132 }, 1133 { 1134 "EventCode": "0xB7, 0xBB", 1135 "MSRValue": "0x0204000100 ", 1136 "Counter": "0,1,2,3", 1137 "UMask": "0x1", 1138 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1139 "MSRIndex": "0x1a6,0x1a7", 1140 "SampleAfterValue": "100003", 1141 "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS", 1142 "Offcore": "1", 1143 "CounterHTOff": "0,1,2,3" 1144 }, 1145 { 1146 "EventCode": "0xB7, 0xBB", 1147 "MSRValue": "0x0104000100 ", 1148 "Counter": "0,1,2,3", 1149 "UMask": "0x1", 1150 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1151 "MSRIndex": "0x1a6,0x1a7", 1152 "SampleAfterValue": "100003", 1153 "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", 1154 "Offcore": "1", 1155 "CounterHTOff": "0,1,2,3" 1156 }, 1157 { 1158 "EventCode": "0xB7, 0xBB", 1159 "MSRValue": "0x0084000100 ", 1160 "Counter": "0,1,2,3", 1161 "UMask": "0x1", 1162 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1163 "MSRIndex": "0x1a6,0x1a7", 1164 "SampleAfterValue": "100003", 1165 "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE", 1166 "Offcore": "1", 1167 "CounterHTOff": "0,1,2,3" 1168 }, 1169 { 1170 "EventCode": "0xB7, 0xBB", 1171 "MSRValue": "0x0044000100 ", 1172 "Counter": "0,1,2,3", 1173 "UMask": "0x1", 1174 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT", 1175 "MSRIndex": "0x1a6,0x1a7", 1176 "SampleAfterValue": "100003", 1177 "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SPL_HIT", 1178 "Offcore": "1", 1179 "CounterHTOff": "0,1,2,3" 1180 }, 1181 { 1182 "EventCode": "0xB7, 0xBB", 1183 "MSRValue": "0x2000400100 ", 1184 "Counter": "0,1,2,3", 1185 "UMask": "0x1", 1186 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 1187 "MSRIndex": "0x1a6,0x1a7", 1188 "SampleAfterValue": "100003", 1189 "BriefDescription": "PF_L3_RFO & L4_HIT_LOCAL_L4 & SNOOP_NON_DRAM", 1190 "Offcore": "1", 1191 "CounterHTOff": "0,1,2,3" 1192 }, 1193 { 1194 "EventCode": "0xB7, 0xBB", 1195 "MSRValue": "0x20001c0100 ", 1196 "Counter": "0,1,2,3", 1197 "UMask": "0x1", 1198 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM", 1199 "MSRIndex": "0x1a6,0x1a7", 1200 "SampleAfterValue": "100003", 1201 "BriefDescription": "PF_L3_RFO & L3_HIT & SNOOP_NON_DRAM", 1202 "Offcore": "1", 1203 "CounterHTOff": "0,1,2,3" 1204 }, 1205 { 1206 "EventCode": "0xB7, 0xBB", 1207 "MSRValue": "0x2000100100 ", 1208 "Counter": "0,1,2,3", 1209 "UMask": "0x1", 1210 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NON_DRAM", 1211 "MSRIndex": "0x1a6,0x1a7", 1212 "SampleAfterValue": "100003", 1213 "BriefDescription": "PF_L3_RFO & L3_HIT_S & SNOOP_NON_DRAM", 1214 "Offcore": "1", 1215 "CounterHTOff": "0,1,2,3" 1216 }, 1217 { 1218 "EventCode": "0xB7, 0xBB", 1219 "MSRValue": "0x2000080100 ", 1220 "Counter": "0,1,2,3", 1221 "UMask": "0x1", 1222 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NON_DRAM", 1223 "MSRIndex": "0x1a6,0x1a7", 1224 "SampleAfterValue": "100003", 1225 "BriefDescription": "PF_L3_RFO & L3_HIT_E & SNOOP_NON_DRAM", 1226 "Offcore": "1", 1227 "CounterHTOff": "0,1,2,3" 1228 }, 1229 { 1230 "EventCode": "0xB7, 0xBB", 1231 "MSRValue": "0x2000040100 ", 1232 "Counter": "0,1,2,3", 1233 "UMask": "0x1", 1234 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NON_DRAM", 1235 "MSRIndex": "0x1a6,0x1a7", 1236 "SampleAfterValue": "100003", 1237 "BriefDescription": "PF_L3_RFO & L3_HIT_M & SNOOP_NON_DRAM", 1238 "Offcore": "1", 1239 "CounterHTOff": "0,1,2,3" 1240 }, 1241 { 1242 "EventCode": "0xB7, 0xBB", 1243 "MSRValue": "0x2000020100 ", 1244 "Counter": "0,1,2,3", 1245 "UMask": "0x1", 1246 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 1247 "MSRIndex": "0x1a6,0x1a7", 1248 "SampleAfterValue": "100003", 1249 "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NON_DRAM", 1250 "Offcore": "1", 1251 "CounterHTOff": "0,1,2,3" 1252 }, 1253 { 1254 "EventCode": "0xB7, 0xBB", 1255 "MSRValue": "0x3ffc000080 ", 1256 "Counter": "0,1,2,3", 1257 "UMask": "0x1", 1258 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 1259 "MSRIndex": "0x1a6,0x1a7", 1260 "SampleAfterValue": "100003", 1261 "BriefDescription": "PF_L3_DATA_RD & L3_MISS & ANY_SNOOP", 1262 "Offcore": "1", 1263 "CounterHTOff": "0,1,2,3" 1264 }, 1265 { 1266 "EventCode": "0xB7, 0xBB", 1267 "MSRValue": "0x203c000080 ", 1268 "Counter": "0,1,2,3", 1269 "UMask": "0x1", 1270 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NON_DRAM", 1271 "MSRIndex": "0x1a6,0x1a7", 1272 "SampleAfterValue": "100003", 1273 "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_NON_DRAM", 1274 "Offcore": "1", 1275 "CounterHTOff": "0,1,2,3" 1276 }, 1277 { 1278 "EventCode": "0xB7, 0xBB", 1279 "MSRValue": "0x103c000080 ", 1280 "Counter": "0,1,2,3", 1281 "UMask": "0x1", 1282 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HITM", 1283 "MSRIndex": "0x1a6,0x1a7", 1284 "SampleAfterValue": "100003", 1285 "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_HITM", 1286 "Offcore": "1", 1287 "CounterHTOff": "0,1,2,3" 1288 }, 1289 { 1290 "EventCode": "0xB7, 0xBB", 1291 "MSRValue": "0x043c000080 ", 1292 "Counter": "0,1,2,3", 1293 "UMask": "0x1", 1294 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1295 "MSRIndex": "0x1a6,0x1a7", 1296 "SampleAfterValue": "100003", 1297 "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD", 1298 "Offcore": "1", 1299 "CounterHTOff": "0,1,2,3" 1300 }, 1301 { 1302 "EventCode": "0xB7, 0xBB", 1303 "MSRValue": "0x023c000080 ", 1304 "Counter": "0,1,2,3", 1305 "UMask": "0x1", 1306 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 1307 "MSRIndex": "0x1a6,0x1a7", 1308 "SampleAfterValue": "100003", 1309 "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_MISS", 1310 "Offcore": "1", 1311 "CounterHTOff": "0,1,2,3" 1312 }, 1313 { 1314 "EventCode": "0xB7, 0xBB", 1315 "MSRValue": "0x013c000080 ", 1316 "Counter": "0,1,2,3", 1317 "UMask": "0x1", 1318 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 1319 "MSRIndex": "0x1a6,0x1a7", 1320 "SampleAfterValue": "100003", 1321 "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED", 1322 "Offcore": "1", 1323 "CounterHTOff": "0,1,2,3" 1324 }, 1325 { 1326 "EventCode": "0xB7, 0xBB", 1327 "MSRValue": "0x00bc000080 ", 1328 "Counter": "0,1,2,3", 1329 "UMask": "0x1", 1330 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 1331 "MSRIndex": "0x1a6,0x1a7", 1332 "SampleAfterValue": "100003", 1333 "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_NONE", 1334 "Offcore": "1", 1335 "CounterHTOff": "0,1,2,3" 1336 }, 1337 { 1338 "EventCode": "0xB7, 0xBB", 1339 "MSRValue": "0x007c000080 ", 1340 "Counter": "0,1,2,3", 1341 "UMask": "0x1", 1342 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SPL_HIT", 1343 "MSRIndex": "0x1a6,0x1a7", 1344 "SampleAfterValue": "100003", 1345 "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SPL_HIT", 1346 "Offcore": "1", 1347 "CounterHTOff": "0,1,2,3" 1348 }, 1349 { 1350 "EventCode": "0xB7, 0xBB", 1351 "MSRValue": "0x3fc4000080 ", 1352 "Counter": "0,1,2,3", 1353 "UMask": "0x1", 1354 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1355 "MSRIndex": "0x1a6,0x1a7", 1356 "SampleAfterValue": "100003", 1357 "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", 1358 "Offcore": "1", 1359 "CounterHTOff": "0,1,2,3" 1360 }, 1361 { 1362 "EventCode": "0xB7, 0xBB", 1363 "MSRValue": "0x2004000080 ", 1364 "Counter": "0,1,2,3", 1365 "UMask": "0x1", 1366 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1367 "MSRIndex": "0x1a6,0x1a7", 1368 "SampleAfterValue": "100003", 1369 "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", 1370 "Offcore": "1", 1371 "CounterHTOff": "0,1,2,3" 1372 }, 1373 { 1374 "EventCode": "0xB7, 0xBB", 1375 "MSRValue": "0x1004000080 ", 1376 "Counter": "0,1,2,3", 1377 "UMask": "0x1", 1378 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1379 "MSRIndex": "0x1a6,0x1a7", 1380 "SampleAfterValue": "100003", 1381 "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", 1382 "Offcore": "1", 1383 "CounterHTOff": "0,1,2,3" 1384 }, 1385 { 1386 "EventCode": "0xB7, 0xBB", 1387 "MSRValue": "0x0404000080 ", 1388 "Counter": "0,1,2,3", 1389 "UMask": "0x1", 1390 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1391 "MSRIndex": "0x1a6,0x1a7", 1392 "SampleAfterValue": "100003", 1393 "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", 1394 "Offcore": "1", 1395 "CounterHTOff": "0,1,2,3" 1396 }, 1397 { 1398 "EventCode": "0xB7, 0xBB", 1399 "MSRValue": "0x0204000080 ", 1400 "Counter": "0,1,2,3", 1401 "UMask": "0x1", 1402 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1403 "MSRIndex": "0x1a6,0x1a7", 1404 "SampleAfterValue": "100003", 1405 "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", 1406 "Offcore": "1", 1407 "CounterHTOff": "0,1,2,3" 1408 }, 1409 { 1410 "EventCode": "0xB7, 0xBB", 1411 "MSRValue": "0x0104000080 ", 1412 "Counter": "0,1,2,3", 1413 "UMask": "0x1", 1414 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1415 "MSRIndex": "0x1a6,0x1a7", 1416 "SampleAfterValue": "100003", 1417 "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", 1418 "Offcore": "1", 1419 "CounterHTOff": "0,1,2,3" 1420 }, 1421 { 1422 "EventCode": "0xB7, 0xBB", 1423 "MSRValue": "0x0084000080 ", 1424 "Counter": "0,1,2,3", 1425 "UMask": "0x1", 1426 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1427 "MSRIndex": "0x1a6,0x1a7", 1428 "SampleAfterValue": "100003", 1429 "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", 1430 "Offcore": "1", 1431 "CounterHTOff": "0,1,2,3" 1432 }, 1433 { 1434 "EventCode": "0xB7, 0xBB", 1435 "MSRValue": "0x0044000080 ", 1436 "Counter": "0,1,2,3", 1437 "UMask": "0x1", 1438 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", 1439 "MSRIndex": "0x1a6,0x1a7", 1440 "SampleAfterValue": "100003", 1441 "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SPL_HIT", 1442 "Offcore": "1", 1443 "CounterHTOff": "0,1,2,3" 1444 }, 1445 { 1446 "EventCode": "0xB7, 0xBB", 1447 "MSRValue": "0x2000400080 ", 1448 "Counter": "0,1,2,3", 1449 "UMask": "0x1", 1450 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 1451 "MSRIndex": "0x1a6,0x1a7", 1452 "SampleAfterValue": "100003", 1453 "BriefDescription": "PF_L3_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NON_DRAM", 1454 "Offcore": "1", 1455 "CounterHTOff": "0,1,2,3" 1456 }, 1457 { 1458 "EventCode": "0xB7, 0xBB", 1459 "MSRValue": "0x20001c0080 ", 1460 "Counter": "0,1,2,3", 1461 "UMask": "0x1", 1462 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 1463 "MSRIndex": "0x1a6,0x1a7", 1464 "SampleAfterValue": "100003", 1465 "BriefDescription": "PF_L3_DATA_RD & L3_HIT & SNOOP_NON_DRAM", 1466 "Offcore": "1", 1467 "CounterHTOff": "0,1,2,3" 1468 }, 1469 { 1470 "EventCode": "0xB7, 0xBB", 1471 "MSRValue": "0x2000100080 ", 1472 "Counter": "0,1,2,3", 1473 "UMask": "0x1", 1474 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM", 1475 "MSRIndex": "0x1a6,0x1a7", 1476 "SampleAfterValue": "100003", 1477 "BriefDescription": "PF_L3_DATA_RD & L3_HIT_S & SNOOP_NON_DRAM", 1478 "Offcore": "1", 1479 "CounterHTOff": "0,1,2,3" 1480 }, 1481 { 1482 "EventCode": "0xB7, 0xBB", 1483 "MSRValue": "0x2000080080 ", 1484 "Counter": "0,1,2,3", 1485 "UMask": "0x1", 1486 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM", 1487 "MSRIndex": "0x1a6,0x1a7", 1488 "SampleAfterValue": "100003", 1489 "BriefDescription": "PF_L3_DATA_RD & L3_HIT_E & SNOOP_NON_DRAM", 1490 "Offcore": "1", 1491 "CounterHTOff": "0,1,2,3" 1492 }, 1493 { 1494 "EventCode": "0xB7, 0xBB", 1495 "MSRValue": "0x2000040080 ", 1496 "Counter": "0,1,2,3", 1497 "UMask": "0x1", 1498 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM", 1499 "MSRIndex": "0x1a6,0x1a7", 1500 "SampleAfterValue": "100003", 1501 "BriefDescription": "PF_L3_DATA_RD & L3_HIT_M & SNOOP_NON_DRAM", 1502 "Offcore": "1", 1503 "CounterHTOff": "0,1,2,3" 1504 }, 1505 { 1506 "EventCode": "0xB7, 0xBB", 1507 "MSRValue": "0x2000020080 ", 1508 "Counter": "0,1,2,3", 1509 "UMask": "0x1", 1510 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1511 "MSRIndex": "0x1a6,0x1a7", 1512 "SampleAfterValue": "100003", 1513 "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", 1514 "Offcore": "1", 1515 "CounterHTOff": "0,1,2,3" 1516 }, 1517 { 1518 "EventCode": "0xB7, 0xBB", 1519 "MSRValue": "0x3ffc000004 ", 1520 "Counter": "0,1,2,3", 1521 "UMask": "0x1", 1522 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 1523 "MSRIndex": "0x1a6,0x1a7", 1524 "SampleAfterValue": "100003", 1525 "BriefDescription": "DEMAND_CODE_RD & L3_MISS & ANY_SNOOP", 1526 "Offcore": "1", 1527 "CounterHTOff": "0,1,2,3" 1528 }, 1529 { 1530 "EventCode": "0xB7, 0xBB", 1531 "MSRValue": "0x203c000004 ", 1532 "Counter": "0,1,2,3", 1533 "UMask": "0x1", 1534 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM", 1535 "MSRIndex": "0x1a6,0x1a7", 1536 "SampleAfterValue": "100003", 1537 "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_NON_DRAM", 1538 "Offcore": "1", 1539 "CounterHTOff": "0,1,2,3" 1540 }, 1541 { 1542 "EventCode": "0xB7, 0xBB", 1543 "MSRValue": "0x103c000004 ", 1544 "Counter": "0,1,2,3", 1545 "UMask": "0x1", 1546 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", 1547 "MSRIndex": "0x1a6,0x1a7", 1548 "SampleAfterValue": "100003", 1549 "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_HITM", 1550 "Offcore": "1", 1551 "CounterHTOff": "0,1,2,3" 1552 }, 1553 { 1554 "EventCode": "0xB7, 0xBB", 1555 "MSRValue": "0x043c000004 ", 1556 "Counter": "0,1,2,3", 1557 "UMask": "0x1", 1558 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1559 "MSRIndex": "0x1a6,0x1a7", 1560 "SampleAfterValue": "100003", 1561 "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_HIT_NO_FWD", 1562 "Offcore": "1", 1563 "CounterHTOff": "0,1,2,3" 1564 }, 1565 { 1566 "EventCode": "0xB7, 0xBB", 1567 "MSRValue": "0x023c000004 ", 1568 "Counter": "0,1,2,3", 1569 "UMask": "0x1", 1570 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 1571 "MSRIndex": "0x1a6,0x1a7", 1572 "SampleAfterValue": "100003", 1573 "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_MISS", 1574 "Offcore": "1", 1575 "CounterHTOff": "0,1,2,3" 1576 }, 1577 { 1578 "EventCode": "0xB7, 0xBB", 1579 "MSRValue": "0x013c000004 ", 1580 "Counter": "0,1,2,3", 1581 "UMask": "0x1", 1582 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 1583 "MSRIndex": "0x1a6,0x1a7", 1584 "SampleAfterValue": "100003", 1585 "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_NOT_NEEDED", 1586 "Offcore": "1", 1587 "CounterHTOff": "0,1,2,3" 1588 }, 1589 { 1590 "EventCode": "0xB7, 0xBB", 1591 "MSRValue": "0x00bc000004 ", 1592 "Counter": "0,1,2,3", 1593 "UMask": "0x1", 1594 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 1595 "MSRIndex": "0x1a6,0x1a7", 1596 "SampleAfterValue": "100003", 1597 "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_NONE", 1598 "Offcore": "1", 1599 "CounterHTOff": "0,1,2,3" 1600 }, 1601 { 1602 "EventCode": "0xB7, 0xBB", 1603 "MSRValue": "0x007c000004 ", 1604 "Counter": "0,1,2,3", 1605 "UMask": "0x1", 1606 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", 1607 "MSRIndex": "0x1a6,0x1a7", 1608 "SampleAfterValue": "100003", 1609 "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SPL_HIT", 1610 "Offcore": "1", 1611 "CounterHTOff": "0,1,2,3" 1612 }, 1613 { 1614 "EventCode": "0xB7, 0xBB", 1615 "MSRValue": "0x3fc4000004 ", 1616 "Counter": "0,1,2,3", 1617 "UMask": "0x1", 1618 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1619 "MSRIndex": "0x1a6,0x1a7", 1620 "SampleAfterValue": "100003", 1621 "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", 1622 "Offcore": "1", 1623 "CounterHTOff": "0,1,2,3" 1624 }, 1625 { 1626 "EventCode": "0xB7, 0xBB", 1627 "MSRValue": "0x2004000004 ", 1628 "Counter": "0,1,2,3", 1629 "UMask": "0x1", 1630 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1631 "MSRIndex": "0x1a6,0x1a7", 1632 "SampleAfterValue": "100003", 1633 "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", 1634 "Offcore": "1", 1635 "CounterHTOff": "0,1,2,3" 1636 }, 1637 { 1638 "EventCode": "0xB7, 0xBB", 1639 "MSRValue": "0x1004000004 ", 1640 "Counter": "0,1,2,3", 1641 "UMask": "0x1", 1642 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1643 "MSRIndex": "0x1a6,0x1a7", 1644 "SampleAfterValue": "100003", 1645 "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", 1646 "Offcore": "1", 1647 "CounterHTOff": "0,1,2,3" 1648 }, 1649 { 1650 "EventCode": "0xB7, 0xBB", 1651 "MSRValue": "0x0404000004 ", 1652 "Counter": "0,1,2,3", 1653 "UMask": "0x1", 1654 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1655 "MSRIndex": "0x1a6,0x1a7", 1656 "SampleAfterValue": "100003", 1657 "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", 1658 "Offcore": "1", 1659 "CounterHTOff": "0,1,2,3" 1660 }, 1661 { 1662 "EventCode": "0xB7, 0xBB", 1663 "MSRValue": "0x0204000004 ", 1664 "Counter": "0,1,2,3", 1665 "UMask": "0x1", 1666 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1667 "MSRIndex": "0x1a6,0x1a7", 1668 "SampleAfterValue": "100003", 1669 "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", 1670 "Offcore": "1", 1671 "CounterHTOff": "0,1,2,3" 1672 }, 1673 { 1674 "EventCode": "0xB7, 0xBB", 1675 "MSRValue": "0x0104000004 ", 1676 "Counter": "0,1,2,3", 1677 "UMask": "0x1", 1678 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1679 "MSRIndex": "0x1a6,0x1a7", 1680 "SampleAfterValue": "100003", 1681 "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", 1682 "Offcore": "1", 1683 "CounterHTOff": "0,1,2,3" 1684 }, 1685 { 1686 "EventCode": "0xB7, 0xBB", 1687 "MSRValue": "0x0084000004 ", 1688 "Counter": "0,1,2,3", 1689 "UMask": "0x1", 1690 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1691 "MSRIndex": "0x1a6,0x1a7", 1692 "SampleAfterValue": "100003", 1693 "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", 1694 "Offcore": "1", 1695 "CounterHTOff": "0,1,2,3" 1696 }, 1697 { 1698 "EventCode": "0xB7, 0xBB", 1699 "MSRValue": "0x0044000004 ", 1700 "Counter": "0,1,2,3", 1701 "UMask": "0x1", 1702 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", 1703 "MSRIndex": "0x1a6,0x1a7", 1704 "SampleAfterValue": "100003", 1705 "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SPL_HIT", 1706 "Offcore": "1", 1707 "CounterHTOff": "0,1,2,3" 1708 }, 1709 { 1710 "EventCode": "0xB7, 0xBB", 1711 "MSRValue": "0x2000400004 ", 1712 "Counter": "0,1,2,3", 1713 "UMask": "0x1", 1714 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 1715 "MSRIndex": "0x1a6,0x1a7", 1716 "SampleAfterValue": "100003", 1717 "BriefDescription": "DEMAND_CODE_RD & L4_HIT_LOCAL_L4 & SNOOP_NON_DRAM", 1718 "Offcore": "1", 1719 "CounterHTOff": "0,1,2,3" 1720 }, 1721 { 1722 "EventCode": "0xB7, 0xBB", 1723 "MSRValue": "0x20001c0004 ", 1724 "Counter": "0,1,2,3", 1725 "UMask": "0x1", 1726 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 1727 "MSRIndex": "0x1a6,0x1a7", 1728 "SampleAfterValue": "100003", 1729 "BriefDescription": "DEMAND_CODE_RD & L3_HIT & SNOOP_NON_DRAM", 1730 "Offcore": "1", 1731 "CounterHTOff": "0,1,2,3" 1732 }, 1733 { 1734 "EventCode": "0xB7, 0xBB", 1735 "MSRValue": "0x2000100004 ", 1736 "Counter": "0,1,2,3", 1737 "UMask": "0x1", 1738 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM", 1739 "MSRIndex": "0x1a6,0x1a7", 1740 "SampleAfterValue": "100003", 1741 "BriefDescription": "DEMAND_CODE_RD & L3_HIT_S & SNOOP_NON_DRAM", 1742 "Offcore": "1", 1743 "CounterHTOff": "0,1,2,3" 1744 }, 1745 { 1746 "EventCode": "0xB7, 0xBB", 1747 "MSRValue": "0x2000080004 ", 1748 "Counter": "0,1,2,3", 1749 "UMask": "0x1", 1750 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM", 1751 "MSRIndex": "0x1a6,0x1a7", 1752 "SampleAfterValue": "100003", 1753 "BriefDescription": "DEMAND_CODE_RD & L3_HIT_E & SNOOP_NON_DRAM", 1754 "Offcore": "1", 1755 "CounterHTOff": "0,1,2,3" 1756 }, 1757 { 1758 "EventCode": "0xB7, 0xBB", 1759 "MSRValue": "0x2000040004 ", 1760 "Counter": "0,1,2,3", 1761 "UMask": "0x1", 1762 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM", 1763 "MSRIndex": "0x1a6,0x1a7", 1764 "SampleAfterValue": "100003", 1765 "BriefDescription": "DEMAND_CODE_RD & L3_HIT_M & SNOOP_NON_DRAM", 1766 "Offcore": "1", 1767 "CounterHTOff": "0,1,2,3" 1768 }, 1769 { 1770 "EventCode": "0xB7, 0xBB", 1771 "MSRValue": "0x2000020004 ", 1772 "Counter": "0,1,2,3", 1773 "UMask": "0x1", 1774 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1775 "MSRIndex": "0x1a6,0x1a7", 1776 "SampleAfterValue": "100003", 1777 "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", 1778 "Offcore": "1", 1779 "CounterHTOff": "0,1,2,3" 1780 }, 1781 { 1782 "EventCode": "0xB7, 0xBB", 1783 "MSRValue": "0x3ffc000002 ", 1784 "Counter": "0,1,2,3", 1785 "UMask": "0x1", 1786 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 1787 "MSRIndex": "0x1a6,0x1a7", 1788 "SampleAfterValue": "100003", 1789 "BriefDescription": "DEMAND_RFO & L3_MISS & ANY_SNOOP", 1790 "Offcore": "1", 1791 "CounterHTOff": "0,1,2,3" 1792 }, 1793 { 1794 "EventCode": "0xB7, 0xBB", 1795 "MSRValue": "0x203c000002 ", 1796 "Counter": "0,1,2,3", 1797 "UMask": "0x1", 1798 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM", 1799 "MSRIndex": "0x1a6,0x1a7", 1800 "SampleAfterValue": "100003", 1801 "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_NON_DRAM", 1802 "Offcore": "1", 1803 "CounterHTOff": "0,1,2,3" 1804 }, 1805 { 1806 "EventCode": "0xB7, 0xBB", 1807 "MSRValue": "0x103c000002 ", 1808 "Counter": "0,1,2,3", 1809 "UMask": "0x1", 1810 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM", 1811 "MSRIndex": "0x1a6,0x1a7", 1812 "SampleAfterValue": "100003", 1813 "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_HITM", 1814 "Offcore": "1", 1815 "CounterHTOff": "0,1,2,3" 1816 }, 1817 { 1818 "EventCode": "0xB7, 0xBB", 1819 "MSRValue": "0x043c000002 ", 1820 "Counter": "0,1,2,3", 1821 "UMask": "0x1", 1822 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 1823 "MSRIndex": "0x1a6,0x1a7", 1824 "SampleAfterValue": "100003", 1825 "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_HIT_NO_FWD", 1826 "Offcore": "1", 1827 "CounterHTOff": "0,1,2,3" 1828 }, 1829 { 1830 "EventCode": "0xB7, 0xBB", 1831 "MSRValue": "0x023c000002 ", 1832 "Counter": "0,1,2,3", 1833 "UMask": "0x1", 1834 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", 1835 "MSRIndex": "0x1a6,0x1a7", 1836 "SampleAfterValue": "100003", 1837 "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_MISS", 1838 "Offcore": "1", 1839 "CounterHTOff": "0,1,2,3" 1840 }, 1841 { 1842 "EventCode": "0xB7, 0xBB", 1843 "MSRValue": "0x013c000002 ", 1844 "Counter": "0,1,2,3", 1845 "UMask": "0x1", 1846 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED", 1847 "MSRIndex": "0x1a6,0x1a7", 1848 "SampleAfterValue": "100003", 1849 "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_NOT_NEEDED", 1850 "Offcore": "1", 1851 "CounterHTOff": "0,1,2,3" 1852 }, 1853 { 1854 "EventCode": "0xB7, 0xBB", 1855 "MSRValue": "0x00bc000002 ", 1856 "Counter": "0,1,2,3", 1857 "UMask": "0x1", 1858 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", 1859 "MSRIndex": "0x1a6,0x1a7", 1860 "SampleAfterValue": "100003", 1861 "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_NONE", 1862 "Offcore": "1", 1863 "CounterHTOff": "0,1,2,3" 1864 }, 1865 { 1866 "EventCode": "0xB7, 0xBB", 1867 "MSRValue": "0x007c000002 ", 1868 "Counter": "0,1,2,3", 1869 "UMask": "0x1", 1870 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT", 1871 "MSRIndex": "0x1a6,0x1a7", 1872 "SampleAfterValue": "100003", 1873 "BriefDescription": "DEMAND_RFO & L3_MISS & SPL_HIT", 1874 "Offcore": "1", 1875 "CounterHTOff": "0,1,2,3" 1876 }, 1877 { 1878 "EventCode": "0xB7, 0xBB", 1879 "MSRValue": "0x3fc4000002 ", 1880 "Counter": "0,1,2,3", 1881 "UMask": "0x1", 1882 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1883 "MSRIndex": "0x1a6,0x1a7", 1884 "SampleAfterValue": "100003", 1885 "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP", 1886 "Offcore": "1", 1887 "CounterHTOff": "0,1,2,3" 1888 }, 1889 { 1890 "EventCode": "0xB7, 0xBB", 1891 "MSRValue": "0x2004000002 ", 1892 "Counter": "0,1,2,3", 1893 "UMask": "0x1", 1894 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1895 "MSRIndex": "0x1a6,0x1a7", 1896 "SampleAfterValue": "100003", 1897 "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", 1898 "Offcore": "1", 1899 "CounterHTOff": "0,1,2,3" 1900 }, 1901 { 1902 "EventCode": "0xB7, 0xBB", 1903 "MSRValue": "0x1004000002 ", 1904 "Counter": "0,1,2,3", 1905 "UMask": "0x1", 1906 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1907 "MSRIndex": "0x1a6,0x1a7", 1908 "SampleAfterValue": "100003", 1909 "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HITM", 1910 "Offcore": "1", 1911 "CounterHTOff": "0,1,2,3" 1912 }, 1913 { 1914 "EventCode": "0xB7, 0xBB", 1915 "MSRValue": "0x0404000002 ", 1916 "Counter": "0,1,2,3", 1917 "UMask": "0x1", 1918 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1919 "MSRIndex": "0x1a6,0x1a7", 1920 "SampleAfterValue": "100003", 1921 "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", 1922 "Offcore": "1", 1923 "CounterHTOff": "0,1,2,3" 1924 }, 1925 { 1926 "EventCode": "0xB7, 0xBB", 1927 "MSRValue": "0x0204000002 ", 1928 "Counter": "0,1,2,3", 1929 "UMask": "0x1", 1930 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1931 "MSRIndex": "0x1a6,0x1a7", 1932 "SampleAfterValue": "100003", 1933 "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS", 1934 "Offcore": "1", 1935 "CounterHTOff": "0,1,2,3" 1936 }, 1937 { 1938 "EventCode": "0xB7, 0xBB", 1939 "MSRValue": "0x0104000002 ", 1940 "Counter": "0,1,2,3", 1941 "UMask": "0x1", 1942 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1943 "MSRIndex": "0x1a6,0x1a7", 1944 "SampleAfterValue": "100003", 1945 "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", 1946 "Offcore": "1", 1947 "CounterHTOff": "0,1,2,3" 1948 }, 1949 { 1950 "EventCode": "0xB7, 0xBB", 1951 "MSRValue": "0x0084000002 ", 1952 "Counter": "0,1,2,3", 1953 "UMask": "0x1", 1954 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1955 "MSRIndex": "0x1a6,0x1a7", 1956 "SampleAfterValue": "100003", 1957 "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE", 1958 "Offcore": "1", 1959 "CounterHTOff": "0,1,2,3" 1960 }, 1961 { 1962 "EventCode": "0xB7, 0xBB", 1963 "MSRValue": "0x0044000002 ", 1964 "Counter": "0,1,2,3", 1965 "UMask": "0x1", 1966 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT", 1967 "MSRIndex": "0x1a6,0x1a7", 1968 "SampleAfterValue": "100003", 1969 "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & SPL_HIT", 1970 "Offcore": "1", 1971 "CounterHTOff": "0,1,2,3" 1972 }, 1973 { 1974 "EventCode": "0xB7, 0xBB", 1975 "MSRValue": "0x2000400002 ", 1976 "Counter": "0,1,2,3", 1977 "UMask": "0x1", 1978 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 1979 "MSRIndex": "0x1a6,0x1a7", 1980 "SampleAfterValue": "100003", 1981 "BriefDescription": "DEMAND_RFO & L4_HIT_LOCAL_L4 & SNOOP_NON_DRAM", 1982 "Offcore": "1", 1983 "CounterHTOff": "0,1,2,3" 1984 }, 1985 { 1986 "EventCode": "0xB7, 0xBB", 1987 "MSRValue": "0x20001c0002 ", 1988 "Counter": "0,1,2,3", 1989 "UMask": "0x1", 1990 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", 1991 "MSRIndex": "0x1a6,0x1a7", 1992 "SampleAfterValue": "100003", 1993 "BriefDescription": "DEMAND_RFO & L3_HIT & SNOOP_NON_DRAM", 1994 "Offcore": "1", 1995 "CounterHTOff": "0,1,2,3" 1996 }, 1997 { 1998 "EventCode": "0xB7, 0xBB", 1999 "MSRValue": "0x2000100002 ", 2000 "Counter": "0,1,2,3", 2001 "UMask": "0x1", 2002 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM", 2003 "MSRIndex": "0x1a6,0x1a7", 2004 "SampleAfterValue": "100003", 2005 "BriefDescription": "DEMAND_RFO & L3_HIT_S & SNOOP_NON_DRAM", 2006 "Offcore": "1", 2007 "CounterHTOff": "0,1,2,3" 2008 }, 2009 { 2010 "EventCode": "0xB7, 0xBB", 2011 "MSRValue": "0x2000080002 ", 2012 "Counter": "0,1,2,3", 2013 "UMask": "0x1", 2014 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM", 2015 "MSRIndex": "0x1a6,0x1a7", 2016 "SampleAfterValue": "100003", 2017 "BriefDescription": "DEMAND_RFO & L3_HIT_E & SNOOP_NON_DRAM", 2018 "Offcore": "1", 2019 "CounterHTOff": "0,1,2,3" 2020 }, 2021 { 2022 "EventCode": "0xB7, 0xBB", 2023 "MSRValue": "0x2000040002 ", 2024 "Counter": "0,1,2,3", 2025 "UMask": "0x1", 2026 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM", 2027 "MSRIndex": "0x1a6,0x1a7", 2028 "SampleAfterValue": "100003", 2029 "BriefDescription": "DEMAND_RFO & L3_HIT_M & SNOOP_NON_DRAM", 2030 "Offcore": "1", 2031 "CounterHTOff": "0,1,2,3" 2032 }, 2033 { 2034 "EventCode": "0xB7, 0xBB", 2035 "MSRValue": "0x2000020002 ", 2036 "Counter": "0,1,2,3", 2037 "UMask": "0x1", 2038 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 2039 "MSRIndex": "0x1a6,0x1a7", 2040 "SampleAfterValue": "100003", 2041 "BriefDescription": "DEMAND_RFO & SUPPLIER_NONE & SNOOP_NON_DRAM", 2042 "Offcore": "1", 2043 "CounterHTOff": "0,1,2,3" 2044 }, 2045 { 2046 "EventCode": "0xB7, 0xBB", 2047 "MSRValue": "0x3ffc000001 ", 2048 "Counter": "0,1,2,3", 2049 "UMask": "0x1", 2050 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 2051 "MSRIndex": "0x1a6,0x1a7", 2052 "SampleAfterValue": "100003", 2053 "BriefDescription": "DEMAND_DATA_RD & L3_MISS & ANY_SNOOP", 2054 "Offcore": "1", 2055 "CounterHTOff": "0,1,2,3" 2056 }, 2057 { 2058 "EventCode": "0xB7, 0xBB", 2059 "MSRValue": "0x203c000001 ", 2060 "Counter": "0,1,2,3", 2061 "UMask": "0x1", 2062 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM", 2063 "MSRIndex": "0x1a6,0x1a7", 2064 "SampleAfterValue": "100003", 2065 "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NON_DRAM", 2066 "Offcore": "1", 2067 "CounterHTOff": "0,1,2,3" 2068 }, 2069 { 2070 "EventCode": "0xB7, 0xBB", 2071 "MSRValue": "0x103c000001 ", 2072 "Counter": "0,1,2,3", 2073 "UMask": "0x1", 2074 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", 2075 "MSRIndex": "0x1a6,0x1a7", 2076 "SampleAfterValue": "100003", 2077 "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HITM", 2078 "Offcore": "1", 2079 "CounterHTOff": "0,1,2,3" 2080 }, 2081 { 2082 "EventCode": "0xB7, 0xBB", 2083 "MSRValue": "0x043c000001 ", 2084 "Counter": "0,1,2,3", 2085 "UMask": "0x1", 2086 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 2087 "MSRIndex": "0x1a6,0x1a7", 2088 "SampleAfterValue": "100003", 2089 "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD", 2090 "Offcore": "1", 2091 "CounterHTOff": "0,1,2,3" 2092 }, 2093 { 2094 "EventCode": "0xB7, 0xBB", 2095 "MSRValue": "0x023c000001 ", 2096 "Counter": "0,1,2,3", 2097 "UMask": "0x1", 2098 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 2099 "MSRIndex": "0x1a6,0x1a7", 2100 "SampleAfterValue": "100003", 2101 "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_MISS", 2102 "Offcore": "1", 2103 "CounterHTOff": "0,1,2,3" 2104 }, 2105 { 2106 "EventCode": "0xB7, 0xBB", 2107 "MSRValue": "0x013c000001 ", 2108 "Counter": "0,1,2,3", 2109 "UMask": "0x1", 2110 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 2111 "MSRIndex": "0x1a6,0x1a7", 2112 "SampleAfterValue": "100003", 2113 "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED", 2114 "Offcore": "1", 2115 "CounterHTOff": "0,1,2,3" 2116 }, 2117 { 2118 "EventCode": "0xB7, 0xBB", 2119 "MSRValue": "0x00bc000001 ", 2120 "Counter": "0,1,2,3", 2121 "UMask": "0x1", 2122 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 2123 "MSRIndex": "0x1a6,0x1a7", 2124 "SampleAfterValue": "100003", 2125 "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NONE", 2126 "Offcore": "1", 2127 "CounterHTOff": "0,1,2,3" 2128 }, 2129 { 2130 "EventCode": "0xB7, 0xBB", 2131 "MSRValue": "0x007c000001 ", 2132 "Counter": "0,1,2,3", 2133 "UMask": "0x1", 2134 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT", 2135 "MSRIndex": "0x1a6,0x1a7", 2136 "SampleAfterValue": "100003", 2137 "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SPL_HIT", 2138 "Offcore": "1", 2139 "CounterHTOff": "0,1,2,3" 2140 }, 2141 { 2142 "EventCode": "0xB7, 0xBB", 2143 "MSRValue": "0x3fc4000001 ", 2144 "Counter": "0,1,2,3", 2145 "UMask": "0x1", 2146 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2147 "MSRIndex": "0x1a6,0x1a7", 2148 "SampleAfterValue": "100003", 2149 "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", 2150 "Offcore": "1", 2151 "CounterHTOff": "0,1,2,3" 2152 }, 2153 { 2154 "EventCode": "0xB7, 0xBB", 2155 "MSRValue": "0x2004000001 ", 2156 "Counter": "0,1,2,3", 2157 "UMask": "0x1", 2158 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 2159 "MSRIndex": "0x1a6,0x1a7", 2160 "SampleAfterValue": "100003", 2161 "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM", 2162 "Offcore": "1", 2163 "CounterHTOff": "0,1,2,3" 2164 }, 2165 { 2166 "EventCode": "0xB7, 0xBB", 2167 "MSRValue": "0x1004000001 ", 2168 "Counter": "0,1,2,3", 2169 "UMask": "0x1", 2170 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 2171 "MSRIndex": "0x1a6,0x1a7", 2172 "SampleAfterValue": "100003", 2173 "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", 2174 "Offcore": "1", 2175 "CounterHTOff": "0,1,2,3" 2176 }, 2177 { 2178 "EventCode": "0xB7, 0xBB", 2179 "MSRValue": "0x0404000001 ", 2180 "Counter": "0,1,2,3", 2181 "UMask": "0x1", 2182 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 2183 "MSRIndex": "0x1a6,0x1a7", 2184 "SampleAfterValue": "100003", 2185 "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", 2186 "Offcore": "1", 2187 "CounterHTOff": "0,1,2,3" 2188 }, 2189 { 2190 "EventCode": "0xB7, 0xBB", 2191 "MSRValue": "0x0204000001 ", 2192 "Counter": "0,1,2,3", 2193 "UMask": "0x1", 2194 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2195 "MSRIndex": "0x1a6,0x1a7", 2196 "SampleAfterValue": "100003", 2197 "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", 2198 "Offcore": "1", 2199 "CounterHTOff": "0,1,2,3" 2200 }, 2201 { 2202 "EventCode": "0xB7, 0xBB", 2203 "MSRValue": "0x0104000001 ", 2204 "Counter": "0,1,2,3", 2205 "UMask": "0x1", 2206 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 2207 "MSRIndex": "0x1a6,0x1a7", 2208 "SampleAfterValue": "100003", 2209 "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", 2210 "Offcore": "1", 2211 "CounterHTOff": "0,1,2,3" 2212 }, 2213 { 2214 "EventCode": "0xB7, 0xBB", 2215 "MSRValue": "0x0084000001 ", 2216 "Counter": "0,1,2,3", 2217 "UMask": "0x1", 2218 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2219 "MSRIndex": "0x1a6,0x1a7", 2220 "SampleAfterValue": "100003", 2221 "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", 2222 "Offcore": "1", 2223 "CounterHTOff": "0,1,2,3" 2224 }, 2225 { 2226 "EventCode": "0xB7, 0xBB", 2227 "MSRValue": "0x0044000001 ", 2228 "Counter": "0,1,2,3", 2229 "UMask": "0x1", 2230 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", 2231 "MSRIndex": "0x1a6,0x1a7", 2232 "SampleAfterValue": "100003", 2233 "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SPL_HIT", 2234 "Offcore": "1", 2235 "CounterHTOff": "0,1,2,3" 2236 }, 2237 { 2238 "EventCode": "0xB7, 0xBB", 2239 "MSRValue": "0x2000400001 ", 2240 "Counter": "0,1,2,3", 2241 "UMask": "0x1", 2242 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 2243 "MSRIndex": "0x1a6,0x1a7", 2244 "SampleAfterValue": "100003", 2245 "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NON_DRAM", 2246 "Offcore": "1", 2247 "CounterHTOff": "0,1,2,3" 2248 }, 2249 { 2250 "EventCode": "0xB7, 0xBB", 2251 "MSRValue": "0x20001c0001 ", 2252 "Counter": "0,1,2,3", 2253 "UMask": "0x1", 2254 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 2255 "MSRIndex": "0x1a6,0x1a7", 2256 "SampleAfterValue": "100003", 2257 "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_NON_DRAM", 2258 "Offcore": "1", 2259 "CounterHTOff": "0,1,2,3" 2260 }, 2261 { 2262 "EventCode": "0xB7, 0xBB", 2263 "MSRValue": "0x2000100001 ", 2264 "Counter": "0,1,2,3", 2265 "UMask": "0x1", 2266 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM", 2267 "MSRIndex": "0x1a6,0x1a7", 2268 "SampleAfterValue": "100003", 2269 "BriefDescription": "DEMAND_DATA_RD & L3_HIT_S & SNOOP_NON_DRAM", 2270 "Offcore": "1", 2271 "CounterHTOff": "0,1,2,3" 2272 }, 2273 { 2274 "EventCode": "0xB7, 0xBB", 2275 "MSRValue": "0x2000080001 ", 2276 "Counter": "0,1,2,3", 2277 "UMask": "0x1", 2278 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM", 2279 "MSRIndex": "0x1a6,0x1a7", 2280 "SampleAfterValue": "100003", 2281 "BriefDescription": "DEMAND_DATA_RD & L3_HIT_E & SNOOP_NON_DRAM", 2282 "Offcore": "1", 2283 "CounterHTOff": "0,1,2,3" 2284 }, 2285 { 2286 "EventCode": "0xB7, 0xBB", 2287 "MSRValue": "0x2000040001 ", 2288 "Counter": "0,1,2,3", 2289 "UMask": "0x1", 2290 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM", 2291 "MSRIndex": "0x1a6,0x1a7", 2292 "SampleAfterValue": "100003", 2293 "BriefDescription": "DEMAND_DATA_RD & L3_HIT_M & SNOOP_NON_DRAM", 2294 "Offcore": "1", 2295 "CounterHTOff": "0,1,2,3" 2296 }, 2297 { 2298 "EventCode": "0xB7, 0xBB", 2299 "MSRValue": "0x2000020001 ", 2300 "Counter": "0,1,2,3", 2301 "UMask": "0x1", 2302 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 2303 "MSRIndex": "0x1a6,0x1a7", 2304 "SampleAfterValue": "100003", 2305 "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM", 2306 "Offcore": "1", 2307 "CounterHTOff": "0,1,2,3" 2308 } 2309]