1[ 2 { 3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "CounterMask": "2", 7 "EventCode": "0xA3", 8 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x2" 11 }, 12 { 13 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "CounterMask": "6", 17 "EventCode": "0xA3", 18 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 19 "SampleAfterValue": "2000003", 20 "UMask": "0x6" 21 }, 22 { 23 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 24 "Counter": "0,1,2,3", 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "EventCode": "0xC8", 27 "EventName": "HLE_RETIRED.ABORTED", 28 "PEBS": "1", 29 "PublicDescription": "Number of times HLE abort was triggered.", 30 "SampleAfterValue": "2000003", 31 "UMask": "0x4" 32 }, 33 { 34 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 35 "Counter": "0,1,2,3", 36 "CounterHTOff": "0,1,2,3,4,5,6,7", 37 "EventCode": "0xC8", 38 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 39 "SampleAfterValue": "2000003", 40 "UMask": "0x80" 41 }, 42 { 43 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 44 "Counter": "0,1,2,3", 45 "CounterHTOff": "0,1,2,3,4,5,6,7", 46 "EventCode": "0xC8", 47 "EventName": "HLE_RETIRED.ABORTED_MEM", 48 "SampleAfterValue": "2000003", 49 "UMask": "0x8" 50 }, 51 { 52 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 53 "Counter": "0,1,2,3", 54 "CounterHTOff": "0,1,2,3,4,5,6,7", 55 "EventCode": "0xC8", 56 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 57 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 58 "SampleAfterValue": "2000003", 59 "UMask": "0x40" 60 }, 61 { 62 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 63 "Counter": "0,1,2,3", 64 "CounterHTOff": "0,1,2,3,4,5,6,7", 65 "EventCode": "0xC8", 66 "EventName": "HLE_RETIRED.ABORTED_TIMER", 67 "SampleAfterValue": "2000003", 68 "UMask": "0x10" 69 }, 70 { 71 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 72 "Counter": "0,1,2,3", 73 "CounterHTOff": "0,1,2,3,4,5,6,7", 74 "EventCode": "0xC8", 75 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 76 "SampleAfterValue": "2000003", 77 "UMask": "0x20" 78 }, 79 { 80 "BriefDescription": "Number of times an HLE execution successfully committed", 81 "Counter": "0,1,2,3", 82 "CounterHTOff": "0,1,2,3,4,5,6,7", 83 "EventCode": "0xC8", 84 "EventName": "HLE_RETIRED.COMMIT", 85 "PublicDescription": "Number of times HLE commit succeeded.", 86 "SampleAfterValue": "2000003", 87 "UMask": "0x2" 88 }, 89 { 90 "BriefDescription": "Number of times an HLE execution started.", 91 "Counter": "0,1,2,3", 92 "CounterHTOff": "0,1,2,3,4,5,6,7", 93 "EventCode": "0xC8", 94 "EventName": "HLE_RETIRED.START", 95 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 96 "SampleAfterValue": "2000003", 97 "UMask": "0x1" 98 }, 99 { 100 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 101 "Counter": "0,1,2,3", 102 "CounterHTOff": "0,1,2,3,4,5,6,7", 103 "Errata": "SKL089", 104 "EventCode": "0xC3", 105 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 106 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 107 "SampleAfterValue": "100003", 108 "UMask": "0x2" 109 }, 110 { 111 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 112 "Counter": "0,1,2,3", 113 "CounterHTOff": "0,1,2,3", 114 "Data_LA": "1", 115 "EventCode": "0xcd", 116 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 117 "MSRIndex": "0x3F6", 118 "MSRValue": "0x80", 119 "PEBS": "2", 120 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 121 "SampleAfterValue": "1009", 122 "TakenAlone": "1", 123 "UMask": "0x1" 124 }, 125 { 126 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 127 "Counter": "0,1,2,3", 128 "CounterHTOff": "0,1,2,3", 129 "Data_LA": "1", 130 "EventCode": "0xcd", 131 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 132 "MSRIndex": "0x3F6", 133 "MSRValue": "0x10", 134 "PEBS": "2", 135 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 136 "SampleAfterValue": "20011", 137 "TakenAlone": "1", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 142 "Counter": "0,1,2,3", 143 "CounterHTOff": "0,1,2,3", 144 "Data_LA": "1", 145 "EventCode": "0xcd", 146 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 147 "MSRIndex": "0x3F6", 148 "MSRValue": "0x100", 149 "PEBS": "2", 150 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 151 "SampleAfterValue": "503", 152 "TakenAlone": "1", 153 "UMask": "0x1" 154 }, 155 { 156 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 157 "Counter": "0,1,2,3", 158 "CounterHTOff": "0,1,2,3", 159 "Data_LA": "1", 160 "EventCode": "0xcd", 161 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 162 "MSRIndex": "0x3F6", 163 "MSRValue": "0x20", 164 "PEBS": "2", 165 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 166 "SampleAfterValue": "100007", 167 "TakenAlone": "1", 168 "UMask": "0x1" 169 }, 170 { 171 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 172 "Counter": "0,1,2,3", 173 "CounterHTOff": "0,1,2,3", 174 "Data_LA": "1", 175 "EventCode": "0xcd", 176 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 177 "MSRIndex": "0x3F6", 178 "MSRValue": "0x4", 179 "PEBS": "2", 180 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 181 "SampleAfterValue": "100003", 182 "TakenAlone": "1", 183 "UMask": "0x1" 184 }, 185 { 186 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 187 "Counter": "0,1,2,3", 188 "CounterHTOff": "0,1,2,3", 189 "Data_LA": "1", 190 "EventCode": "0xcd", 191 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 192 "MSRIndex": "0x3F6", 193 "MSRValue": "0x200", 194 "PEBS": "2", 195 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 196 "SampleAfterValue": "101", 197 "TakenAlone": "1", 198 "UMask": "0x1" 199 }, 200 { 201 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 202 "Counter": "0,1,2,3", 203 "CounterHTOff": "0,1,2,3", 204 "Data_LA": "1", 205 "EventCode": "0xcd", 206 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 207 "MSRIndex": "0x3F6", 208 "MSRValue": "0x40", 209 "PEBS": "2", 210 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 211 "SampleAfterValue": "2003", 212 "TakenAlone": "1", 213 "UMask": "0x1" 214 }, 215 { 216 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 217 "Counter": "0,1,2,3", 218 "CounterHTOff": "0,1,2,3", 219 "Data_LA": "1", 220 "EventCode": "0xcd", 221 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 222 "MSRIndex": "0x3F6", 223 "MSRValue": "0x8", 224 "PEBS": "2", 225 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 226 "SampleAfterValue": "50021", 227 "TakenAlone": "1", 228 "UMask": "0x1" 229 }, 230 { 231 "BriefDescription": "Demand Data Read requests who miss L3 cache", 232 "Counter": "0,1,2,3", 233 "CounterHTOff": "0,1,2,3,4,5,6,7", 234 "EventCode": "0xB0", 235 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 236 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 237 "SampleAfterValue": "100003", 238 "UMask": "0x10" 239 }, 240 { 241 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 242 "Counter": "0,1,2,3", 243 "CounterHTOff": "0,1,2,3,4,5,6,7", 244 "CounterMask": "1", 245 "EventCode": "0x60", 246 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 247 "SampleAfterValue": "2000003", 248 "UMask": "0x10" 249 }, 250 { 251 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 252 "Counter": "0,1,2,3", 253 "CounterHTOff": "0,1,2,3,4,5,6,7", 254 "EventCode": "0x60", 255 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 256 "SampleAfterValue": "2000003", 257 "UMask": "0x10" 258 }, 259 { 260 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 261 "Counter": "0,1,2,3", 262 "CounterHTOff": "0,1,2,3,4,5,6,7", 263 "CounterMask": "6", 264 "EventCode": "0x60", 265 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 266 "SampleAfterValue": "2000003", 267 "UMask": "0x10" 268 }, 269 { 270 "BriefDescription": "Counts all demand code reads", 271 "Counter": "0,1,2,3", 272 "CounterHTOff": "0,1,2,3", 273 "EventCode": "0xB7, 0xBB", 274 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 275 "MSRIndex": "0x1a6,0x1a7", 276 "MSRValue": "0x20001C0004", 277 "Offcore": "1", 278 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 279 "SampleAfterValue": "100003", 280 "UMask": "0x1" 281 }, 282 { 283 "BriefDescription": "Counts all demand code reads", 284 "Counter": "0,1,2,3", 285 "CounterHTOff": "0,1,2,3", 286 "EventCode": "0xB7, 0xBB", 287 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM", 288 "MSRIndex": "0x1a6,0x1a7", 289 "MSRValue": "0x2000080004", 290 "Offcore": "1", 291 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 292 "SampleAfterValue": "100003", 293 "UMask": "0x1" 294 }, 295 { 296 "BriefDescription": "Counts all demand code reads", 297 "Counter": "0,1,2,3", 298 "CounterHTOff": "0,1,2,3", 299 "EventCode": "0xB7, 0xBB", 300 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM", 301 "MSRIndex": "0x1a6,0x1a7", 302 "MSRValue": "0x2000040004", 303 "Offcore": "1", 304 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 305 "SampleAfterValue": "100003", 306 "UMask": "0x1" 307 }, 308 { 309 "BriefDescription": "Counts all demand code reads", 310 "Counter": "0,1,2,3", 311 "CounterHTOff": "0,1,2,3", 312 "EventCode": "0xB7, 0xBB", 313 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM", 314 "MSRIndex": "0x1a6,0x1a7", 315 "MSRValue": "0x2000100004", 316 "Offcore": "1", 317 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 318 "SampleAfterValue": "100003", 319 "UMask": "0x1" 320 }, 321 { 322 "BriefDescription": "Counts all demand code reads", 323 "Counter": "0,1,2,3", 324 "CounterHTOff": "0,1,2,3", 325 "EventCode": "0xB7, 0xBB", 326 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 327 "MSRIndex": "0x1a6,0x1a7", 328 "MSRValue": "0x3FFC400004", 329 "Offcore": "1", 330 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 331 "SampleAfterValue": "100003", 332 "UMask": "0x1" 333 }, 334 { 335 "BriefDescription": "Counts all demand code reads", 336 "Counter": "0,1,2,3", 337 "CounterHTOff": "0,1,2,3", 338 "EventCode": "0xB7, 0xBB", 339 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", 340 "MSRIndex": "0x1a6,0x1a7", 341 "MSRValue": "0x103C400004", 342 "Offcore": "1", 343 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 344 "SampleAfterValue": "100003", 345 "UMask": "0x1" 346 }, 347 { 348 "BriefDescription": "Counts all demand code reads", 349 "Counter": "0,1,2,3", 350 "CounterHTOff": "0,1,2,3", 351 "EventCode": "0xB7, 0xBB", 352 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 353 "MSRIndex": "0x1a6,0x1a7", 354 "MSRValue": "0x43C400004", 355 "Offcore": "1", 356 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 357 "SampleAfterValue": "100003", 358 "UMask": "0x1" 359 }, 360 { 361 "BriefDescription": "Counts all demand code reads", 362 "Counter": "0,1,2,3", 363 "CounterHTOff": "0,1,2,3", 364 "EventCode": "0xB7, 0xBB", 365 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 366 "MSRIndex": "0x1a6,0x1a7", 367 "MSRValue": "0x23C400004", 368 "Offcore": "1", 369 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 370 "SampleAfterValue": "100003", 371 "UMask": "0x1" 372 }, 373 { 374 "BriefDescription": "Counts all demand code reads", 375 "Counter": "0,1,2,3", 376 "CounterHTOff": "0,1,2,3", 377 "EventCode": "0xB7, 0xBB", 378 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 379 "MSRIndex": "0x1a6,0x1a7", 380 "MSRValue": "0xBC400004", 381 "Offcore": "1", 382 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 383 "SampleAfterValue": "100003", 384 "UMask": "0x1" 385 }, 386 { 387 "BriefDescription": "Counts all demand code reads", 388 "Counter": "0,1,2,3", 389 "CounterHTOff": "0,1,2,3", 390 "EventCode": "0xB7, 0xBB", 391 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM", 392 "MSRIndex": "0x1a6,0x1a7", 393 "MSRValue": "0x203C400004", 394 "Offcore": "1", 395 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 396 "SampleAfterValue": "100003", 397 "UMask": "0x1" 398 }, 399 { 400 "BriefDescription": "Counts all demand code reads", 401 "Counter": "0,1,2,3", 402 "CounterHTOff": "0,1,2,3", 403 "EventCode": "0xB7, 0xBB", 404 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 405 "MSRIndex": "0x1a6,0x1a7", 406 "MSRValue": "0x13C400004", 407 "Offcore": "1", 408 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 409 "SampleAfterValue": "100003", 410 "UMask": "0x1" 411 }, 412 { 413 "BriefDescription": "Counts all demand code reads", 414 "Counter": "0,1,2,3", 415 "CounterHTOff": "0,1,2,3", 416 "EventCode": "0xB7, 0xBB", 417 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", 418 "MSRIndex": "0x1a6,0x1a7", 419 "MSRValue": "0x7C400004", 420 "Offcore": "1", 421 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 422 "SampleAfterValue": "100003", 423 "UMask": "0x1" 424 }, 425 { 426 "BriefDescription": "Counts all demand code reads", 427 "Counter": "0,1,2,3", 428 "CounterHTOff": "0,1,2,3", 429 "EventCode": "0xB7, 0xBB", 430 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 431 "MSRIndex": "0x1a6,0x1a7", 432 "MSRValue": "0x3FC4000004", 433 "Offcore": "1", 434 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 435 "SampleAfterValue": "100003", 436 "UMask": "0x1" 437 }, 438 { 439 "BriefDescription": "Counts all demand code reads", 440 "Counter": "0,1,2,3", 441 "CounterHTOff": "0,1,2,3", 442 "EventCode": "0xB7, 0xBB", 443 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 444 "MSRIndex": "0x1a6,0x1a7", 445 "MSRValue": "0x1004000004", 446 "Offcore": "1", 447 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 448 "SampleAfterValue": "100003", 449 "UMask": "0x1" 450 }, 451 { 452 "BriefDescription": "Counts all demand code reads", 453 "Counter": "0,1,2,3", 454 "CounterHTOff": "0,1,2,3", 455 "EventCode": "0xB7, 0xBB", 456 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 457 "MSRIndex": "0x1a6,0x1a7", 458 "MSRValue": "0x404000004", 459 "Offcore": "1", 460 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 461 "SampleAfterValue": "100003", 462 "UMask": "0x1" 463 }, 464 { 465 "BriefDescription": "Counts all demand code reads", 466 "Counter": "0,1,2,3", 467 "CounterHTOff": "0,1,2,3", 468 "EventCode": "0xB7, 0xBB", 469 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 470 "MSRIndex": "0x1a6,0x1a7", 471 "MSRValue": "0x204000004", 472 "Offcore": "1", 473 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 474 "SampleAfterValue": "100003", 475 "UMask": "0x1" 476 }, 477 { 478 "BriefDescription": "Counts all demand code reads", 479 "Counter": "0,1,2,3", 480 "CounterHTOff": "0,1,2,3", 481 "EventCode": "0xB7, 0xBB", 482 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 483 "MSRIndex": "0x1a6,0x1a7", 484 "MSRValue": "0x84000004", 485 "Offcore": "1", 486 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 487 "SampleAfterValue": "100003", 488 "UMask": "0x1" 489 }, 490 { 491 "BriefDescription": "Counts all demand code reads", 492 "Counter": "0,1,2,3", 493 "CounterHTOff": "0,1,2,3", 494 "EventCode": "0xB7, 0xBB", 495 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 496 "MSRIndex": "0x1a6,0x1a7", 497 "MSRValue": "0x2004000004", 498 "Offcore": "1", 499 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 500 "SampleAfterValue": "100003", 501 "UMask": "0x1" 502 }, 503 { 504 "BriefDescription": "Counts all demand code reads", 505 "Counter": "0,1,2,3", 506 "CounterHTOff": "0,1,2,3", 507 "EventCode": "0xB7, 0xBB", 508 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 509 "MSRIndex": "0x1a6,0x1a7", 510 "MSRValue": "0x104000004", 511 "Offcore": "1", 512 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 513 "SampleAfterValue": "100003", 514 "UMask": "0x1" 515 }, 516 { 517 "BriefDescription": "Counts all demand code reads", 518 "Counter": "0,1,2,3", 519 "CounterHTOff": "0,1,2,3", 520 "EventCode": "0xB7, 0xBB", 521 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", 522 "MSRIndex": "0x1a6,0x1a7", 523 "MSRValue": "0x44000004", 524 "Offcore": "1", 525 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 526 "SampleAfterValue": "100003", 527 "UMask": "0x1" 528 }, 529 { 530 "BriefDescription": "Counts all demand code reads", 531 "Counter": "0,1,2,3", 532 "CounterHTOff": "0,1,2,3", 533 "EventCode": "0xB7, 0xBB", 534 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 535 "MSRIndex": "0x1a6,0x1a7", 536 "MSRValue": "0x2000400004", 537 "Offcore": "1", 538 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 539 "SampleAfterValue": "100003", 540 "UMask": "0x1" 541 }, 542 { 543 "BriefDescription": "Counts all demand code reads", 544 "Counter": "0,1,2,3", 545 "CounterHTOff": "0,1,2,3", 546 "EventCode": "0xB7, 0xBB", 547 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 548 "MSRIndex": "0x1a6,0x1a7", 549 "MSRValue": "0x2000020004", 550 "Offcore": "1", 551 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 552 "SampleAfterValue": "100003", 553 "UMask": "0x1" 554 }, 555 { 556 "BriefDescription": "Counts demand data reads", 557 "Counter": "0,1,2,3", 558 "CounterHTOff": "0,1,2,3", 559 "EventCode": "0xB7, 0xBB", 560 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 561 "MSRIndex": "0x1a6,0x1a7", 562 "MSRValue": "0x20001C0001", 563 "Offcore": "1", 564 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 565 "SampleAfterValue": "100003", 566 "UMask": "0x1" 567 }, 568 { 569 "BriefDescription": "Counts demand data reads", 570 "Counter": "0,1,2,3", 571 "CounterHTOff": "0,1,2,3", 572 "EventCode": "0xB7, 0xBB", 573 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM", 574 "MSRIndex": "0x1a6,0x1a7", 575 "MSRValue": "0x2000080001", 576 "Offcore": "1", 577 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 578 "SampleAfterValue": "100003", 579 "UMask": "0x1" 580 }, 581 { 582 "BriefDescription": "Counts demand data reads", 583 "Counter": "0,1,2,3", 584 "CounterHTOff": "0,1,2,3", 585 "EventCode": "0xB7, 0xBB", 586 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM", 587 "MSRIndex": "0x1a6,0x1a7", 588 "MSRValue": "0x2000040001", 589 "Offcore": "1", 590 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 591 "SampleAfterValue": "100003", 592 "UMask": "0x1" 593 }, 594 { 595 "BriefDescription": "Counts demand data reads", 596 "Counter": "0,1,2,3", 597 "CounterHTOff": "0,1,2,3", 598 "EventCode": "0xB7, 0xBB", 599 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM", 600 "MSRIndex": "0x1a6,0x1a7", 601 "MSRValue": "0x2000100001", 602 "Offcore": "1", 603 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 604 "SampleAfterValue": "100003", 605 "UMask": "0x1" 606 }, 607 { 608 "BriefDescription": "Counts demand data reads", 609 "Counter": "0,1,2,3", 610 "CounterHTOff": "0,1,2,3", 611 "EventCode": "0xB7, 0xBB", 612 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 613 "MSRIndex": "0x1a6,0x1a7", 614 "MSRValue": "0x3FFC400001", 615 "Offcore": "1", 616 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 617 "SampleAfterValue": "100003", 618 "UMask": "0x1" 619 }, 620 { 621 "BriefDescription": "Counts demand data reads", 622 "Counter": "0,1,2,3", 623 "CounterHTOff": "0,1,2,3", 624 "EventCode": "0xB7, 0xBB", 625 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", 626 "MSRIndex": "0x1a6,0x1a7", 627 "MSRValue": "0x103C400001", 628 "Offcore": "1", 629 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 630 "SampleAfterValue": "100003", 631 "UMask": "0x1" 632 }, 633 { 634 "BriefDescription": "Counts demand data reads", 635 "Counter": "0,1,2,3", 636 "CounterHTOff": "0,1,2,3", 637 "EventCode": "0xB7, 0xBB", 638 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 639 "MSRIndex": "0x1a6,0x1a7", 640 "MSRValue": "0x43C400001", 641 "Offcore": "1", 642 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 643 "SampleAfterValue": "100003", 644 "UMask": "0x1" 645 }, 646 { 647 "BriefDescription": "Counts demand data reads", 648 "Counter": "0,1,2,3", 649 "CounterHTOff": "0,1,2,3", 650 "EventCode": "0xB7, 0xBB", 651 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 652 "MSRIndex": "0x1a6,0x1a7", 653 "MSRValue": "0x23C400001", 654 "Offcore": "1", 655 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 656 "SampleAfterValue": "100003", 657 "UMask": "0x1" 658 }, 659 { 660 "BriefDescription": "Counts demand data reads", 661 "Counter": "0,1,2,3", 662 "CounterHTOff": "0,1,2,3", 663 "EventCode": "0xB7, 0xBB", 664 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 665 "MSRIndex": "0x1a6,0x1a7", 666 "MSRValue": "0xBC400001", 667 "Offcore": "1", 668 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 669 "SampleAfterValue": "100003", 670 "UMask": "0x1" 671 }, 672 { 673 "BriefDescription": "Counts demand data reads", 674 "Counter": "0,1,2,3", 675 "CounterHTOff": "0,1,2,3", 676 "EventCode": "0xB7, 0xBB", 677 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM", 678 "MSRIndex": "0x1a6,0x1a7", 679 "MSRValue": "0x203C400001", 680 "Offcore": "1", 681 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 682 "SampleAfterValue": "100003", 683 "UMask": "0x1" 684 }, 685 { 686 "BriefDescription": "Counts demand data reads", 687 "Counter": "0,1,2,3", 688 "CounterHTOff": "0,1,2,3", 689 "EventCode": "0xB7, 0xBB", 690 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 691 "MSRIndex": "0x1a6,0x1a7", 692 "MSRValue": "0x13C400001", 693 "Offcore": "1", 694 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 695 "SampleAfterValue": "100003", 696 "UMask": "0x1" 697 }, 698 { 699 "BriefDescription": "Counts demand data reads", 700 "Counter": "0,1,2,3", 701 "CounterHTOff": "0,1,2,3", 702 "EventCode": "0xB7, 0xBB", 703 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT", 704 "MSRIndex": "0x1a6,0x1a7", 705 "MSRValue": "0x7C400001", 706 "Offcore": "1", 707 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 708 "SampleAfterValue": "100003", 709 "UMask": "0x1" 710 }, 711 { 712 "BriefDescription": "Counts demand data reads", 713 "Counter": "0,1,2,3", 714 "CounterHTOff": "0,1,2,3", 715 "EventCode": "0xB7, 0xBB", 716 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 717 "MSRIndex": "0x1a6,0x1a7", 718 "MSRValue": "0x3FC4000001", 719 "Offcore": "1", 720 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 721 "SampleAfterValue": "100003", 722 "UMask": "0x1" 723 }, 724 { 725 "BriefDescription": "Counts demand data reads", 726 "Counter": "0,1,2,3", 727 "CounterHTOff": "0,1,2,3", 728 "EventCode": "0xB7, 0xBB", 729 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 730 "MSRIndex": "0x1a6,0x1a7", 731 "MSRValue": "0x1004000001", 732 "Offcore": "1", 733 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 734 "SampleAfterValue": "100003", 735 "UMask": "0x1" 736 }, 737 { 738 "BriefDescription": "Counts demand data reads", 739 "Counter": "0,1,2,3", 740 "CounterHTOff": "0,1,2,3", 741 "EventCode": "0xB7, 0xBB", 742 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 743 "MSRIndex": "0x1a6,0x1a7", 744 "MSRValue": "0x404000001", 745 "Offcore": "1", 746 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 747 "SampleAfterValue": "100003", 748 "UMask": "0x1" 749 }, 750 { 751 "BriefDescription": "Counts demand data reads", 752 "Counter": "0,1,2,3", 753 "CounterHTOff": "0,1,2,3", 754 "EventCode": "0xB7, 0xBB", 755 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 756 "MSRIndex": "0x1a6,0x1a7", 757 "MSRValue": "0x204000001", 758 "Offcore": "1", 759 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 760 "SampleAfterValue": "100003", 761 "UMask": "0x1" 762 }, 763 { 764 "BriefDescription": "Counts demand data reads", 765 "Counter": "0,1,2,3", 766 "CounterHTOff": "0,1,2,3", 767 "EventCode": "0xB7, 0xBB", 768 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 769 "MSRIndex": "0x1a6,0x1a7", 770 "MSRValue": "0x84000001", 771 "Offcore": "1", 772 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 773 "SampleAfterValue": "100003", 774 "UMask": "0x1" 775 }, 776 { 777 "BriefDescription": "Counts demand data reads", 778 "Counter": "0,1,2,3", 779 "CounterHTOff": "0,1,2,3", 780 "EventCode": "0xB7, 0xBB", 781 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 782 "MSRIndex": "0x1a6,0x1a7", 783 "MSRValue": "0x2004000001", 784 "Offcore": "1", 785 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 786 "SampleAfterValue": "100003", 787 "UMask": "0x1" 788 }, 789 { 790 "BriefDescription": "Counts demand data reads", 791 "Counter": "0,1,2,3", 792 "CounterHTOff": "0,1,2,3", 793 "EventCode": "0xB7, 0xBB", 794 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 795 "MSRIndex": "0x1a6,0x1a7", 796 "MSRValue": "0x104000001", 797 "Offcore": "1", 798 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 799 "SampleAfterValue": "100003", 800 "UMask": "0x1" 801 }, 802 { 803 "BriefDescription": "Counts demand data reads", 804 "Counter": "0,1,2,3", 805 "CounterHTOff": "0,1,2,3", 806 "EventCode": "0xB7, 0xBB", 807 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", 808 "MSRIndex": "0x1a6,0x1a7", 809 "MSRValue": "0x44000001", 810 "Offcore": "1", 811 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 812 "SampleAfterValue": "100003", 813 "UMask": "0x1" 814 }, 815 { 816 "BriefDescription": "Counts demand data reads", 817 "Counter": "0,1,2,3", 818 "CounterHTOff": "0,1,2,3", 819 "EventCode": "0xB7, 0xBB", 820 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 821 "MSRIndex": "0x1a6,0x1a7", 822 "MSRValue": "0x2000400001", 823 "Offcore": "1", 824 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 825 "SampleAfterValue": "100003", 826 "UMask": "0x1" 827 }, 828 { 829 "BriefDescription": "Counts demand data reads", 830 "Counter": "0,1,2,3", 831 "CounterHTOff": "0,1,2,3", 832 "EventCode": "0xB7, 0xBB", 833 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 834 "MSRIndex": "0x1a6,0x1a7", 835 "MSRValue": "0x2000020001", 836 "Offcore": "1", 837 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 838 "SampleAfterValue": "100003", 839 "UMask": "0x1" 840 }, 841 { 842 "BriefDescription": "Counts all demand data writes (RFOs)", 843 "Counter": "0,1,2,3", 844 "CounterHTOff": "0,1,2,3", 845 "EventCode": "0xB7, 0xBB", 846 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", 847 "MSRIndex": "0x1a6,0x1a7", 848 "MSRValue": "0x20001C0002", 849 "Offcore": "1", 850 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 851 "SampleAfterValue": "100003", 852 "UMask": "0x1" 853 }, 854 { 855 "BriefDescription": "Counts all demand data writes (RFOs)", 856 "Counter": "0,1,2,3", 857 "CounterHTOff": "0,1,2,3", 858 "EventCode": "0xB7, 0xBB", 859 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM", 860 "MSRIndex": "0x1a6,0x1a7", 861 "MSRValue": "0x2000080002", 862 "Offcore": "1", 863 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 864 "SampleAfterValue": "100003", 865 "UMask": "0x1" 866 }, 867 { 868 "BriefDescription": "Counts all demand data writes (RFOs)", 869 "Counter": "0,1,2,3", 870 "CounterHTOff": "0,1,2,3", 871 "EventCode": "0xB7, 0xBB", 872 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM", 873 "MSRIndex": "0x1a6,0x1a7", 874 "MSRValue": "0x2000040002", 875 "Offcore": "1", 876 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 877 "SampleAfterValue": "100003", 878 "UMask": "0x1" 879 }, 880 { 881 "BriefDescription": "Counts all demand data writes (RFOs)", 882 "Counter": "0,1,2,3", 883 "CounterHTOff": "0,1,2,3", 884 "EventCode": "0xB7, 0xBB", 885 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM", 886 "MSRIndex": "0x1a6,0x1a7", 887 "MSRValue": "0x2000100002", 888 "Offcore": "1", 889 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 890 "SampleAfterValue": "100003", 891 "UMask": "0x1" 892 }, 893 { 894 "BriefDescription": "Counts all demand data writes (RFOs)", 895 "Counter": "0,1,2,3", 896 "CounterHTOff": "0,1,2,3", 897 "EventCode": "0xB7, 0xBB", 898 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 899 "MSRIndex": "0x1a6,0x1a7", 900 "MSRValue": "0x3FFC400002", 901 "Offcore": "1", 902 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 903 "SampleAfterValue": "100003", 904 "UMask": "0x1" 905 }, 906 { 907 "BriefDescription": "Counts all demand data writes (RFOs)", 908 "Counter": "0,1,2,3", 909 "CounterHTOff": "0,1,2,3", 910 "EventCode": "0xB7, 0xBB", 911 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM", 912 "MSRIndex": "0x1a6,0x1a7", 913 "MSRValue": "0x103C400002", 914 "Offcore": "1", 915 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 916 "SampleAfterValue": "100003", 917 "UMask": "0x1" 918 }, 919 { 920 "BriefDescription": "Counts all demand data writes (RFOs)", 921 "Counter": "0,1,2,3", 922 "CounterHTOff": "0,1,2,3", 923 "EventCode": "0xB7, 0xBB", 924 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 925 "MSRIndex": "0x1a6,0x1a7", 926 "MSRValue": "0x43C400002", 927 "Offcore": "1", 928 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 929 "SampleAfterValue": "100003", 930 "UMask": "0x1" 931 }, 932 { 933 "BriefDescription": "Counts all demand data writes (RFOs)", 934 "Counter": "0,1,2,3", 935 "CounterHTOff": "0,1,2,3", 936 "EventCode": "0xB7, 0xBB", 937 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", 938 "MSRIndex": "0x1a6,0x1a7", 939 "MSRValue": "0x23C400002", 940 "Offcore": "1", 941 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 942 "SampleAfterValue": "100003", 943 "UMask": "0x1" 944 }, 945 { 946 "BriefDescription": "Counts all demand data writes (RFOs)", 947 "Counter": "0,1,2,3", 948 "CounterHTOff": "0,1,2,3", 949 "EventCode": "0xB7, 0xBB", 950 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", 951 "MSRIndex": "0x1a6,0x1a7", 952 "MSRValue": "0xBC400002", 953 "Offcore": "1", 954 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 955 "SampleAfterValue": "100003", 956 "UMask": "0x1" 957 }, 958 { 959 "BriefDescription": "Counts all demand data writes (RFOs)", 960 "Counter": "0,1,2,3", 961 "CounterHTOff": "0,1,2,3", 962 "EventCode": "0xB7, 0xBB", 963 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM", 964 "MSRIndex": "0x1a6,0x1a7", 965 "MSRValue": "0x203C400002", 966 "Offcore": "1", 967 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 968 "SampleAfterValue": "100003", 969 "UMask": "0x1" 970 }, 971 { 972 "BriefDescription": "Counts all demand data writes (RFOs)", 973 "Counter": "0,1,2,3", 974 "CounterHTOff": "0,1,2,3", 975 "EventCode": "0xB7, 0xBB", 976 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED", 977 "MSRIndex": "0x1a6,0x1a7", 978 "MSRValue": "0x13C400002", 979 "Offcore": "1", 980 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 981 "SampleAfterValue": "100003", 982 "UMask": "0x1" 983 }, 984 { 985 "BriefDescription": "Counts all demand data writes (RFOs)", 986 "Counter": "0,1,2,3", 987 "CounterHTOff": "0,1,2,3", 988 "EventCode": "0xB7, 0xBB", 989 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT", 990 "MSRIndex": "0x1a6,0x1a7", 991 "MSRValue": "0x7C400002", 992 "Offcore": "1", 993 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 994 "SampleAfterValue": "100003", 995 "UMask": "0x1" 996 }, 997 { 998 "BriefDescription": "Counts all demand data writes (RFOs)", 999 "Counter": "0,1,2,3", 1000 "CounterHTOff": "0,1,2,3", 1001 "EventCode": "0xB7, 0xBB", 1002 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1003 "MSRIndex": "0x1a6,0x1a7", 1004 "MSRValue": "0x3FC4000002", 1005 "Offcore": "1", 1006 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1007 "SampleAfterValue": "100003", 1008 "UMask": "0x1" 1009 }, 1010 { 1011 "BriefDescription": "Counts all demand data writes (RFOs)", 1012 "Counter": "0,1,2,3", 1013 "CounterHTOff": "0,1,2,3", 1014 "EventCode": "0xB7, 0xBB", 1015 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1016 "MSRIndex": "0x1a6,0x1a7", 1017 "MSRValue": "0x1004000002", 1018 "Offcore": "1", 1019 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1020 "SampleAfterValue": "100003", 1021 "UMask": "0x1" 1022 }, 1023 { 1024 "BriefDescription": "Counts all demand data writes (RFOs)", 1025 "Counter": "0,1,2,3", 1026 "CounterHTOff": "0,1,2,3", 1027 "EventCode": "0xB7, 0xBB", 1028 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1029 "MSRIndex": "0x1a6,0x1a7", 1030 "MSRValue": "0x404000002", 1031 "Offcore": "1", 1032 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1033 "SampleAfterValue": "100003", 1034 "UMask": "0x1" 1035 }, 1036 { 1037 "BriefDescription": "Counts all demand data writes (RFOs)", 1038 "Counter": "0,1,2,3", 1039 "CounterHTOff": "0,1,2,3", 1040 "EventCode": "0xB7, 0xBB", 1041 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1042 "MSRIndex": "0x1a6,0x1a7", 1043 "MSRValue": "0x204000002", 1044 "Offcore": "1", 1045 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1046 "SampleAfterValue": "100003", 1047 "UMask": "0x1" 1048 }, 1049 { 1050 "BriefDescription": "Counts all demand data writes (RFOs)", 1051 "Counter": "0,1,2,3", 1052 "CounterHTOff": "0,1,2,3", 1053 "EventCode": "0xB7, 0xBB", 1054 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1055 "MSRIndex": "0x1a6,0x1a7", 1056 "MSRValue": "0x84000002", 1057 "Offcore": "1", 1058 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1059 "SampleAfterValue": "100003", 1060 "UMask": "0x1" 1061 }, 1062 { 1063 "BriefDescription": "Counts all demand data writes (RFOs)", 1064 "Counter": "0,1,2,3", 1065 "CounterHTOff": "0,1,2,3", 1066 "EventCode": "0xB7, 0xBB", 1067 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1068 "MSRIndex": "0x1a6,0x1a7", 1069 "MSRValue": "0x2004000002", 1070 "Offcore": "1", 1071 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1072 "SampleAfterValue": "100003", 1073 "UMask": "0x1" 1074 }, 1075 { 1076 "BriefDescription": "Counts all demand data writes (RFOs)", 1077 "Counter": "0,1,2,3", 1078 "CounterHTOff": "0,1,2,3", 1079 "EventCode": "0xB7, 0xBB", 1080 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1081 "MSRIndex": "0x1a6,0x1a7", 1082 "MSRValue": "0x104000002", 1083 "Offcore": "1", 1084 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1085 "SampleAfterValue": "100003", 1086 "UMask": "0x1" 1087 }, 1088 { 1089 "BriefDescription": "Counts all demand data writes (RFOs)", 1090 "Counter": "0,1,2,3", 1091 "CounterHTOff": "0,1,2,3", 1092 "EventCode": "0xB7, 0xBB", 1093 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT", 1094 "MSRIndex": "0x1a6,0x1a7", 1095 "MSRValue": "0x44000002", 1096 "Offcore": "1", 1097 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1098 "SampleAfterValue": "100003", 1099 "UMask": "0x1" 1100 }, 1101 { 1102 "BriefDescription": "Counts all demand data writes (RFOs)", 1103 "Counter": "0,1,2,3", 1104 "CounterHTOff": "0,1,2,3", 1105 "EventCode": "0xB7, 0xBB", 1106 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 1107 "MSRIndex": "0x1a6,0x1a7", 1108 "MSRValue": "0x2000400002", 1109 "Offcore": "1", 1110 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1111 "SampleAfterValue": "100003", 1112 "UMask": "0x1" 1113 }, 1114 { 1115 "BriefDescription": "Counts all demand data writes (RFOs)", 1116 "Counter": "0,1,2,3", 1117 "CounterHTOff": "0,1,2,3", 1118 "EventCode": "0xB7, 0xBB", 1119 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 1120 "MSRIndex": "0x1a6,0x1a7", 1121 "MSRValue": "0x2000020002", 1122 "Offcore": "1", 1123 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1124 "SampleAfterValue": "100003", 1125 "UMask": "0x1" 1126 }, 1127 { 1128 "BriefDescription": "Counts any other requests", 1129 "Counter": "0,1,2,3", 1130 "CounterHTOff": "0,1,2,3", 1131 "EventCode": "0xB7, 0xBB", 1132 "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", 1133 "MSRIndex": "0x1a6,0x1a7", 1134 "MSRValue": "0x20001C8000", 1135 "Offcore": "1", 1136 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1137 "SampleAfterValue": "100003", 1138 "UMask": "0x1" 1139 }, 1140 { 1141 "BriefDescription": "Counts any other requests", 1142 "Counter": "0,1,2,3", 1143 "CounterHTOff": "0,1,2,3", 1144 "EventCode": "0xB7, 0xBB", 1145 "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM", 1146 "MSRIndex": "0x1a6,0x1a7", 1147 "MSRValue": "0x2000088000", 1148 "Offcore": "1", 1149 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1150 "SampleAfterValue": "100003", 1151 "UMask": "0x1" 1152 }, 1153 { 1154 "BriefDescription": "Counts any other requests", 1155 "Counter": "0,1,2,3", 1156 "CounterHTOff": "0,1,2,3", 1157 "EventCode": "0xB7, 0xBB", 1158 "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM", 1159 "MSRIndex": "0x1a6,0x1a7", 1160 "MSRValue": "0x2000048000", 1161 "Offcore": "1", 1162 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1163 "SampleAfterValue": "100003", 1164 "UMask": "0x1" 1165 }, 1166 { 1167 "BriefDescription": "Counts any other requests", 1168 "Counter": "0,1,2,3", 1169 "CounterHTOff": "0,1,2,3", 1170 "EventCode": "0xB7, 0xBB", 1171 "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM", 1172 "MSRIndex": "0x1a6,0x1a7", 1173 "MSRValue": "0x2000108000", 1174 "Offcore": "1", 1175 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1176 "SampleAfterValue": "100003", 1177 "UMask": "0x1" 1178 }, 1179 { 1180 "BriefDescription": "Counts any other requests", 1181 "Counter": "0,1,2,3", 1182 "CounterHTOff": "0,1,2,3", 1183 "EventCode": "0xB7, 0xBB", 1184 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", 1185 "MSRIndex": "0x1a6,0x1a7", 1186 "MSRValue": "0x3FFC408000", 1187 "Offcore": "1", 1188 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1189 "SampleAfterValue": "100003", 1190 "UMask": "0x1" 1191 }, 1192 { 1193 "BriefDescription": "Counts any other requests", 1194 "Counter": "0,1,2,3", 1195 "CounterHTOff": "0,1,2,3", 1196 "EventCode": "0xB7, 0xBB", 1197 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM", 1198 "MSRIndex": "0x1a6,0x1a7", 1199 "MSRValue": "0x103C408000", 1200 "Offcore": "1", 1201 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1202 "SampleAfterValue": "100003", 1203 "UMask": "0x1" 1204 }, 1205 { 1206 "BriefDescription": "Counts any other requests", 1207 "Counter": "0,1,2,3", 1208 "CounterHTOff": "0,1,2,3", 1209 "EventCode": "0xB7, 0xBB", 1210 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", 1211 "MSRIndex": "0x1a6,0x1a7", 1212 "MSRValue": "0x43C408000", 1213 "Offcore": "1", 1214 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1215 "SampleAfterValue": "100003", 1216 "UMask": "0x1" 1217 }, 1218 { 1219 "BriefDescription": "Counts any other requests", 1220 "Counter": "0,1,2,3", 1221 "CounterHTOff": "0,1,2,3", 1222 "EventCode": "0xB7, 0xBB", 1223 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", 1224 "MSRIndex": "0x1a6,0x1a7", 1225 "MSRValue": "0x23C408000", 1226 "Offcore": "1", 1227 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1228 "SampleAfterValue": "100003", 1229 "UMask": "0x1" 1230 }, 1231 { 1232 "BriefDescription": "Counts any other requests", 1233 "Counter": "0,1,2,3", 1234 "CounterHTOff": "0,1,2,3", 1235 "EventCode": "0xB7, 0xBB", 1236 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", 1237 "MSRIndex": "0x1a6,0x1a7", 1238 "MSRValue": "0xBC408000", 1239 "Offcore": "1", 1240 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1241 "SampleAfterValue": "100003", 1242 "UMask": "0x1" 1243 }, 1244 { 1245 "BriefDescription": "Counts any other requests", 1246 "Counter": "0,1,2,3", 1247 "CounterHTOff": "0,1,2,3", 1248 "EventCode": "0xB7, 0xBB", 1249 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", 1250 "MSRIndex": "0x1a6,0x1a7", 1251 "MSRValue": "0x203C408000", 1252 "Offcore": "1", 1253 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1254 "SampleAfterValue": "100003", 1255 "UMask": "0x1" 1256 }, 1257 { 1258 "BriefDescription": "Counts any other requests", 1259 "Counter": "0,1,2,3", 1260 "CounterHTOff": "0,1,2,3", 1261 "EventCode": "0xB7, 0xBB", 1262 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", 1263 "MSRIndex": "0x1a6,0x1a7", 1264 "MSRValue": "0x13C408000", 1265 "Offcore": "1", 1266 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1267 "SampleAfterValue": "100003", 1268 "UMask": "0x1" 1269 }, 1270 { 1271 "BriefDescription": "Counts any other requests", 1272 "Counter": "0,1,2,3", 1273 "CounterHTOff": "0,1,2,3", 1274 "EventCode": "0xB7, 0xBB", 1275 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", 1276 "MSRIndex": "0x1a6,0x1a7", 1277 "MSRValue": "0x7C408000", 1278 "Offcore": "1", 1279 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1280 "SampleAfterValue": "100003", 1281 "UMask": "0x1" 1282 }, 1283 { 1284 "BriefDescription": "Counts any other requests", 1285 "Counter": "0,1,2,3", 1286 "CounterHTOff": "0,1,2,3", 1287 "EventCode": "0xB7, 0xBB", 1288 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1289 "MSRIndex": "0x1a6,0x1a7", 1290 "MSRValue": "0x3FC4008000", 1291 "Offcore": "1", 1292 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1293 "SampleAfterValue": "100003", 1294 "UMask": "0x1" 1295 }, 1296 { 1297 "BriefDescription": "Counts any other requests", 1298 "Counter": "0,1,2,3", 1299 "CounterHTOff": "0,1,2,3", 1300 "EventCode": "0xB7, 0xBB", 1301 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1302 "MSRIndex": "0x1a6,0x1a7", 1303 "MSRValue": "0x1004008000", 1304 "Offcore": "1", 1305 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1306 "SampleAfterValue": "100003", 1307 "UMask": "0x1" 1308 }, 1309 { 1310 "BriefDescription": "Counts any other requests", 1311 "Counter": "0,1,2,3", 1312 "CounterHTOff": "0,1,2,3", 1313 "EventCode": "0xB7, 0xBB", 1314 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1315 "MSRIndex": "0x1a6,0x1a7", 1316 "MSRValue": "0x404008000", 1317 "Offcore": "1", 1318 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1319 "SampleAfterValue": "100003", 1320 "UMask": "0x1" 1321 }, 1322 { 1323 "BriefDescription": "Counts any other requests", 1324 "Counter": "0,1,2,3", 1325 "CounterHTOff": "0,1,2,3", 1326 "EventCode": "0xB7, 0xBB", 1327 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1328 "MSRIndex": "0x1a6,0x1a7", 1329 "MSRValue": "0x204008000", 1330 "Offcore": "1", 1331 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1332 "SampleAfterValue": "100003", 1333 "UMask": "0x1" 1334 }, 1335 { 1336 "BriefDescription": "Counts any other requests", 1337 "Counter": "0,1,2,3", 1338 "CounterHTOff": "0,1,2,3", 1339 "EventCode": "0xB7, 0xBB", 1340 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1341 "MSRIndex": "0x1a6,0x1a7", 1342 "MSRValue": "0x84008000", 1343 "Offcore": "1", 1344 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1345 "SampleAfterValue": "100003", 1346 "UMask": "0x1" 1347 }, 1348 { 1349 "BriefDescription": "Counts any other requests", 1350 "Counter": "0,1,2,3", 1351 "CounterHTOff": "0,1,2,3", 1352 "EventCode": "0xB7, 0xBB", 1353 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1354 "MSRIndex": "0x1a6,0x1a7", 1355 "MSRValue": "0x2004008000", 1356 "Offcore": "1", 1357 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1358 "SampleAfterValue": "100003", 1359 "UMask": "0x1" 1360 }, 1361 { 1362 "BriefDescription": "Counts any other requests", 1363 "Counter": "0,1,2,3", 1364 "CounterHTOff": "0,1,2,3", 1365 "EventCode": "0xB7, 0xBB", 1366 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1367 "MSRIndex": "0x1a6,0x1a7", 1368 "MSRValue": "0x104008000", 1369 "Offcore": "1", 1370 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1371 "SampleAfterValue": "100003", 1372 "UMask": "0x1" 1373 }, 1374 { 1375 "BriefDescription": "Counts any other requests", 1376 "Counter": "0,1,2,3", 1377 "CounterHTOff": "0,1,2,3", 1378 "EventCode": "0xB7, 0xBB", 1379 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", 1380 "MSRIndex": "0x1a6,0x1a7", 1381 "MSRValue": "0x44008000", 1382 "Offcore": "1", 1383 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1384 "SampleAfterValue": "100003", 1385 "UMask": "0x1" 1386 }, 1387 { 1388 "BriefDescription": "Counts any other requests", 1389 "Counter": "0,1,2,3", 1390 "CounterHTOff": "0,1,2,3", 1391 "EventCode": "0xB7, 0xBB", 1392 "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 1393 "MSRIndex": "0x1a6,0x1a7", 1394 "MSRValue": "0x2000408000", 1395 "Offcore": "1", 1396 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1397 "SampleAfterValue": "100003", 1398 "UMask": "0x1" 1399 }, 1400 { 1401 "BriefDescription": "Counts any other requests", 1402 "Counter": "0,1,2,3", 1403 "CounterHTOff": "0,1,2,3", 1404 "EventCode": "0xB7, 0xBB", 1405 "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", 1406 "MSRIndex": "0x1a6,0x1a7", 1407 "MSRValue": "0x2000028000", 1408 "Offcore": "1", 1409 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1410 "SampleAfterValue": "100003", 1411 "UMask": "0x1" 1412 }, 1413 { 1414 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 1415 "Counter": "0,1,2,3", 1416 "CounterHTOff": "0,1,2,3,4,5,6,7", 1417 "EventCode": "0xC9", 1418 "EventName": "RTM_RETIRED.ABORTED", 1419 "PEBS": "1", 1420 "PublicDescription": "Number of times RTM abort was triggered.", 1421 "SampleAfterValue": "2000003", 1422 "UMask": "0x4" 1423 }, 1424 { 1425 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 1426 "Counter": "0,1,2,3", 1427 "CounterHTOff": "0,1,2,3,4,5,6,7", 1428 "EventCode": "0xC9", 1429 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 1430 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 1431 "SampleAfterValue": "2000003", 1432 "UMask": "0x80" 1433 }, 1434 { 1435 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 1436 "Counter": "0,1,2,3", 1437 "CounterHTOff": "0,1,2,3,4,5,6,7", 1438 "EventCode": "0xC9", 1439 "EventName": "RTM_RETIRED.ABORTED_MEM", 1440 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 1441 "SampleAfterValue": "2000003", 1442 "UMask": "0x8" 1443 }, 1444 { 1445 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 1446 "Counter": "0,1,2,3", 1447 "CounterHTOff": "0,1,2,3,4,5,6,7", 1448 "EventCode": "0xC9", 1449 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 1450 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 1451 "SampleAfterValue": "2000003", 1452 "UMask": "0x40" 1453 }, 1454 { 1455 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 1456 "Counter": "0,1,2,3", 1457 "CounterHTOff": "0,1,2,3,4,5,6,7", 1458 "EventCode": "0xC9", 1459 "EventName": "RTM_RETIRED.ABORTED_TIMER", 1460 "SampleAfterValue": "2000003", 1461 "UMask": "0x10" 1462 }, 1463 { 1464 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 1465 "Counter": "0,1,2,3", 1466 "CounterHTOff": "0,1,2,3,4,5,6,7", 1467 "EventCode": "0xC9", 1468 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 1469 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 1470 "SampleAfterValue": "2000003", 1471 "UMask": "0x20" 1472 }, 1473 { 1474 "BriefDescription": "Number of times an RTM execution successfully committed", 1475 "Counter": "0,1,2,3", 1476 "CounterHTOff": "0,1,2,3,4,5,6,7", 1477 "EventCode": "0xC9", 1478 "EventName": "RTM_RETIRED.COMMIT", 1479 "PublicDescription": "Number of times RTM commit succeeded.", 1480 "SampleAfterValue": "2000003", 1481 "UMask": "0x2" 1482 }, 1483 { 1484 "BriefDescription": "Number of times an RTM execution started.", 1485 "Counter": "0,1,2,3", 1486 "CounterHTOff": "0,1,2,3,4,5,6,7", 1487 "EventCode": "0xC9", 1488 "EventName": "RTM_RETIRED.START", 1489 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 1490 "SampleAfterValue": "2000003", 1491 "UMask": "0x1" 1492 }, 1493 { 1494 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 1495 "Counter": "0,1,2,3", 1496 "CounterHTOff": "0,1,2,3,4,5,6,7", 1497 "EventCode": "0x5d", 1498 "EventName": "TX_EXEC.MISC1", 1499 "SampleAfterValue": "2000003", 1500 "UMask": "0x1" 1501 }, 1502 { 1503 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 1504 "Counter": "0,1,2,3", 1505 "CounterHTOff": "0,1,2,3,4,5,6,7", 1506 "EventCode": "0x5d", 1507 "EventName": "TX_EXEC.MISC2", 1508 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 1509 "SampleAfterValue": "2000003", 1510 "UMask": "0x2" 1511 }, 1512 { 1513 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 1514 "Counter": "0,1,2,3", 1515 "CounterHTOff": "0,1,2,3,4,5,6,7", 1516 "EventCode": "0x5d", 1517 "EventName": "TX_EXEC.MISC3", 1518 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 1519 "SampleAfterValue": "2000003", 1520 "UMask": "0x4" 1521 }, 1522 { 1523 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 1524 "Counter": "0,1,2,3", 1525 "CounterHTOff": "0,1,2,3,4,5,6,7", 1526 "EventCode": "0x5d", 1527 "EventName": "TX_EXEC.MISC4", 1528 "PublicDescription": "RTM region detected inside HLE.", 1529 "SampleAfterValue": "2000003", 1530 "UMask": "0x8" 1531 }, 1532 { 1533 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 1534 "Counter": "0,1,2,3", 1535 "CounterHTOff": "0,1,2,3,4,5,6,7", 1536 "EventCode": "0x5d", 1537 "EventName": "TX_EXEC.MISC5", 1538 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 1539 "SampleAfterValue": "2000003", 1540 "UMask": "0x10" 1541 }, 1542 { 1543 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 1544 "Counter": "0,1,2,3", 1545 "CounterHTOff": "0,1,2,3,4,5,6,7", 1546 "EventCode": "0x54", 1547 "EventName": "TX_MEM.ABORT_CAPACITY", 1548 "SampleAfterValue": "2000003", 1549 "UMask": "0x2" 1550 }, 1551 { 1552 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 1553 "Counter": "0,1,2,3", 1554 "CounterHTOff": "0,1,2,3,4,5,6,7", 1555 "EventCode": "0x54", 1556 "EventName": "TX_MEM.ABORT_CONFLICT", 1557 "PublicDescription": "Number of times a TSX line had a cache conflict.", 1558 "SampleAfterValue": "2000003", 1559 "UMask": "0x1" 1560 }, 1561 { 1562 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 1563 "Counter": "0,1,2,3", 1564 "CounterHTOff": "0,1,2,3,4,5,6,7", 1565 "EventCode": "0x54", 1566 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 1567 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 1568 "SampleAfterValue": "2000003", 1569 "UMask": "0x10" 1570 }, 1571 { 1572 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 1573 "Counter": "0,1,2,3", 1574 "CounterHTOff": "0,1,2,3,4,5,6,7", 1575 "EventCode": "0x54", 1576 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 1577 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 1578 "SampleAfterValue": "2000003", 1579 "UMask": "0x8" 1580 }, 1581 { 1582 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 1583 "Counter": "0,1,2,3", 1584 "CounterHTOff": "0,1,2,3,4,5,6,7", 1585 "EventCode": "0x54", 1586 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 1587 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 1588 "SampleAfterValue": "2000003", 1589 "UMask": "0x20" 1590 }, 1591 { 1592 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 1593 "Counter": "0,1,2,3", 1594 "CounterHTOff": "0,1,2,3,4,5,6,7", 1595 "EventCode": "0x54", 1596 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 1597 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 1598 "SampleAfterValue": "2000003", 1599 "UMask": "0x4" 1600 }, 1601 { 1602 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 1603 "Counter": "0,1,2,3", 1604 "CounterHTOff": "0,1,2,3,4,5,6,7", 1605 "EventCode": "0x54", 1606 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 1607 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 1608 "SampleAfterValue": "2000003", 1609 "UMask": "0x40" 1610 } 1611]