1[ 2 { 3 "BriefDescription": "Counts all demand code reads", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3", 6 "EventCode": "0xB7, 0xBB", 7 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM", 8 "MSRIndex": "0x1a6,0x1a7", 9 "MSRValue": "0x2000080004", 10 "Offcore": "1", 11 "PublicDescription": "Counts all demand code reads", 12 "SampleAfterValue": "100003", 13 "UMask": "0x1" 14 }, 15 { 16 "BriefDescription": "Counts demand data reads", 17 "Counter": "0,1,2,3", 18 "CounterHTOff": "0,1,2,3", 19 "EventCode": "0xB7, 0xBB", 20 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 21 "MSRIndex": "0x1a6,0x1a7", 22 "MSRValue": "0x0104000001", 23 "Offcore": "1", 24 "PublicDescription": "Counts demand data reads", 25 "SampleAfterValue": "100003", 26 "UMask": "0x1" 27 }, 28 { 29 "BriefDescription": "Counts all demand data writes (RFOs)", 30 "Counter": "0,1,2,3", 31 "CounterHTOff": "0,1,2,3", 32 "EventCode": "0xB7, 0xBB", 33 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM", 34 "MSRIndex": "0x1a6,0x1a7", 35 "MSRValue": "0x2000100002", 36 "Offcore": "1", 37 "PublicDescription": "Counts all demand data writes (RFOs)", 38 "SampleAfterValue": "100003", 39 "UMask": "0x1" 40 }, 41 { 42 "BriefDescription": "Counts any other requests", 43 "Counter": "0,1,2,3", 44 "CounterHTOff": "0,1,2,3", 45 "EventCode": "0xB7, 0xBB", 46 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 47 "MSRIndex": "0x1a6,0x1a7", 48 "MSRValue": "0x0084008000", 49 "Offcore": "1", 50 "PublicDescription": "Counts any other requests", 51 "SampleAfterValue": "100003", 52 "UMask": "0x1" 53 }, 54 { 55 "BriefDescription": "Counts all demand code reads", 56 "Counter": "0,1,2,3", 57 "CounterHTOff": "0,1,2,3", 58 "EventCode": "0xB7, 0xBB", 59 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", 60 "MSRIndex": "0x1a6,0x1a7", 61 "MSRValue": "0x007C400004", 62 "Offcore": "1", 63 "PublicDescription": "Counts all demand code reads", 64 "SampleAfterValue": "100003", 65 "UMask": "0x1" 66 }, 67 { 68 "BriefDescription": "Counts any other requests", 69 "Counter": "0,1,2,3", 70 "CounterHTOff": "0,1,2,3", 71 "EventCode": "0xB7, 0xBB", 72 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", 73 "MSRIndex": "0x1a6,0x1a7", 74 "MSRValue": "0x043C408000", 75 "Offcore": "1", 76 "PublicDescription": "Counts any other requests", 77 "SampleAfterValue": "100003", 78 "UMask": "0x1" 79 }, 80 { 81 "BriefDescription": "Counts all demand code reads", 82 "Counter": "0,1,2,3", 83 "CounterHTOff": "0,1,2,3", 84 "EventCode": "0xB7, 0xBB", 85 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 86 "MSRIndex": "0x1a6,0x1a7", 87 "MSRValue": "0x0204000004", 88 "Offcore": "1", 89 "PublicDescription": "Counts all demand code reads", 90 "SampleAfterValue": "100003", 91 "UMask": "0x1" 92 }, 93 { 94 "BriefDescription": "Counts any other requests", 95 "Counter": "0,1,2,3", 96 "CounterHTOff": "0,1,2,3", 97 "EventCode": "0xB7, 0xBB", 98 "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM", 99 "MSRIndex": "0x1a6,0x1a7", 100 "MSRValue": "0x2000088000", 101 "Offcore": "1", 102 "PublicDescription": "Counts any other requests", 103 "SampleAfterValue": "100003", 104 "UMask": "0x1" 105 }, 106 { 107 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 108 "Counter": "0,1,2,3", 109 "CounterHTOff": "0,1,2,3,4,5,6,7", 110 "CounterMask": "6", 111 "EventCode": "0x60", 112 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 113 "SampleAfterValue": "2000003", 114 "UMask": "0x10" 115 }, 116 { 117 "BriefDescription": "Counts any other requests", 118 "Counter": "0,1,2,3", 119 "CounterHTOff": "0,1,2,3", 120 "EventCode": "0xB7, 0xBB", 121 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", 122 "MSRIndex": "0x1a6,0x1a7", 123 "MSRValue": "0x00BC408000", 124 "Offcore": "1", 125 "PublicDescription": "Counts any other requests", 126 "SampleAfterValue": "100003", 127 "UMask": "0x1" 128 }, 129 { 130 "BriefDescription": "Counts any other requests", 131 "Counter": "0,1,2,3", 132 "CounterHTOff": "0,1,2,3", 133 "EventCode": "0xB7, 0xBB", 134 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM", 135 "MSRIndex": "0x1a6,0x1a7", 136 "MSRValue": "0x103C408000", 137 "Offcore": "1", 138 "PublicDescription": "Counts any other requests", 139 "SampleAfterValue": "100003", 140 "UMask": "0x1" 141 }, 142 { 143 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 144 "Counter": "0,1,2,3", 145 "CounterHTOff": "0,1,2,3,4,5,6,7", 146 "EventCode": "0xC8", 147 "EventName": "HLE_RETIRED.ABORTED_TIMER", 148 "SampleAfterValue": "2000003", 149 "UMask": "0x10" 150 }, 151 { 152 "BriefDescription": "Counts demand data reads", 153 "Counter": "0,1,2,3", 154 "CounterHTOff": "0,1,2,3", 155 "EventCode": "0xB7, 0xBB", 156 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 157 "MSRIndex": "0x1a6,0x1a7", 158 "MSRValue": "0x023C400001", 159 "Offcore": "1", 160 "PublicDescription": "Counts demand data reads", 161 "SampleAfterValue": "100003", 162 "UMask": "0x1" 163 }, 164 { 165 "BriefDescription": "Counts all demand data writes (RFOs)", 166 "Counter": "0,1,2,3", 167 "CounterHTOff": "0,1,2,3", 168 "EventCode": "0xB7, 0xBB", 169 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 170 "MSRIndex": "0x1a6,0x1a7", 171 "MSRValue": "0x0204000002", 172 "Offcore": "1", 173 "PublicDescription": "Counts all demand data writes (RFOs)", 174 "SampleAfterValue": "100003", 175 "UMask": "0x1" 176 }, 177 { 178 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 179 "Counter": "0,1,2,3", 180 "CounterHTOff": "0,1,2,3,4,5,6,7", 181 "EventCode": "0xC9", 182 "EventName": "RTM_RETIRED.ABORTED_MEM", 183 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 184 "SampleAfterValue": "2000003", 185 "UMask": "0x8" 186 }, 187 { 188 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 189 "Counter": "0,1,2,3", 190 "CounterHTOff": "0,1,2,3,4,5,6,7", 191 "EventCode": "0xC9", 192 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 193 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 194 "SampleAfterValue": "2000003", 195 "UMask": "0x40" 196 }, 197 { 198 "BriefDescription": "Counts all demand data writes (RFOs)", 199 "Counter": "0,1,2,3", 200 "CounterHTOff": "0,1,2,3", 201 "EventCode": "0xB7, 0xBB", 202 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM", 203 "MSRIndex": "0x1a6,0x1a7", 204 "MSRValue": "0x2000080002", 205 "Offcore": "1", 206 "PublicDescription": "Counts all demand data writes (RFOs)", 207 "SampleAfterValue": "100003", 208 "UMask": "0x1" 209 }, 210 { 211 "BriefDescription": "Counts any other requests", 212 "Counter": "0,1,2,3", 213 "CounterHTOff": "0,1,2,3", 214 "EventCode": "0xB7, 0xBB", 215 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 216 "MSRIndex": "0x1a6,0x1a7", 217 "MSRValue": "0x1004008000", 218 "Offcore": "1", 219 "PublicDescription": "Counts any other requests", 220 "SampleAfterValue": "100003", 221 "UMask": "0x1" 222 }, 223 { 224 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 225 "Counter": "0,1,2,3", 226 "CounterHTOff": "0,1,2,3,4,5,6,7", 227 "CounterMask": "2", 228 "EventCode": "0xA3", 229 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 230 "SampleAfterValue": "2000003", 231 "UMask": "0x2" 232 }, 233 { 234 "BriefDescription": "Counts any other requests", 235 "Counter": "0,1,2,3", 236 "CounterHTOff": "0,1,2,3", 237 "EventCode": "0xB7, 0xBB", 238 "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", 239 "MSRIndex": "0x1a6,0x1a7", 240 "MSRValue": "0x2000028000", 241 "Offcore": "1", 242 "PublicDescription": "Counts any other requests", 243 "SampleAfterValue": "100003", 244 "UMask": "0x1" 245 }, 246 { 247 "BriefDescription": "Counts any other requests", 248 "Counter": "0,1,2,3", 249 "CounterHTOff": "0,1,2,3", 250 "EventCode": "0xB7, 0xBB", 251 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", 252 "MSRIndex": "0x1a6,0x1a7", 253 "MSRValue": "0x3FFC408000", 254 "Offcore": "1", 255 "PublicDescription": "Counts any other requests", 256 "SampleAfterValue": "100003", 257 "UMask": "0x1" 258 }, 259 { 260 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 261 "Counter": "0,1,2,3", 262 "CounterHTOff": "0,1,2,3", 263 "Data_LA": "1", 264 "EventCode": "0xcd", 265 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 266 "MSRIndex": "0x3F6", 267 "MSRValue": "0x20", 268 "PEBS": "2", 269 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 270 "SampleAfterValue": "100007", 271 "TakenAlone": "1", 272 "UMask": "0x1" 273 }, 274 { 275 "BriefDescription": "Counts all demand data writes (RFOs)", 276 "Counter": "0,1,2,3", 277 "CounterHTOff": "0,1,2,3", 278 "EventCode": "0xB7, 0xBB", 279 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 280 "MSRIndex": "0x1a6,0x1a7", 281 "MSRValue": "0x043C400002", 282 "Offcore": "1", 283 "PublicDescription": "Counts all demand data writes (RFOs)", 284 "SampleAfterValue": "100003", 285 "UMask": "0x1" 286 }, 287 { 288 "BriefDescription": "Counts all demand code reads", 289 "Counter": "0,1,2,3", 290 "CounterHTOff": "0,1,2,3", 291 "EventCode": "0xB7, 0xBB", 292 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 293 "MSRIndex": "0x1a6,0x1a7", 294 "MSRValue": "0x2000020004", 295 "Offcore": "1", 296 "PublicDescription": "Counts all demand code reads", 297 "SampleAfterValue": "100003", 298 "UMask": "0x1" 299 }, 300 { 301 "BriefDescription": "Counts all demand data writes (RFOs)", 302 "Counter": "0,1,2,3", 303 "CounterHTOff": "0,1,2,3", 304 "EventCode": "0xB7, 0xBB", 305 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT", 306 "MSRIndex": "0x1a6,0x1a7", 307 "MSRValue": "0x0044000002", 308 "Offcore": "1", 309 "PublicDescription": "Counts all demand data writes (RFOs)", 310 "SampleAfterValue": "100003", 311 "UMask": "0x1" 312 }, 313 { 314 "BriefDescription": "Counts any other requests", 315 "Counter": "0,1,2,3", 316 "CounterHTOff": "0,1,2,3", 317 "EventCode": "0xB7, 0xBB", 318 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 319 "MSRIndex": "0x1a6,0x1a7", 320 "MSRValue": "0x0204008000", 321 "Offcore": "1", 322 "PublicDescription": "Counts any other requests", 323 "SampleAfterValue": "100003", 324 "UMask": "0x1" 325 }, 326 { 327 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 328 "Counter": "0,1,2,3", 329 "CounterHTOff": "0,1,2,3,4,5,6,7", 330 "EventCode": "0x54", 331 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 332 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 333 "SampleAfterValue": "2000003", 334 "UMask": "0x4" 335 }, 336 { 337 "BriefDescription": "Counts demand data reads", 338 "Counter": "0,1,2,3", 339 "CounterHTOff": "0,1,2,3", 340 "EventCode": "0xB7, 0xBB", 341 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", 342 "MSRIndex": "0x1a6,0x1a7", 343 "MSRValue": "0x103C400001", 344 "Offcore": "1", 345 "PublicDescription": "Counts demand data reads", 346 "SampleAfterValue": "100003", 347 "UMask": "0x1" 348 }, 349 { 350 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 351 "Counter": "0,1,2,3", 352 "CounterHTOff": "0,1,2,3,4,5,6,7", 353 "EventCode": "0x54", 354 "EventName": "TX_MEM.ABORT_CONFLICT", 355 "PublicDescription": "Number of times a TSX line had a cache conflict.", 356 "SampleAfterValue": "2000003", 357 "UMask": "0x1" 358 }, 359 { 360 "BriefDescription": "Counts demand data reads", 361 "Counter": "0,1,2,3", 362 "CounterHTOff": "0,1,2,3", 363 "EventCode": "0xB7, 0xBB", 364 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 365 "MSRIndex": "0x1a6,0x1a7", 366 "MSRValue": "0x1004000001", 367 "Offcore": "1", 368 "PublicDescription": "Counts demand data reads", 369 "SampleAfterValue": "100003", 370 "UMask": "0x1" 371 }, 372 { 373 "BriefDescription": "Counts demand data reads", 374 "Counter": "0,1,2,3", 375 "CounterHTOff": "0,1,2,3", 376 "EventCode": "0xB7, 0xBB", 377 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM", 378 "MSRIndex": "0x1a6,0x1a7", 379 "MSRValue": "0x2000080001", 380 "Offcore": "1", 381 "PublicDescription": "Counts demand data reads", 382 "SampleAfterValue": "100003", 383 "UMask": "0x1" 384 }, 385 { 386 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 387 "Counter": "0,1,2,3", 388 "CounterHTOff": "0,1,2,3", 389 "Data_LA": "1", 390 "EventCode": "0xcd", 391 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 392 "MSRIndex": "0x3F6", 393 "MSRValue": "0x40", 394 "PEBS": "2", 395 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 396 "SampleAfterValue": "2003", 397 "TakenAlone": "1", 398 "UMask": "0x1" 399 }, 400 { 401 "BriefDescription": "Counts demand data reads", 402 "Counter": "0,1,2,3", 403 "CounterHTOff": "0,1,2,3", 404 "EventCode": "0xB7, 0xBB", 405 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 406 "MSRIndex": "0x1a6,0x1a7", 407 "MSRValue": "0x0204000001", 408 "Offcore": "1", 409 "PublicDescription": "Counts demand data reads", 410 "SampleAfterValue": "100003", 411 "UMask": "0x1" 412 }, 413 { 414 "BriefDescription": "Counts all demand data writes (RFOs)", 415 "Counter": "0,1,2,3", 416 "CounterHTOff": "0,1,2,3", 417 "EventCode": "0xB7, 0xBB", 418 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 419 "MSRIndex": "0x1a6,0x1a7", 420 "MSRValue": "0x2000020002", 421 "Offcore": "1", 422 "PublicDescription": "Counts all demand data writes (RFOs)", 423 "SampleAfterValue": "100003", 424 "UMask": "0x1" 425 }, 426 { 427 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 428 "Counter": "0,1,2,3", 429 "CounterHTOff": "0,1,2,3,4,5,6,7", 430 "EventCode": "0x54", 431 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 432 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 433 "SampleAfterValue": "2000003", 434 "UMask": "0x8" 435 }, 436 { 437 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 438 "Counter": "0,1,2,3", 439 "CounterHTOff": "0,1,2,3,4,5,6,7", 440 "EventCode": "0x5d", 441 "EventName": "TX_EXEC.MISC5", 442 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 443 "SampleAfterValue": "2000003", 444 "UMask": "0x10" 445 }, 446 { 447 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 448 "Counter": "0,1,2,3", 449 "CounterHTOff": "0,1,2,3,4,5,6,7", 450 "EventCode": "0x5d", 451 "EventName": "TX_EXEC.MISC4", 452 "PublicDescription": "RTM region detected inside HLE.", 453 "SampleAfterValue": "2000003", 454 "UMask": "0x8" 455 }, 456 { 457 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 458 "Counter": "0,1,2,3", 459 "CounterHTOff": "0,1,2,3,4,5,6,7", 460 "EventCode": "0x5d", 461 "EventName": "TX_EXEC.MISC3", 462 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 463 "SampleAfterValue": "2000003", 464 "UMask": "0x4" 465 }, 466 { 467 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 468 "Counter": "0,1,2,3", 469 "CounterHTOff": "0,1,2,3,4,5,6,7", 470 "EventCode": "0x5d", 471 "EventName": "TX_EXEC.MISC2", 472 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 473 "SampleAfterValue": "2000003", 474 "UMask": "0x2" 475 }, 476 { 477 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 478 "Counter": "0,1,2,3", 479 "CounterHTOff": "0,1,2,3,4,5,6,7", 480 "EventCode": "0x5d", 481 "EventName": "TX_EXEC.MISC1", 482 "SampleAfterValue": "2000003", 483 "UMask": "0x1" 484 }, 485 { 486 "BriefDescription": "Counts demand data reads", 487 "Counter": "0,1,2,3", 488 "CounterHTOff": "0,1,2,3", 489 "EventCode": "0xB7, 0xBB", 490 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 491 "MSRIndex": "0x1a6,0x1a7", 492 "MSRValue": "0x0404000001", 493 "Offcore": "1", 494 "PublicDescription": "Counts demand data reads", 495 "SampleAfterValue": "100003", 496 "UMask": "0x1" 497 }, 498 { 499 "BriefDescription": "Counts all demand code reads", 500 "Counter": "0,1,2,3", 501 "CounterHTOff": "0,1,2,3", 502 "EventCode": "0xB7, 0xBB", 503 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 504 "MSRIndex": "0x1a6,0x1a7", 505 "MSRValue": "0x0084000004", 506 "Offcore": "1", 507 "PublicDescription": "Counts all demand code reads", 508 "SampleAfterValue": "100003", 509 "UMask": "0x1" 510 }, 511 { 512 "BriefDescription": "Number of times an RTM execution successfully committed", 513 "Counter": "0,1,2,3", 514 "CounterHTOff": "0,1,2,3,4,5,6,7", 515 "EventCode": "0xC9", 516 "EventName": "RTM_RETIRED.COMMIT", 517 "PublicDescription": "Number of times RTM commit succeeded.", 518 "SampleAfterValue": "2000003", 519 "UMask": "0x2" 520 }, 521 { 522 "BriefDescription": "Counts demand data reads", 523 "Counter": "0,1,2,3", 524 "CounterHTOff": "0,1,2,3", 525 "EventCode": "0xB7, 0xBB", 526 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM", 527 "MSRIndex": "0x1a6,0x1a7", 528 "MSRValue": "0x2000100001", 529 "Offcore": "1", 530 "PublicDescription": "Counts demand data reads", 531 "SampleAfterValue": "100003", 532 "UMask": "0x1" 533 }, 534 { 535 "BriefDescription": "Counts all demand code reads", 536 "Counter": "0,1,2,3", 537 "CounterHTOff": "0,1,2,3", 538 "EventCode": "0xB7, 0xBB", 539 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", 540 "MSRIndex": "0x1a6,0x1a7", 541 "MSRValue": "0x103C400004", 542 "Offcore": "1", 543 "PublicDescription": "Counts all demand code reads", 544 "SampleAfterValue": "100003", 545 "UMask": "0x1" 546 }, 547 { 548 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 549 "Counter": "0,1,2,3", 550 "CounterHTOff": "0,1,2,3,4,5,6,7", 551 "EventCode": "0x60", 552 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 553 "SampleAfterValue": "2000003", 554 "UMask": "0x10" 555 }, 556 { 557 "BriefDescription": "Counts any other requests", 558 "Counter": "0,1,2,3", 559 "CounterHTOff": "0,1,2,3", 560 "EventCode": "0xB7, 0xBB", 561 "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM", 562 "MSRIndex": "0x1a6,0x1a7", 563 "MSRValue": "0x2000048000", 564 "Offcore": "1", 565 "PublicDescription": "Counts any other requests", 566 "SampleAfterValue": "100003", 567 "UMask": "0x1" 568 }, 569 { 570 "BriefDescription": "Counts all demand data writes (RFOs)", 571 "Counter": "0,1,2,3", 572 "CounterHTOff": "0,1,2,3", 573 "EventCode": "0xB7, 0xBB", 574 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 575 "MSRIndex": "0x1a6,0x1a7", 576 "MSRValue": "0x0104000002", 577 "Offcore": "1", 578 "PublicDescription": "Counts all demand data writes (RFOs)", 579 "SampleAfterValue": "100003", 580 "UMask": "0x1" 581 }, 582 { 583 "BriefDescription": "Counts all demand code reads", 584 "Counter": "0,1,2,3", 585 "CounterHTOff": "0,1,2,3", 586 "EventCode": "0xB7, 0xBB", 587 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM", 588 "MSRIndex": "0x1a6,0x1a7", 589 "MSRValue": "0x203C400004", 590 "Offcore": "1", 591 "PublicDescription": "Counts all demand code reads", 592 "SampleAfterValue": "100003", 593 "UMask": "0x1" 594 }, 595 { 596 "BriefDescription": "Counts any other requests", 597 "Counter": "0,1,2,3", 598 "CounterHTOff": "0,1,2,3", 599 "EventCode": "0xB7, 0xBB", 600 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", 601 "MSRIndex": "0x1a6,0x1a7", 602 "MSRValue": "0x007C408000", 603 "Offcore": "1", 604 "PublicDescription": "Counts any other requests", 605 "SampleAfterValue": "100003", 606 "UMask": "0x1" 607 }, 608 { 609 "BriefDescription": "Counts all demand code reads", 610 "Counter": "0,1,2,3", 611 "CounterHTOff": "0,1,2,3", 612 "EventCode": "0xB7, 0xBB", 613 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 614 "MSRIndex": "0x1a6,0x1a7", 615 "MSRValue": "0x0104000004", 616 "Offcore": "1", 617 "PublicDescription": "Counts all demand code reads", 618 "SampleAfterValue": "100003", 619 "UMask": "0x1" 620 }, 621 { 622 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 623 "Counter": "0,1,2,3", 624 "CounterHTOff": "0,1,2,3,4,5,6,7", 625 "EventCode": "0xC9", 626 "EventName": "RTM_RETIRED.ABORTED_TIMER", 627 "SampleAfterValue": "2000003", 628 "UMask": "0x10" 629 }, 630 { 631 "BriefDescription": "Counts all demand code reads", 632 "Counter": "0,1,2,3", 633 "CounterHTOff": "0,1,2,3", 634 "EventCode": "0xB7, 0xBB", 635 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 636 "MSRIndex": "0x1a6,0x1a7", 637 "MSRValue": "0x2004000004", 638 "Offcore": "1", 639 "PublicDescription": "Counts all demand code reads", 640 "SampleAfterValue": "100003", 641 "UMask": "0x1" 642 }, 643 { 644 "BriefDescription": "Counts all demand code reads", 645 "Counter": "0,1,2,3", 646 "CounterHTOff": "0,1,2,3", 647 "EventCode": "0xB7, 0xBB", 648 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 649 "MSRIndex": "0x1a6,0x1a7", 650 "MSRValue": "0x1004000004", 651 "Offcore": "1", 652 "PublicDescription": "Counts all demand code reads", 653 "SampleAfterValue": "100003", 654 "UMask": "0x1" 655 }, 656 { 657 "BriefDescription": "Counts any other requests", 658 "Counter": "0,1,2,3", 659 "CounterHTOff": "0,1,2,3", 660 "EventCode": "0xB7, 0xBB", 661 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", 662 "MSRIndex": "0x1a6,0x1a7", 663 "MSRValue": "0x0044008000", 664 "Offcore": "1", 665 "PublicDescription": "Counts any other requests", 666 "SampleAfterValue": "100003", 667 "UMask": "0x1" 668 }, 669 { 670 "BriefDescription": "Counts demand data reads", 671 "Counter": "0,1,2,3", 672 "CounterHTOff": "0,1,2,3", 673 "EventCode": "0xB7, 0xBB", 674 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", 675 "MSRIndex": "0x1a6,0x1a7", 676 "MSRValue": "0x0044000001", 677 "Offcore": "1", 678 "PublicDescription": "Counts demand data reads", 679 "SampleAfterValue": "100003", 680 "UMask": "0x1" 681 }, 682 { 683 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 684 "Counter": "0,1,2,3", 685 "CounterHTOff": "0,1,2,3,4,5,6,7", 686 "EventCode": "0xC8", 687 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 688 "SampleAfterValue": "2000003", 689 "UMask": "0x20" 690 }, 691 { 692 "BriefDescription": "Counts all demand data writes (RFOs)", 693 "Counter": "0,1,2,3", 694 "CounterHTOff": "0,1,2,3", 695 "EventCode": "0xB7, 0xBB", 696 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 697 "MSRIndex": "0x1a6,0x1a7", 698 "MSRValue": "0x0084000002", 699 "Offcore": "1", 700 "PublicDescription": "Counts all demand data writes (RFOs)", 701 "SampleAfterValue": "100003", 702 "UMask": "0x1" 703 }, 704 { 705 "BriefDescription": "Counts all demand code reads", 706 "Counter": "0,1,2,3", 707 "CounterHTOff": "0,1,2,3", 708 "EventCode": "0xB7, 0xBB", 709 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 710 "MSRIndex": "0x1a6,0x1a7", 711 "MSRValue": "0x043C400004", 712 "Offcore": "1", 713 "PublicDescription": "Counts all demand code reads", 714 "SampleAfterValue": "100003", 715 "UMask": "0x1" 716 }, 717 { 718 "BriefDescription": "Counts all demand data writes (RFOs)", 719 "Counter": "0,1,2,3", 720 "CounterHTOff": "0,1,2,3", 721 "EventCode": "0xB7, 0xBB", 722 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", 723 "MSRIndex": "0x1a6,0x1a7", 724 "MSRValue": "0x00BC400002", 725 "Offcore": "1", 726 "PublicDescription": "Counts all demand data writes (RFOs)", 727 "SampleAfterValue": "100003", 728 "UMask": "0x1" 729 }, 730 { 731 "BriefDescription": "Counts any other requests", 732 "Counter": "0,1,2,3", 733 "CounterHTOff": "0,1,2,3", 734 "EventCode": "0xB7, 0xBB", 735 "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 736 "MSRIndex": "0x1a6,0x1a7", 737 "MSRValue": "0x2000408000", 738 "Offcore": "1", 739 "PublicDescription": "Counts any other requests", 740 "SampleAfterValue": "100003", 741 "UMask": "0x1" 742 }, 743 { 744 "BriefDescription": "Counts all demand code reads", 745 "Counter": "0,1,2,3", 746 "CounterHTOff": "0,1,2,3", 747 "EventCode": "0xB7, 0xBB", 748 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM", 749 "MSRIndex": "0x1a6,0x1a7", 750 "MSRValue": "0x2000040004", 751 "Offcore": "1", 752 "PublicDescription": "Counts all demand code reads", 753 "SampleAfterValue": "100003", 754 "UMask": "0x1" 755 }, 756 { 757 "BriefDescription": "Counts all demand code reads", 758 "Counter": "0,1,2,3", 759 "CounterHTOff": "0,1,2,3", 760 "EventCode": "0xB7, 0xBB", 761 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 762 "MSRIndex": "0x1a6,0x1a7", 763 "MSRValue": "0x2000400004", 764 "Offcore": "1", 765 "PublicDescription": "Counts all demand code reads", 766 "SampleAfterValue": "100003", 767 "UMask": "0x1" 768 }, 769 { 770 "BriefDescription": "Counts all demand data writes (RFOs)", 771 "Counter": "0,1,2,3", 772 "CounterHTOff": "0,1,2,3", 773 "EventCode": "0xB7, 0xBB", 774 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 775 "MSRIndex": "0x1a6,0x1a7", 776 "MSRValue": "0x2000400002", 777 "Offcore": "1", 778 "PublicDescription": "Counts all demand data writes (RFOs)", 779 "SampleAfterValue": "100003", 780 "UMask": "0x1" 781 }, 782 { 783 "BriefDescription": "Counts all demand code reads", 784 "Counter": "0,1,2,3", 785 "CounterHTOff": "0,1,2,3", 786 "EventCode": "0xB7, 0xBB", 787 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 788 "MSRIndex": "0x1a6,0x1a7", 789 "MSRValue": "0x20001C0004", 790 "Offcore": "1", 791 "PublicDescription": "Counts all demand code reads", 792 "SampleAfterValue": "100003", 793 "UMask": "0x1" 794 }, 795 { 796 "BriefDescription": "Counts all demand data writes (RFOs)", 797 "Counter": "0,1,2,3", 798 "CounterHTOff": "0,1,2,3", 799 "EventCode": "0xB7, 0xBB", 800 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM", 801 "MSRIndex": "0x1a6,0x1a7", 802 "MSRValue": "0x103C400002", 803 "Offcore": "1", 804 "PublicDescription": "Counts all demand data writes (RFOs)", 805 "SampleAfterValue": "100003", 806 "UMask": "0x1" 807 }, 808 { 809 "BriefDescription": "Counts all demand code reads", 810 "Counter": "0,1,2,3", 811 "CounterHTOff": "0,1,2,3", 812 "EventCode": "0xB7, 0xBB", 813 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 814 "MSRIndex": "0x1a6,0x1a7", 815 "MSRValue": "0x013C400004", 816 "Offcore": "1", 817 "PublicDescription": "Counts all demand code reads", 818 "SampleAfterValue": "100003", 819 "UMask": "0x1" 820 }, 821 { 822 "BriefDescription": "Counts any other requests", 823 "Counter": "0,1,2,3", 824 "CounterHTOff": "0,1,2,3", 825 "EventCode": "0xB7, 0xBB", 826 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 827 "MSRIndex": "0x1a6,0x1a7", 828 "MSRValue": "0x0404008000", 829 "Offcore": "1", 830 "PublicDescription": "Counts any other requests", 831 "SampleAfterValue": "100003", 832 "UMask": "0x1" 833 }, 834 { 835 "BriefDescription": "Counts any other requests", 836 "Counter": "0,1,2,3", 837 "CounterHTOff": "0,1,2,3", 838 "EventCode": "0xB7, 0xBB", 839 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 840 "MSRIndex": "0x1a6,0x1a7", 841 "MSRValue": "0x0104008000", 842 "Offcore": "1", 843 "PublicDescription": "Counts any other requests", 844 "SampleAfterValue": "100003", 845 "UMask": "0x1" 846 }, 847 { 848 "BriefDescription": "Counts demand data reads", 849 "Counter": "0,1,2,3", 850 "CounterHTOff": "0,1,2,3", 851 "EventCode": "0xB7, 0xBB", 852 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 853 "MSRIndex": "0x1a6,0x1a7", 854 "MSRValue": "0x2000400001", 855 "Offcore": "1", 856 "PublicDescription": "Counts demand data reads", 857 "SampleAfterValue": "100003", 858 "UMask": "0x1" 859 }, 860 { 861 "BriefDescription": "Counts any other requests", 862 "Counter": "0,1,2,3", 863 "CounterHTOff": "0,1,2,3", 864 "EventCode": "0xB7, 0xBB", 865 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", 866 "MSRIndex": "0x1a6,0x1a7", 867 "MSRValue": "0x013C408000", 868 "Offcore": "1", 869 "PublicDescription": "Counts any other requests", 870 "SampleAfterValue": "100003", 871 "UMask": "0x1" 872 }, 873 { 874 "BriefDescription": "Number of times an HLE execution successfully committed", 875 "Counter": "0,1,2,3", 876 "CounterHTOff": "0,1,2,3,4,5,6,7", 877 "EventCode": "0xC8", 878 "EventName": "HLE_RETIRED.COMMIT", 879 "PublicDescription": "Number of times HLE commit succeeded.", 880 "SampleAfterValue": "2000003", 881 "UMask": "0x2" 882 }, 883 { 884 "BriefDescription": "Counts demand data reads", 885 "Counter": "0,1,2,3", 886 "CounterHTOff": "0,1,2,3", 887 "EventCode": "0xB7, 0xBB", 888 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 889 "MSRIndex": "0x1a6,0x1a7", 890 "MSRValue": "0x2000020001", 891 "Offcore": "1", 892 "PublicDescription": "Counts demand data reads", 893 "SampleAfterValue": "100003", 894 "UMask": "0x1" 895 }, 896 { 897 "BriefDescription": "Counts any other requests", 898 "Counter": "0,1,2,3", 899 "CounterHTOff": "0,1,2,3", 900 "EventCode": "0xB7, 0xBB", 901 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", 902 "MSRIndex": "0x1a6,0x1a7", 903 "MSRValue": "0x203C408000", 904 "Offcore": "1", 905 "PublicDescription": "Counts any other requests", 906 "SampleAfterValue": "100003", 907 "UMask": "0x1" 908 }, 909 { 910 "BriefDescription": "Counts all demand data writes (RFOs)", 911 "Counter": "0,1,2,3", 912 "CounterHTOff": "0,1,2,3", 913 "EventCode": "0xB7, 0xBB", 914 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", 915 "MSRIndex": "0x1a6,0x1a7", 916 "MSRValue": "0x023C400002", 917 "Offcore": "1", 918 "PublicDescription": "Counts all demand data writes (RFOs)", 919 "SampleAfterValue": "100003", 920 "UMask": "0x1" 921 }, 922 { 923 "BriefDescription": "Counts all demand data writes (RFOs)", 924 "Counter": "0,1,2,3", 925 "CounterHTOff": "0,1,2,3", 926 "EventCode": "0xB7, 0xBB", 927 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM", 928 "MSRIndex": "0x1a6,0x1a7", 929 "MSRValue": "0x2000040002", 930 "Offcore": "1", 931 "PublicDescription": "Counts all demand data writes (RFOs)", 932 "SampleAfterValue": "100003", 933 "UMask": "0x1" 934 }, 935 { 936 "BriefDescription": "Demand Data Read requests who miss L3 cache", 937 "Counter": "0,1,2,3", 938 "CounterHTOff": "0,1,2,3,4,5,6,7", 939 "EventCode": "0xB0", 940 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 941 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 942 "SampleAfterValue": "100003", 943 "UMask": "0x10" 944 }, 945 { 946 "BriefDescription": "Counts demand data reads", 947 "Counter": "0,1,2,3", 948 "CounterHTOff": "0,1,2,3", 949 "EventCode": "0xB7, 0xBB", 950 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 951 "MSRIndex": "0x1a6,0x1a7", 952 "MSRValue": "0x00BC400001", 953 "Offcore": "1", 954 "PublicDescription": "Counts demand data reads", 955 "SampleAfterValue": "100003", 956 "UMask": "0x1" 957 }, 958 { 959 "BriefDescription": "Counts all demand data writes (RFOs)", 960 "Counter": "0,1,2,3", 961 "CounterHTOff": "0,1,2,3", 962 "EventCode": "0xB7, 0xBB", 963 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 964 "MSRIndex": "0x1a6,0x1a7", 965 "MSRValue": "0x2004000002", 966 "Offcore": "1", 967 "PublicDescription": "Counts all demand data writes (RFOs)", 968 "SampleAfterValue": "100003", 969 "UMask": "0x1" 970 }, 971 { 972 "BriefDescription": "Counts all demand code reads", 973 "Counter": "0,1,2,3", 974 "CounterHTOff": "0,1,2,3", 975 "EventCode": "0xB7, 0xBB", 976 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 977 "MSRIndex": "0x1a6,0x1a7", 978 "MSRValue": "0x023C400004", 979 "Offcore": "1", 980 "PublicDescription": "Counts all demand code reads", 981 "SampleAfterValue": "100003", 982 "UMask": "0x1" 983 }, 984 { 985 "BriefDescription": "Counts demand data reads", 986 "Counter": "0,1,2,3", 987 "CounterHTOff": "0,1,2,3", 988 "EventCode": "0xB7, 0xBB", 989 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 990 "MSRIndex": "0x1a6,0x1a7", 991 "MSRValue": "0x3FFC400001", 992 "Offcore": "1", 993 "PublicDescription": "Counts demand data reads", 994 "SampleAfterValue": "100003", 995 "UMask": "0x1" 996 }, 997 { 998 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 999 "Counter": "0,1,2,3", 1000 "CounterHTOff": "0,1,2,3,4,5,6,7", 1001 "EventCode": "0xC9", 1002 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 1003 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 1004 "SampleAfterValue": "2000003", 1005 "UMask": "0x20" 1006 }, 1007 { 1008 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 1009 "Counter": "0,1,2,3", 1010 "CounterHTOff": "0,1,2,3,4,5,6,7", 1011 "EventCode": "0xC8", 1012 "EventName": "HLE_RETIRED.ABORTED_MEM", 1013 "SampleAfterValue": "2000003", 1014 "UMask": "0x8" 1015 }, 1016 { 1017 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 1018 "Counter": "0,1,2,3", 1019 "CounterHTOff": "0,1,2,3", 1020 "Data_LA": "1", 1021 "EventCode": "0xcd", 1022 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 1023 "MSRIndex": "0x3F6", 1024 "MSRValue": "0x100", 1025 "PEBS": "2", 1026 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 1027 "SampleAfterValue": "503", 1028 "TakenAlone": "1", 1029 "UMask": "0x1" 1030 }, 1031 { 1032 "BriefDescription": "Counts demand data reads", 1033 "Counter": "0,1,2,3", 1034 "CounterHTOff": "0,1,2,3", 1035 "EventCode": "0xB7, 0xBB", 1036 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 1037 "MSRIndex": "0x1a6,0x1a7", 1038 "MSRValue": "0x013C400001", 1039 "Offcore": "1", 1040 "PublicDescription": "Counts demand data reads", 1041 "SampleAfterValue": "100003", 1042 "UMask": "0x1" 1043 }, 1044 { 1045 "BriefDescription": "Counts demand data reads", 1046 "Counter": "0,1,2,3", 1047 "CounterHTOff": "0,1,2,3", 1048 "EventCode": "0xB7, 0xBB", 1049 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM", 1050 "MSRIndex": "0x1a6,0x1a7", 1051 "MSRValue": "0x203C400001", 1052 "Offcore": "1", 1053 "PublicDescription": "Counts demand data reads", 1054 "SampleAfterValue": "100003", 1055 "UMask": "0x1" 1056 }, 1057 { 1058 "BriefDescription": "Counts all demand data writes (RFOs)", 1059 "Counter": "0,1,2,3", 1060 "CounterHTOff": "0,1,2,3", 1061 "EventCode": "0xB7, 0xBB", 1062 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT", 1063 "MSRIndex": "0x1a6,0x1a7", 1064 "MSRValue": "0x007C400002", 1065 "Offcore": "1", 1066 "PublicDescription": "Counts all demand data writes (RFOs)", 1067 "SampleAfterValue": "100003", 1068 "UMask": "0x1" 1069 }, 1070 { 1071 "BriefDescription": "Counts any other requests", 1072 "Counter": "0,1,2,3", 1073 "CounterHTOff": "0,1,2,3", 1074 "EventCode": "0xB7, 0xBB", 1075 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1076 "MSRIndex": "0x1a6,0x1a7", 1077 "MSRValue": "0x3FC4008000", 1078 "Offcore": "1", 1079 "PublicDescription": "Counts any other requests", 1080 "SampleAfterValue": "100003", 1081 "UMask": "0x1" 1082 }, 1083 { 1084 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 1085 "Counter": "0,1,2,3", 1086 "CounterHTOff": "0,1,2,3,4,5,6,7", 1087 "EventCode": "0xC9", 1088 "EventName": "RTM_RETIRED.ABORTED", 1089 "PEBS": "1", 1090 "PublicDescription": "Number of times RTM abort was triggered.", 1091 "SampleAfterValue": "2000003", 1092 "UMask": "0x4" 1093 }, 1094 { 1095 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 1096 "Counter": "0,1,2,3", 1097 "CounterHTOff": "0,1,2,3,4,5,6,7", 1098 "EventCode": "0xC8", 1099 "EventName": "HLE_RETIRED.ABORTED", 1100 "PEBS": "1", 1101 "PublicDescription": "Number of times HLE abort was triggered.", 1102 "SampleAfterValue": "2000003", 1103 "UMask": "0x4" 1104 }, 1105 { 1106 "BriefDescription": "Counts all demand data writes (RFOs)", 1107 "Counter": "0,1,2,3", 1108 "CounterHTOff": "0,1,2,3", 1109 "EventCode": "0xB7, 0xBB", 1110 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM", 1111 "MSRIndex": "0x1a6,0x1a7", 1112 "MSRValue": "0x203C400002", 1113 "Offcore": "1", 1114 "PublicDescription": "Counts all demand data writes (RFOs)", 1115 "SampleAfterValue": "100003", 1116 "UMask": "0x1" 1117 }, 1118 { 1119 "BriefDescription": "Counts all demand code reads", 1120 "Counter": "0,1,2,3", 1121 "CounterHTOff": "0,1,2,3", 1122 "EventCode": "0xB7, 0xBB", 1123 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1124 "MSRIndex": "0x1a6,0x1a7", 1125 "MSRValue": "0x0404000004", 1126 "Offcore": "1", 1127 "PublicDescription": "Counts all demand code reads", 1128 "SampleAfterValue": "100003", 1129 "UMask": "0x1" 1130 }, 1131 { 1132 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 1133 "Counter": "0,1,2,3", 1134 "CounterHTOff": "0,1,2,3", 1135 "Data_LA": "1", 1136 "EventCode": "0xcd", 1137 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 1138 "MSRIndex": "0x3F6", 1139 "MSRValue": "0x10", 1140 "PEBS": "2", 1141 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 1142 "SampleAfterValue": "20011", 1143 "TakenAlone": "1", 1144 "UMask": "0x1" 1145 }, 1146 { 1147 "BriefDescription": "Counts any other requests", 1148 "Counter": "0,1,2,3", 1149 "CounterHTOff": "0,1,2,3", 1150 "EventCode": "0xB7, 0xBB", 1151 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1152 "MSRIndex": "0x1a6,0x1a7", 1153 "MSRValue": "0x2004008000", 1154 "Offcore": "1", 1155 "PublicDescription": "Counts any other requests", 1156 "SampleAfterValue": "100003", 1157 "UMask": "0x1" 1158 }, 1159 { 1160 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 1161 "Counter": "0,1,2,3", 1162 "CounterHTOff": "0,1,2,3,4,5,6,7", 1163 "EventCode": "0x54", 1164 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 1165 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 1166 "SampleAfterValue": "2000003", 1167 "UMask": "0x20" 1168 }, 1169 { 1170 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 1171 "Counter": "0,1,2,3", 1172 "CounterHTOff": "0,1,2,3,4,5,6,7", 1173 "CounterMask": "1", 1174 "EventCode": "0x60", 1175 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 1176 "SampleAfterValue": "2000003", 1177 "UMask": "0x10" 1178 }, 1179 { 1180 "BriefDescription": "Counts all demand code reads", 1181 "Counter": "0,1,2,3", 1182 "CounterHTOff": "0,1,2,3", 1183 "EventCode": "0xB7, 0xBB", 1184 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1185 "MSRIndex": "0x1a6,0x1a7", 1186 "MSRValue": "0x3FC4000004", 1187 "Offcore": "1", 1188 "PublicDescription": "Counts all demand code reads", 1189 "SampleAfterValue": "100003", 1190 "UMask": "0x1" 1191 }, 1192 { 1193 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 1194 "Counter": "0,1,2,3", 1195 "CounterHTOff": "0,1,2,3", 1196 "Data_LA": "1", 1197 "EventCode": "0xcd", 1198 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 1199 "MSRIndex": "0x3F6", 1200 "MSRValue": "0x200", 1201 "PEBS": "2", 1202 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 1203 "SampleAfterValue": "101", 1204 "TakenAlone": "1", 1205 "UMask": "0x1" 1206 }, 1207 { 1208 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 1209 "Counter": "0,1,2,3", 1210 "CounterHTOff": "0,1,2,3,4,5,6,7", 1211 "EventCode": "0x54", 1212 "EventName": "TX_MEM.ABORT_CAPACITY", 1213 "SampleAfterValue": "2000003", 1214 "UMask": "0x2" 1215 }, 1216 { 1217 "BriefDescription": "Counts demand data reads", 1218 "Counter": "0,1,2,3", 1219 "CounterHTOff": "0,1,2,3", 1220 "EventCode": "0xB7, 0xBB", 1221 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1222 "MSRIndex": "0x1a6,0x1a7", 1223 "MSRValue": "0x0084000001", 1224 "Offcore": "1", 1225 "PublicDescription": "Counts demand data reads", 1226 "SampleAfterValue": "100003", 1227 "UMask": "0x1" 1228 }, 1229 { 1230 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 1231 "Counter": "0,1,2,3", 1232 "CounterHTOff": "0,1,2,3,4,5,6,7", 1233 "EventCode": "0xC8", 1234 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 1235 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 1236 "SampleAfterValue": "2000003", 1237 "UMask": "0x40" 1238 }, 1239 { 1240 "BriefDescription": "Number of times an RTM execution started.", 1241 "Counter": "0,1,2,3", 1242 "CounterHTOff": "0,1,2,3,4,5,6,7", 1243 "EventCode": "0xC9", 1244 "EventName": "RTM_RETIRED.START", 1245 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 1246 "SampleAfterValue": "2000003", 1247 "UMask": "0x1" 1248 }, 1249 { 1250 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 1251 "Counter": "0,1,2,3", 1252 "CounterHTOff": "0,1,2,3,4,5,6,7", 1253 "Errata": "SKL089", 1254 "EventCode": "0xC3", 1255 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 1256 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 1257 "SampleAfterValue": "100003", 1258 "UMask": "0x2" 1259 }, 1260 { 1261 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 1262 "Counter": "0,1,2,3", 1263 "CounterHTOff": "0,1,2,3,4,5,6,7", 1264 "EventCode": "0x54", 1265 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 1266 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 1267 "SampleAfterValue": "2000003", 1268 "UMask": "0x10" 1269 }, 1270 { 1271 "BriefDescription": "Counts all demand data writes (RFOs)", 1272 "Counter": "0,1,2,3", 1273 "CounterHTOff": "0,1,2,3", 1274 "EventCode": "0xB7, 0xBB", 1275 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", 1276 "MSRIndex": "0x1a6,0x1a7", 1277 "MSRValue": "0x20001C0002", 1278 "Offcore": "1", 1279 "PublicDescription": "Counts all demand data writes (RFOs)", 1280 "SampleAfterValue": "100003", 1281 "UMask": "0x1" 1282 }, 1283 { 1284 "BriefDescription": "Counts all demand data writes (RFOs)", 1285 "Counter": "0,1,2,3", 1286 "CounterHTOff": "0,1,2,3", 1287 "EventCode": "0xB7, 0xBB", 1288 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1289 "MSRIndex": "0x1a6,0x1a7", 1290 "MSRValue": "0x1004000002", 1291 "Offcore": "1", 1292 "PublicDescription": "Counts all demand data writes (RFOs)", 1293 "SampleAfterValue": "100003", 1294 "UMask": "0x1" 1295 }, 1296 { 1297 "BriefDescription": "Counts demand data reads", 1298 "Counter": "0,1,2,3", 1299 "CounterHTOff": "0,1,2,3", 1300 "EventCode": "0xB7, 0xBB", 1301 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 1302 "MSRIndex": "0x1a6,0x1a7", 1303 "MSRValue": "0x20001C0001", 1304 "Offcore": "1", 1305 "PublicDescription": "Counts demand data reads", 1306 "SampleAfterValue": "100003", 1307 "UMask": "0x1" 1308 }, 1309 { 1310 "BriefDescription": "Counts all demand data writes (RFOs)", 1311 "Counter": "0,1,2,3", 1312 "CounterHTOff": "0,1,2,3", 1313 "EventCode": "0xB7, 0xBB", 1314 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1315 "MSRIndex": "0x1a6,0x1a7", 1316 "MSRValue": "0x3FC4000002", 1317 "Offcore": "1", 1318 "PublicDescription": "Counts all demand data writes (RFOs)", 1319 "SampleAfterValue": "100003", 1320 "UMask": "0x1" 1321 }, 1322 { 1323 "BriefDescription": "Counts demand data reads", 1324 "Counter": "0,1,2,3", 1325 "CounterHTOff": "0,1,2,3", 1326 "EventCode": "0xB7, 0xBB", 1327 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT", 1328 "MSRIndex": "0x1a6,0x1a7", 1329 "MSRValue": "0x007C400001", 1330 "Offcore": "1", 1331 "PublicDescription": "Counts demand data reads", 1332 "SampleAfterValue": "100003", 1333 "UMask": "0x1" 1334 }, 1335 { 1336 "BriefDescription": "Counts all demand code reads", 1337 "Counter": "0,1,2,3", 1338 "CounterHTOff": "0,1,2,3", 1339 "EventCode": "0xB7, 0xBB", 1340 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM", 1341 "MSRIndex": "0x1a6,0x1a7", 1342 "MSRValue": "0x2000100004", 1343 "Offcore": "1", 1344 "PublicDescription": "Counts all demand code reads", 1345 "SampleAfterValue": "100003", 1346 "UMask": "0x1" 1347 }, 1348 { 1349 "BriefDescription": "Counts all demand code reads", 1350 "Counter": "0,1,2,3", 1351 "CounterHTOff": "0,1,2,3", 1352 "EventCode": "0xB7, 0xBB", 1353 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 1354 "MSRIndex": "0x1a6,0x1a7", 1355 "MSRValue": "0x00BC400004", 1356 "Offcore": "1", 1357 "PublicDescription": "Counts all demand code reads", 1358 "SampleAfterValue": "100003", 1359 "UMask": "0x1" 1360 }, 1361 { 1362 "BriefDescription": "Counts demand data reads", 1363 "Counter": "0,1,2,3", 1364 "CounterHTOff": "0,1,2,3", 1365 "EventCode": "0xB7, 0xBB", 1366 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1367 "MSRIndex": "0x1a6,0x1a7", 1368 "MSRValue": "0x043C400001", 1369 "Offcore": "1", 1370 "PublicDescription": "Counts demand data reads", 1371 "SampleAfterValue": "100003", 1372 "UMask": "0x1" 1373 }, 1374 { 1375 "BriefDescription": "Counts all demand data writes (RFOs)", 1376 "Counter": "0,1,2,3", 1377 "CounterHTOff": "0,1,2,3", 1378 "EventCode": "0xB7, 0xBB", 1379 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 1380 "MSRIndex": "0x1a6,0x1a7", 1381 "MSRValue": "0x3FFC400002", 1382 "Offcore": "1", 1383 "PublicDescription": "Counts all demand data writes (RFOs)", 1384 "SampleAfterValue": "100003", 1385 "UMask": "0x1" 1386 }, 1387 { 1388 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 1389 "Counter": "0,1,2,3", 1390 "CounterHTOff": "0,1,2,3,4,5,6,7", 1391 "EventCode": "0xC9", 1392 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 1393 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 1394 "SampleAfterValue": "2000003", 1395 "UMask": "0x80" 1396 }, 1397 { 1398 "BriefDescription": "Number of times an HLE execution started.", 1399 "Counter": "0,1,2,3", 1400 "CounterHTOff": "0,1,2,3,4,5,6,7", 1401 "EventCode": "0xC8", 1402 "EventName": "HLE_RETIRED.START", 1403 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 1404 "SampleAfterValue": "2000003", 1405 "UMask": "0x1" 1406 }, 1407 { 1408 "BriefDescription": "Counts all demand code reads", 1409 "Counter": "0,1,2,3", 1410 "CounterHTOff": "0,1,2,3", 1411 "EventCode": "0xB7, 0xBB", 1412 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 1413 "MSRIndex": "0x1a6,0x1a7", 1414 "MSRValue": "0x3FFC400004", 1415 "Offcore": "1", 1416 "PublicDescription": "Counts all demand code reads", 1417 "SampleAfterValue": "100003", 1418 "UMask": "0x1" 1419 }, 1420 { 1421 "BriefDescription": "Counts demand data reads", 1422 "Counter": "0,1,2,3", 1423 "CounterHTOff": "0,1,2,3", 1424 "EventCode": "0xB7, 0xBB", 1425 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1426 "MSRIndex": "0x1a6,0x1a7", 1427 "MSRValue": "0x2004000001", 1428 "Offcore": "1", 1429 "PublicDescription": "Counts demand data reads", 1430 "SampleAfterValue": "100003", 1431 "UMask": "0x1" 1432 }, 1433 { 1434 "BriefDescription": "Counts demand data reads", 1435 "Counter": "0,1,2,3", 1436 "CounterHTOff": "0,1,2,3", 1437 "EventCode": "0xB7, 0xBB", 1438 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1439 "MSRIndex": "0x1a6,0x1a7", 1440 "MSRValue": "0x3FC4000001", 1441 "Offcore": "1", 1442 "PublicDescription": "Counts demand data reads", 1443 "SampleAfterValue": "100003", 1444 "UMask": "0x1" 1445 }, 1446 { 1447 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 1448 "Counter": "0,1,2,3", 1449 "CounterHTOff": "0,1,2,3", 1450 "Data_LA": "1", 1451 "EventCode": "0xcd", 1452 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 1453 "MSRIndex": "0x3F6", 1454 "MSRValue": "0x80", 1455 "PEBS": "2", 1456 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 1457 "SampleAfterValue": "1009", 1458 "TakenAlone": "1", 1459 "UMask": "0x1" 1460 }, 1461 { 1462 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 1463 "Counter": "0,1,2,3", 1464 "CounterHTOff": "0,1,2,3,4,5,6,7", 1465 "EventCode": "0x54", 1466 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 1467 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 1468 "SampleAfterValue": "2000003", 1469 "UMask": "0x40" 1470 }, 1471 { 1472 "BriefDescription": "Counts any other requests", 1473 "Counter": "0,1,2,3", 1474 "CounterHTOff": "0,1,2,3", 1475 "EventCode": "0xB7, 0xBB", 1476 "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM", 1477 "MSRIndex": "0x1a6,0x1a7", 1478 "MSRValue": "0x2000108000", 1479 "Offcore": "1", 1480 "PublicDescription": "Counts any other requests", 1481 "SampleAfterValue": "100003", 1482 "UMask": "0x1" 1483 }, 1484 { 1485 "BriefDescription": "Counts all demand code reads", 1486 "Counter": "0,1,2,3", 1487 "CounterHTOff": "0,1,2,3", 1488 "EventCode": "0xB7, 0xBB", 1489 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", 1490 "MSRIndex": "0x1a6,0x1a7", 1491 "MSRValue": "0x0044000004", 1492 "Offcore": "1", 1493 "PublicDescription": "Counts all demand code reads", 1494 "SampleAfterValue": "100003", 1495 "UMask": "0x1" 1496 }, 1497 { 1498 "BriefDescription": "Counts all demand data writes (RFOs)", 1499 "Counter": "0,1,2,3", 1500 "CounterHTOff": "0,1,2,3", 1501 "EventCode": "0xB7, 0xBB", 1502 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED", 1503 "MSRIndex": "0x1a6,0x1a7", 1504 "MSRValue": "0x013C400002", 1505 "Offcore": "1", 1506 "PublicDescription": "Counts all demand data writes (RFOs)", 1507 "SampleAfterValue": "100003", 1508 "UMask": "0x1" 1509 }, 1510 { 1511 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 1512 "Counter": "0,1,2,3", 1513 "CounterHTOff": "0,1,2,3,4,5,6,7", 1514 "CounterMask": "6", 1515 "EventCode": "0xA3", 1516 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 1517 "SampleAfterValue": "2000003", 1518 "UMask": "0x6" 1519 }, 1520 { 1521 "BriefDescription": "Counts any other requests", 1522 "Counter": "0,1,2,3", 1523 "CounterHTOff": "0,1,2,3", 1524 "EventCode": "0xB7, 0xBB", 1525 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", 1526 "MSRIndex": "0x1a6,0x1a7", 1527 "MSRValue": "0x023C408000", 1528 "Offcore": "1", 1529 "PublicDescription": "Counts any other requests", 1530 "SampleAfterValue": "100003", 1531 "UMask": "0x1" 1532 }, 1533 { 1534 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 1535 "Counter": "0,1,2,3", 1536 "CounterHTOff": "0,1,2,3,4,5,6,7", 1537 "EventCode": "0xC8", 1538 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 1539 "SampleAfterValue": "2000003", 1540 "UMask": "0x80" 1541 }, 1542 { 1543 "BriefDescription": "Counts any other requests", 1544 "Counter": "0,1,2,3", 1545 "CounterHTOff": "0,1,2,3", 1546 "EventCode": "0xB7, 0xBB", 1547 "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", 1548 "MSRIndex": "0x1a6,0x1a7", 1549 "MSRValue": "0x20001C8000", 1550 "Offcore": "1", 1551 "PublicDescription": "Counts any other requests", 1552 "SampleAfterValue": "100003", 1553 "UMask": "0x1" 1554 }, 1555 { 1556 "BriefDescription": "Counts demand data reads", 1557 "Counter": "0,1,2,3", 1558 "CounterHTOff": "0,1,2,3", 1559 "EventCode": "0xB7, 0xBB", 1560 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM", 1561 "MSRIndex": "0x1a6,0x1a7", 1562 "MSRValue": "0x2000040001", 1563 "Offcore": "1", 1564 "PublicDescription": "Counts demand data reads", 1565 "SampleAfterValue": "100003", 1566 "UMask": "0x1" 1567 }, 1568 { 1569 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 1570 "Counter": "0,1,2,3", 1571 "CounterHTOff": "0,1,2,3", 1572 "Data_LA": "1", 1573 "EventCode": "0xcd", 1574 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 1575 "MSRIndex": "0x3F6", 1576 "MSRValue": "0x4", 1577 "PEBS": "2", 1578 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 1579 "SampleAfterValue": "100003", 1580 "TakenAlone": "1", 1581 "UMask": "0x1" 1582 }, 1583 { 1584 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 1585 "Counter": "0,1,2,3", 1586 "CounterHTOff": "0,1,2,3", 1587 "Data_LA": "1", 1588 "EventCode": "0xcd", 1589 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 1590 "MSRIndex": "0x3F6", 1591 "MSRValue": "0x8", 1592 "PEBS": "2", 1593 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 1594 "SampleAfterValue": "50021", 1595 "TakenAlone": "1", 1596 "UMask": "0x1" 1597 }, 1598 { 1599 "BriefDescription": "Counts all demand data writes (RFOs)", 1600 "Counter": "0,1,2,3", 1601 "CounterHTOff": "0,1,2,3", 1602 "EventCode": "0xB7, 0xBB", 1603 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1604 "MSRIndex": "0x1a6,0x1a7", 1605 "MSRValue": "0x0404000002", 1606 "Offcore": "1", 1607 "PublicDescription": "Counts all demand data writes (RFOs)", 1608 "SampleAfterValue": "100003", 1609 "UMask": "0x1" 1610 } 1611]