14e411ee4SZhengjun Xing[
24e411ee4SZhengjun Xing    {
34e411ee4SZhengjun Xing        "BriefDescription": "PCU PCLK Clockticks",
44e411ee4SZhengjun Xing        "EventCode": "0x01",
54e411ee4SZhengjun Xing        "EventName": "UNC_P_CLOCKTICKS",
64e411ee4SZhengjun Xing        "PerPkg": "1",
7400dd489SIan Rogers        "PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled",
8400dd489SIan Rogers        "Unit": "PCU"
9400dd489SIan Rogers    },
10400dd489SIan Rogers    {
11*54f5de6fSIan Rogers        "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
12*54f5de6fSIan Rogers        "EventCode": "0x60",
13*54f5de6fSIan Rogers        "EventName": "UNC_P_CORE_TRANSITION_CYCLES",
14*54f5de6fSIan Rogers        "PerPkg": "1",
15*54f5de6fSIan Rogers        "Unit": "PCU"
16*54f5de6fSIan Rogers    },
17*54f5de6fSIan Rogers    {
18*54f5de6fSIan Rogers        "BriefDescription": "UNC_P_DEMOTIONS",
19*54f5de6fSIan Rogers        "EventCode": "0x30",
20*54f5de6fSIan Rogers        "EventName": "UNC_P_DEMOTIONS",
21*54f5de6fSIan Rogers        "PerPkg": "1",
22*54f5de6fSIan Rogers        "Unit": "PCU"
23*54f5de6fSIan Rogers    },
24*54f5de6fSIan Rogers    {
25*54f5de6fSIan Rogers        "BriefDescription": "Phase Shed 0 Cycles",
26*54f5de6fSIan Rogers        "EventCode": "0x75",
27*54f5de6fSIan Rogers        "EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
28*54f5de6fSIan Rogers        "PerPkg": "1",
29*54f5de6fSIan Rogers        "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
30*54f5de6fSIan Rogers        "Unit": "PCU"
31*54f5de6fSIan Rogers    },
32*54f5de6fSIan Rogers    {
33*54f5de6fSIan Rogers        "BriefDescription": "Phase Shed 1 Cycles",
34*54f5de6fSIan Rogers        "EventCode": "0x76",
35*54f5de6fSIan Rogers        "EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
36*54f5de6fSIan Rogers        "PerPkg": "1",
37*54f5de6fSIan Rogers        "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
38*54f5de6fSIan Rogers        "Unit": "PCU"
39*54f5de6fSIan Rogers    },
40*54f5de6fSIan Rogers    {
41*54f5de6fSIan Rogers        "BriefDescription": "Phase Shed 2 Cycles",
42*54f5de6fSIan Rogers        "EventCode": "0x77",
43*54f5de6fSIan Rogers        "EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
44*54f5de6fSIan Rogers        "PerPkg": "1",
45*54f5de6fSIan Rogers        "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
46*54f5de6fSIan Rogers        "Unit": "PCU"
47*54f5de6fSIan Rogers    },
48*54f5de6fSIan Rogers    {
49*54f5de6fSIan Rogers        "BriefDescription": "Phase Shed 3 Cycles",
50*54f5de6fSIan Rogers        "EventCode": "0x78",
51*54f5de6fSIan Rogers        "EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
52*54f5de6fSIan Rogers        "PerPkg": "1",
53*54f5de6fSIan Rogers        "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
54*54f5de6fSIan Rogers        "Unit": "PCU"
55*54f5de6fSIan Rogers    },
56*54f5de6fSIan Rogers    {
57*54f5de6fSIan Rogers        "BriefDescription": "AVX256 Frequency Clipping",
58*54f5de6fSIan Rogers        "EventCode": "0x49",
59*54f5de6fSIan Rogers        "EventName": "UNC_P_FREQ_CLIP_AVX256",
60*54f5de6fSIan Rogers        "PerPkg": "1",
61*54f5de6fSIan Rogers        "Unit": "PCU"
62*54f5de6fSIan Rogers    },
63*54f5de6fSIan Rogers    {
64*54f5de6fSIan Rogers        "BriefDescription": "AVX512 Frequency Clipping",
65*54f5de6fSIan Rogers        "EventCode": "0x4a",
66*54f5de6fSIan Rogers        "EventName": "UNC_P_FREQ_CLIP_AVX512",
67*54f5de6fSIan Rogers        "PerPkg": "1",
68*54f5de6fSIan Rogers        "Unit": "PCU"
69*54f5de6fSIan Rogers    },
70*54f5de6fSIan Rogers    {
71400dd489SIan Rogers        "BriefDescription": "Thermal Strongest Upper Limit Cycles",
72400dd489SIan Rogers        "EventCode": "0x04",
73400dd489SIan Rogers        "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
74400dd489SIan Rogers        "PerPkg": "1",
75400dd489SIan Rogers        "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit.  Count only if throttling is occurring.",
76400dd489SIan Rogers        "Unit": "PCU"
77400dd489SIan Rogers    },
78400dd489SIan Rogers    {
79400dd489SIan Rogers        "BriefDescription": "Power Strongest Upper Limit Cycles",
80400dd489SIan Rogers        "EventCode": "0x05",
81400dd489SIan Rogers        "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
82400dd489SIan Rogers        "PerPkg": "1",
83400dd489SIan Rogers        "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
84400dd489SIan Rogers        "Unit": "PCU"
85400dd489SIan Rogers    },
86400dd489SIan Rogers    {
87*54f5de6fSIan Rogers        "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
88*54f5de6fSIan Rogers        "EventCode": "0x73",
89*54f5de6fSIan Rogers        "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
90*54f5de6fSIan Rogers        "PerPkg": "1",
91*54f5de6fSIan Rogers        "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
92*54f5de6fSIan Rogers        "Unit": "PCU"
93*54f5de6fSIan Rogers    },
94*54f5de6fSIan Rogers    {
95400dd489SIan Rogers        "BriefDescription": "Cycles spent changing Frequency",
96400dd489SIan Rogers        "EventCode": "0x74",
97400dd489SIan Rogers        "EventName": "UNC_P_FREQ_TRANS_CYCLES",
98400dd489SIan Rogers        "PerPkg": "1",
99400dd489SIan Rogers        "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
100400dd489SIan Rogers        "Unit": "PCU"
101400dd489SIan Rogers    },
102400dd489SIan Rogers    {
103*54f5de6fSIan Rogers        "BriefDescription": "Memory Phase Shedding Cycles",
104*54f5de6fSIan Rogers        "EventCode": "0x2f",
105*54f5de6fSIan Rogers        "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
106*54f5de6fSIan Rogers        "PerPkg": "1",
107*54f5de6fSIan Rogers        "PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
108*54f5de6fSIan Rogers        "Unit": "PCU"
109*54f5de6fSIan Rogers    },
110*54f5de6fSIan Rogers    {
111*54f5de6fSIan Rogers        "BriefDescription": "Package C State Residency - C0",
112*54f5de6fSIan Rogers        "EventCode": "0x2a",
113*54f5de6fSIan Rogers        "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
114*54f5de6fSIan Rogers        "PerPkg": "1",
115*54f5de6fSIan Rogers        "PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
116*54f5de6fSIan Rogers        "Unit": "PCU"
117*54f5de6fSIan Rogers    },
118*54f5de6fSIan Rogers    {
119400dd489SIan Rogers        "BriefDescription": "Package C State Residency - C2E",
120400dd489SIan Rogers        "EventCode": "0x2b",
121400dd489SIan Rogers        "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
122400dd489SIan Rogers        "PerPkg": "1",
123400dd489SIan Rogers        "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
124400dd489SIan Rogers        "Unit": "PCU"
125400dd489SIan Rogers    },
126400dd489SIan Rogers    {
127400dd489SIan Rogers        "BriefDescription": "Package C State Residency - C6",
128400dd489SIan Rogers        "EventCode": "0x2d",
129400dd489SIan Rogers        "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
130400dd489SIan Rogers        "PerPkg": "1",
131400dd489SIan Rogers        "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
132400dd489SIan Rogers        "Unit": "PCU"
133400dd489SIan Rogers    },
134400dd489SIan Rogers    {
135*54f5de6fSIan Rogers        "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
136*54f5de6fSIan Rogers        "EventCode": "0x06",
137*54f5de6fSIan Rogers        "EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
138*54f5de6fSIan Rogers        "PerPkg": "1",
139*54f5de6fSIan Rogers        "Unit": "PCU"
140*54f5de6fSIan Rogers    },
141*54f5de6fSIan Rogers    {
142400dd489SIan Rogers        "BriefDescription": "Number of cores in C0",
143400dd489SIan Rogers        "EventCode": "0x35",
144400dd489SIan Rogers        "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0",
145400dd489SIan Rogers        "PerPkg": "1",
146400dd489SIan Rogers        "PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
147400dd489SIan Rogers        "Unit": "PCU"
148400dd489SIan Rogers    },
149400dd489SIan Rogers    {
150400dd489SIan Rogers        "BriefDescription": "Number of cores in C3",
151400dd489SIan Rogers        "EventCode": "0x36",
152400dd489SIan Rogers        "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C3",
153400dd489SIan Rogers        "PerPkg": "1",
154400dd489SIan Rogers        "PublicDescription": "Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
155400dd489SIan Rogers        "Unit": "PCU"
156400dd489SIan Rogers    },
157400dd489SIan Rogers    {
158400dd489SIan Rogers        "BriefDescription": "Number of cores in C6",
159400dd489SIan Rogers        "EventCode": "0x37",
160400dd489SIan Rogers        "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6",
161400dd489SIan Rogers        "PerPkg": "1",
162400dd489SIan Rogers        "PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
163400dd489SIan Rogers        "Unit": "PCU"
164400dd489SIan Rogers    },
165400dd489SIan Rogers    {
166400dd489SIan Rogers        "BriefDescription": "External Prochot",
167400dd489SIan Rogers        "EventCode": "0x0a",
168400dd489SIan Rogers        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
169400dd489SIan Rogers        "PerPkg": "1",
170400dd489SIan Rogers        "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
171400dd489SIan Rogers        "Unit": "PCU"
172400dd489SIan Rogers    },
173400dd489SIan Rogers    {
174400dd489SIan Rogers        "BriefDescription": "Internal Prochot",
175400dd489SIan Rogers        "EventCode": "0x09",
176400dd489SIan Rogers        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
177400dd489SIan Rogers        "PerPkg": "1",
178400dd489SIan Rogers        "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
1794e411ee4SZhengjun Xing        "Unit": "PCU"
180*54f5de6fSIan Rogers    },
181*54f5de6fSIan Rogers    {
182*54f5de6fSIan Rogers        "BriefDescription": "Total Core C State Transition Cycles",
183*54f5de6fSIan Rogers        "EventCode": "0x72",
184*54f5de6fSIan Rogers        "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
185*54f5de6fSIan Rogers        "PerPkg": "1",
186*54f5de6fSIan Rogers        "PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.",
187*54f5de6fSIan Rogers        "Unit": "PCU"
188*54f5de6fSIan Rogers    },
189*54f5de6fSIan Rogers    {
190*54f5de6fSIan Rogers        "BriefDescription": "VR Hot",
191*54f5de6fSIan Rogers        "EventCode": "0x42",
192*54f5de6fSIan Rogers        "EventName": "UNC_P_VR_HOT_CYCLES",
193*54f5de6fSIan Rogers        "PerPkg": "1",
194*54f5de6fSIan Rogers        "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot.  Does not cover DRAM VRs",
195*54f5de6fSIan Rogers        "Unit": "PCU"
1964e411ee4SZhengjun Xing    }
1974e411ee4SZhengjun Xing]
198